1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 2; RUN: %if x86-registered-target %{ opt -S -passes=slp-vectorizer -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck %s %} 3; RUN: %if aarch64-registered-target %{ opt -S -passes=slp-vectorizer -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s %} 4 5define i32 @test(ptr %b, ptr %c, i32 %0, ptr %a, i1 %tobool3.not) { 6; CHECK-LABEL: define i32 @test( 7; CHECK-SAME: ptr [[B:%.*]], ptr [[C:%.*]], i32 [[TMP0:%.*]], ptr [[A:%.*]], i1 [[TOBOOL3_NOT:%.*]]) { 8; CHECK-NEXT: entry: 9; CHECK-NEXT: br i1 [[TOBOOL3_NOT]], label [[BB1:%.*]], label [[BB2:%.*]] 10; CHECK: bb1: 11; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> poison, i32 [[TMP0]], i32 0 12; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> poison, <4 x i32> zeroinitializer 13; CHECK-NEXT: [[TMP3:%.*]] = ashr <4 x i32> [[TMP2]], splat (i32 16) 14; CHECK-NEXT: [[TMP4:%.*]] = icmp slt <4 x i32> [[TMP3]], [[TMP2]] 15; CHECK-NEXT: [[TMP5:%.*]] = zext <4 x i1> [[TMP4]] to <4 x i16> 16; CHECK-NEXT: br label [[BB3:%.*]] 17; CHECK: bb2: 18; CHECK-NEXT: [[TMP6:%.*]] = insertelement <4 x i32> poison, i32 [[TMP0]], i32 0 19; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <4 x i32> [[TMP6]], <4 x i32> poison, <4 x i32> zeroinitializer 20; CHECK-NEXT: [[TMP8:%.*]] = icmp sgt <4 x i32> [[TMP7]], zeroinitializer 21; CHECK-NEXT: [[TMP9:%.*]] = zext <4 x i1> [[TMP8]] to <4 x i32> 22; CHECK-NEXT: [[TMP10:%.*]] = insertelement <4 x i1> poison, i1 [[TOBOOL3_NOT]], i32 0 23; CHECK-NEXT: [[TMP11:%.*]] = shufflevector <4 x i1> [[TMP10]], <4 x i1> poison, <4 x i32> zeroinitializer 24; CHECK-NEXT: [[TMP12:%.*]] = select <4 x i1> [[TMP11]], <4 x i32> [[TMP7]], <4 x i32> [[TMP9]] 25; CHECK-NEXT: [[TMP13:%.*]] = shl <4 x i32> [[TMP12]], splat (i32 16) 26; CHECK-NEXT: [[TMP14:%.*]] = ashr <4 x i32> [[TMP13]], splat (i32 16) 27; CHECK-NEXT: [[TMP15:%.*]] = trunc <4 x i32> [[TMP14]] to <4 x i16> 28; CHECK-NEXT: br i1 true, label [[BB3]], label [[BB2]] 29; CHECK: bb3: 30; CHECK-NEXT: [[TMP16:%.*]] = phi <4 x i16> [ [[TMP5]], [[BB1]] ], [ [[TMP15]], [[BB2]] ] 31; CHECK-NEXT: [[TMP17:%.*]] = extractelement <4 x i16> [[TMP16]], i32 0 32; CHECK-NEXT: [[TMP18:%.*]] = sext i16 [[TMP17]] to i32 33; CHECK-NEXT: store i32 [[TMP18]], ptr [[B]], align 16 34; CHECK-NEXT: [[TMP19:%.*]] = extractelement <4 x i16> [[TMP16]], i32 1 35; CHECK-NEXT: [[TMP20:%.*]] = sext i16 [[TMP19]] to i32 36; CHECK-NEXT: store i32 [[TMP20]], ptr [[A]], align 8 37; CHECK-NEXT: [[TMP21:%.*]] = extractelement <4 x i16> [[TMP16]], i32 2 38; CHECK-NEXT: [[TMP22:%.*]] = sext i16 [[TMP21]] to i32 39; CHECK-NEXT: store i32 [[TMP22]], ptr [[C]], align 16 40; CHECK-NEXT: [[TMP23:%.*]] = extractelement <4 x i16> [[TMP16]], i32 3 41; CHECK-NEXT: [[TMP24:%.*]] = sext i16 [[TMP23]] to i32 42; CHECK-NEXT: store i32 [[TMP24]], ptr [[B]], align 8 43; CHECK-NEXT: ret i32 0 44; 45entry: 46 br i1 %tobool3.not, label %bb1, label %bb2 47 48bb1: 49 %conv1.i.us = ashr i32 %0, 16 50 %cmp2.i.us = icmp slt i32 %conv1.i.us, %0 51 %sext26.us = zext i1 %cmp2.i.us to i32 52 %conv1.i.us.5 = ashr i32 %0, 16 53 %cmp2.i.us.5 = icmp slt i32 %conv1.i.us.5, %0 54 %sext26.us.5 = zext i1 %cmp2.i.us.5 to i32 55 %conv1.i.us.6 = ashr i32 %0, 16 56 %cmp2.i.us.6 = icmp slt i32 %conv1.i.us.6, %0 57 %sext26.us.6 = zext i1 %cmp2.i.us.6 to i32 58 %conv1.i.us.7 = ashr i32 %0, 16 59 %cmp2.i.us.7 = icmp slt i32 %conv1.i.us.7, %0 60 %sext26.us.7 = zext i1 %cmp2.i.us.7 to i32 61 br label %bb3 62 63bb2: 64 %cmp2.i = icmp sgt i32 %0, 0 65 %1 = zext i1 %cmp2.i to i32 66 %cond.i = select i1 %tobool3.not, i32 %0, i32 %1 67 %sext26 = shl i32 %cond.i, 16 68 %conv13 = ashr i32 %sext26, 16 69 %cmp2.i.5 = icmp sgt i32 %0, 0 70 %2 = zext i1 %cmp2.i.5 to i32 71 %cond.i.5 = select i1 %tobool3.not, i32 %0, i32 %2 72 %sext26.5 = shl i32 %cond.i.5, 16 73 %conv13.5 = ashr i32 %sext26.5, 16 74 %cmp2.i.6 = icmp sgt i32 %0, 0 75 %3 = zext i1 %cmp2.i.6 to i32 76 %cond.i.6 = select i1 %tobool3.not, i32 %0, i32 %3 77 %sext26.6 = shl i32 %cond.i.6, 16 78 %conv13.6 = ashr i32 %sext26.6, 16 79 %cmp2.i.7 = icmp sgt i32 %0, 0 80 %4 = zext i1 %cmp2.i.7 to i32 81 %cond.i.7 = select i1 %tobool3.not, i32 %0, i32 %4 82 %sext26.7 = shl i32 %cond.i.7, 16 83 %conv13.7 = ashr i32 %sext26.7, 16 84 br i1 true, label %bb3, label %bb2 85 86bb3: 87 %conv13p = phi i32 [ %sext26.us, %bb1 ], [ %conv13, %bb2 ] 88 %conv13.5p = phi i32 [ %sext26.us.5, %bb1 ], [ %conv13.5, %bb2 ] 89 %conv13.6p = phi i32 [ %sext26.us.6, %bb1 ], [ %conv13.6, %bb2 ] 90 %conv13.7p = phi i32 [ %sext26.us.7, %bb1 ], [ %conv13.7, %bb2 ] 91 store i32 %conv13p, ptr %b, align 16 92 store i32 %conv13.5p, ptr %a, align 8 93 store i32 %conv13.6p, ptr %c, align 16 94 store i32 %conv13.7p, ptr %b, align 8 95 ret i32 0 96} 97