1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 2; RUN: %if x86-registered-target %{ opt -S --passes=slp-vectorizer -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck %s %} 3; RUN: %if aarch64-registered-target %{ opt -S --passes=slp-vectorizer -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s %} 4 5define void @test() { 6; CHECK-LABEL: define void @test() { 7; CHECK-NEXT: entry: 8; CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr null, align 2 9; CHECK-NEXT: [[TMP1:%.*]] = and i8 0, 1 10; CHECK-NEXT: [[TMP2:%.*]] = and i32 0, 0 11; CHECK-NEXT: [[TMP3:%.*]] = select i1 false, i32 0, i32 0 12; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x i8> <i8 0, i8 poison, i8 poison, i8 poison>, i8 [[TMP1]], i32 1 13; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <4 x i8> [[TMP4]], <4 x i8> poison, <4 x i32> <i32 0, i32 1, i32 1, i32 1> 14; CHECK-NEXT: [[TMP15:%.*]] = trunc <4 x i8> [[TMP5]] to <4 x i1> 15; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <4 x i8> [[TMP4]], <4 x i8> poison, <4 x i32> <i32 1, i32 1, i32 1, i32 1> 16; CHECK-NEXT: [[TMP8:%.*]] = or <4 x i8> [[TMP7]], zeroinitializer 17; CHECK-NEXT: [[TMP9:%.*]] = trunc <4 x i8> [[TMP8]] to <4 x i1> 18; CHECK-NEXT: [[TMP10:%.*]] = or <4 x i1> zeroinitializer, [[TMP15]] 19; CHECK-NEXT: [[TMP11:%.*]] = icmp eq <4 x i1> [[TMP9]], [[TMP10]] 20; CHECK-NEXT: [[TMP6:%.*]] = zext <4 x i1> [[TMP15]] to <4 x i32> 21; CHECK-NEXT: [[TMP12:%.*]] = shufflevector <4 x i32> [[TMP6]], <4 x i32> <i32 0, i32 poison, i32 0, i32 0>, <4 x i32> <i32 4, i32 1, i32 6, i32 7> 22; CHECK-NEXT: [[TMP13:%.*]] = select <4 x i1> [[TMP11]], <4 x i32> [[TMP12]], <4 x i32> zeroinitializer 23; CHECK-NEXT: [[TMP14:%.*]] = call i32 @llvm.vector.reduce.and.v4i32(<4 x i32> [[TMP13]]) 24; CHECK-NEXT: [[OP_RDX:%.*]] = and i32 0, [[TMP14]] 25; CHECK-NEXT: store i32 [[OP_RDX]], ptr null, align 4 26; CHECK-NEXT: ret void 27; 28entry: 29 %0 = load i16, ptr null, align 2 30 %1 = and i8 0, 1 31 %2 = and i32 0, 0 32 %3 = select i1 false, i32 0, i32 0 33 %i2 = sext i8 %1 to i32 34 %i3 = or i8 %1, 0 35 %i4 = sext i8 %i3 to i32 36 %i5 = or i32 0, %i2 37 %b1 = icmp eq i32 %i4, %i5 38 %a1 = select i1 %b1, i32 0, i32 0 39 %4 = and i32 %a1, 0 40 %s1 = and i32 %4, 0 41 %i8 = sext i8 %1 to i32 42 %i9 = or i8 %1, 0 43 %i10 = sext i8 %i9 to i32 44 %i11 = or i32 0, %i8 45 %b2 = icmp eq i32 %i10, %i11 46 %a2 = select i1 %b2, i32 0, i32 0 47 %5 = and i32 %a2, 0 48 %s2 = and i32 %5, %s1 49 %i14 = sext i8 %1 to i32 50 %i15 = or i8 %1, 0 51 %i16 = sext i8 %i15 to i32 52 %i17 = or i32 0, %i14 53 %b3 = icmp eq i32 %i16, %i17 54 %a3 = select i1 %b3, i32 %i14, i32 0 55 %6 = and i32 %a3, 0 56 %s3 = and i32 %6, %s2 57 %i20 = sext i8 0 to i32 58 %i21 = or i8 %1, 0 59 %i22 = sext i8 %i21 to i32 60 %i23 = or i32 0, %i20 61 %b4 = icmp eq i32 %i22, %i23 62 %a4 = select i1 %b4, i32 0, i32 0 63 %7 = and i32 %a4, 0 64 %s4 = and i32 %7, %s3 65 store i32 %s4, ptr null, align 4 66 ret void 67} 68