1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 2; RUN: %if x86-registered-target %{ opt -S --passes=slp-vectorizer -mtriple=x86_64-unknown-linux < %s | FileCheck %s %} 3; RUN: %if aarch64-registered-target %{ opt -S --passes=slp-vectorizer -mtriple=aarch64-unknown-linux < %s | FileCheck %s %} 4 5define void @test(ptr %top) { 6; CHECK-LABEL: define void @test( 7; CHECK-SAME: ptr [[TOP:%.*]]) { 8; CHECK-NEXT: entry: 9; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i8>, ptr [[TOP]], align 1 10; CHECK-NEXT: [[TMP1:%.*]] = mul <4 x i8> [[TMP0]], zeroinitializer 11; CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x i8> [[TMP0]], i32 2 12; CHECK-NEXT: [[TMP3:%.*]] = zext i8 [[TMP2]] to i32 13; CHECK-NEXT: [[TMP4:%.*]] = trunc i32 [[TMP3]] to i8 14; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x i8> <i8 0, i8 0, i8 0, i8 poison>, i8 [[TMP4]], i32 3 15; CHECK-NEXT: [[TMP6:%.*]] = or <4 x i8> [[TMP1]], [[TMP5]] 16; CHECK-NEXT: [[TMP7:%.*]] = or <4 x i8> [[TMP6]], zeroinitializer 17; CHECK-NEXT: [[TMP8:%.*]] = lshr <4 x i8> [[TMP7]], splat (i8 2) 18; CHECK-NEXT: br label [[FOR_COND_I:%.*]] 19; CHECK: for.cond.i: 20; CHECK-NEXT: store <4 x i8> [[TMP8]], ptr null, align 1 21; CHECK-NEXT: br label [[FOR_COND_I]] 22; 23entry: 24 %0 = load i8, ptr %top, align 1 25 %conv2.i = zext i8 %0 to i32 26 %mul.i = mul i32 %conv2.i, 0 27 %add.i = or i32 %mul.i, 0 28 %arrayidx3.i = getelementptr i8, ptr %top, i64 1 29 %1 = load i8, ptr %arrayidx3.i, align 1 30 %conv4.i = zext i8 %1 to i32 31 %add5.i = or i32 %add.i, 0 32 %shr.i = lshr i32 %add5.i, 2 33 %conv7.i = trunc i32 %shr.i to i8 34 %mul12.i = mul i32 %conv4.i, 0 35 %arrayidx14.i = getelementptr i8, ptr %top, i64 2 36 %2 = load i8, ptr %arrayidx14.i, align 1 37 %conv15.i = zext i8 %2 to i32 38 %add16.i = or i32 %mul12.i, 0 39 %add17.i = or i32 %add16.i, 0 40 %shr18.i = lshr i32 %add17.i, 2 41 %conv19.i = trunc i32 %shr18.i to i8 42 %mul25.i = mul i32 %conv15.i, 0 43 %arrayidx27.i = getelementptr i8, ptr %top, i64 3 44 %3 = load i8, ptr %arrayidx27.i, align 1 45 %conv28.i = zext i8 %3 to i32 46 %add29.i = or i32 %mul25.i, 0 47 %add30.i = or i32 %add29.i, 0 48 %shr31.i = lshr i32 %add30.i, 2 49 %conv32.i = trunc i32 %shr31.i to i8 50 %mul38.i = mul i32 %conv28.i, 0 51 %add39.i = or i32 %mul38.i, %conv15.i 52 %add42.i = or i32 %add39.i, 0 53 %shr44.i = lshr i32 %add42.i, 2 54 %conv45.i = trunc i32 %shr44.i to i8 55 br label %for.cond.i 56 57for.cond.i: 58 store i8 %conv7.i, ptr null, align 1 59 %vals.sroa.5.0.add.ptr.sroa_idx.i = getelementptr i8, ptr null, i64 1 60 store i8 %conv19.i, ptr %vals.sroa.5.0.add.ptr.sroa_idx.i, align 1 61 %vals.sroa.7.0.add.ptr.sroa_idx.i = getelementptr i8, ptr null, i64 2 62 store i8 %conv32.i, ptr %vals.sroa.7.0.add.ptr.sroa_idx.i, align 1 63 %vals.sroa.9.0.add.ptr.sroa_idx.i = getelementptr i8, ptr null, i64 3 64 store i8 %conv45.i, ptr %vals.sroa.9.0.add.ptr.sroa_idx.i, align 1 65 br label %for.cond.i 66} 67