xref: /llvm-project/llvm/test/Transforms/SLPVectorizer/ext-int-reduced-not-operand.ll (revision 706e71076e0276747e7ae94e3f8a7f73a45e5b6e)
1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
2; RUN: %if x86-registered-target %{ opt -S --passes=slp-vectorizer -mtriple=x86_64-unknown-linux-gnu -slp-threshold=-99999 < %s | FileCheck %s %}
3; RUN: %if x86-registered-target %{ opt -S --passes=slp-vectorizer -mtriple=x86_64-unknown-linux-gnu -slp-threshold=-99999\
4; RUN: -slp-skip-early-profitability-check < %s | FileCheck %s --check-prefixes=FORCED %}
5; RUN: %if aarch64-registered-target %{ opt -S --passes=slp-vectorizer -mtriple=aarch64-unknown-linux-gnu -slp-threshold=-99999 < %s | FileCheck %s %}
6; RUN: %if aarch64-registered-target %{ opt -S --passes=slp-vectorizer -mtriple=aarch64-unknown-linux-gnu -slp-threshold=-99999\
7; RUN: -slp-skip-early-profitability-check < %s | FileCheck %s --check-prefixes=FORCED %}
8
9define i64 @wombat() {
10; FORCED-LABEL: define i64 @wombat() {
11; FORCED-NEXT:  bb:
12; FORCED-NEXT:    br label [[BB2:%.*]]
13; FORCED:       bb1:
14; FORCED-NEXT:    br label [[BB2]]
15; FORCED:       bb2:
16; FORCED-NEXT:    [[PHI:%.*]] = phi i32 [ 0, [[BB:%.*]] ], [ 0, [[BB1:%.*]] ]
17; FORCED-NEXT:    [[TMP0:%.*]] = insertelement <2 x i32> poison, i32 [[PHI]], i32 0
18; FORCED-NEXT:    [[TMP1:%.*]] = shufflevector <2 x i32> [[TMP0]], <2 x i32> poison, <2 x i32> zeroinitializer
19; FORCED-NEXT:    [[TMP2:%.*]] = trunc <2 x i32> [[TMP1]] to <2 x i1>
20; FORCED-NEXT:    [[TMP3:%.*]] = extractelement <2 x i1> [[TMP2]], i32 0
21; FORCED-NEXT:    [[TMP4:%.*]] = zext i1 [[TMP3]] to i64
22; FORCED-NEXT:    [[TMP5:%.*]] = extractelement <2 x i1> [[TMP2]], i32 1
23; FORCED-NEXT:    [[TMP6:%.*]] = zext i1 [[TMP5]] to i64
24; FORCED-NEXT:    [[OR:%.*]] = or i64 [[TMP4]], [[TMP6]]
25; FORCED-NEXT:    ret i64 [[OR]]
26;
27; CHECK-LABEL: define i64 @wombat() {
28; CHECK-NEXT:  bb:
29; CHECK-NEXT:    br label [[BB2:%.*]]
30; CHECK:       bb1:
31; CHECK-NEXT:    br label [[BB2]]
32; CHECK:       bb2:
33; CHECK-NEXT:    [[PHI:%.*]] = phi i32 [ 0, [[BB:%.*]] ], [ 0, [[BB1:%.*]] ]
34; CHECK-NEXT:    [[TMP4:%.*]] = zext i32 [[PHI]] to i64
35; CHECK-NEXT:    [[TMP6:%.*]] = sext i32 [[PHI]] to i64
36; CHECK-NEXT:    [[OR:%.*]] = or i64 [[TMP4]], [[TMP6]]
37; CHECK-NEXT:    ret i64 [[OR]]
38;
39bb:
40  br label %bb2
41
42bb1:
43  br label %bb2
44
45bb2:
46  %phi = phi i32 [ 0, %bb ], [ 0, %bb1 ]
47  %zext = zext i32 %phi to i64
48  %sext = sext i32 %phi to i64
49  %or = or i64 %zext, %sext
50  ret i64 %or
51}
52