xref: /llvm-project/llvm/test/Transforms/SLPVectorizer/SystemZ/revec-fix-117393.ll (revision ead3a2f5980e1a713c8d4e18a4c825e1012b3701)
1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2; RUN: opt -mtriple=systemz-unknown -mcpu=z15 -passes=slp-vectorizer -S -slp-revec %s | FileCheck %s
3
4define void @h() {
5; CHECK-LABEL: @h(
6; CHECK-NEXT:  entry:
7; CHECK-NEXT:    [[TMP0:%.*]] = shl <4 x i32> zeroinitializer, zeroinitializer
8; CHECK-NEXT:    [[TMP1:%.*]] = or <4 x i32> [[TMP0]], zeroinitializer
9; CHECK-NEXT:    [[TMP2:%.*]] = or <4 x i32> splat (i32 1), zeroinitializer
10; CHECK-NEXT:    [[TMP3:%.*]] = shl <4 x i32> zeroinitializer, zeroinitializer
11; CHECK-NEXT:    [[TMP4:%.*]] = or <4 x i32> [[TMP3]], zeroinitializer
12; CHECK-NEXT:    [[TMP5:%.*]] = and <4 x i32> [[TMP2]], [[TMP1]]
13; CHECK-NEXT:    [[TMP6:%.*]] = and <4 x i32> zeroinitializer, [[TMP5]]
14; CHECK-NEXT:    [[TMP7:%.*]] = and <4 x i32> [[TMP4]], [[TMP6]]
15; CHECK-NEXT:    [[TMP8:%.*]] = call i32 @llvm.vector.reduce.and.v4i32(<4 x i32> [[TMP7]])
16; CHECK-NEXT:    ret void
17;
18entry:
19  %0 = shl <4 x i32> zeroinitializer, zeroinitializer
20  %1 = or <4 x i32> %0, zeroinitializer
21  %2 = or <4 x i32> splat (i32 1), zeroinitializer
22  %3 = or <4 x i32> zeroinitializer, zeroinitializer
23  %4 = shl <4 x i32> zeroinitializer, zeroinitializer
24  %5 = or <4 x i32> %4, zeroinitializer
25  %6 = and <4 x i32> %2, %1
26  %7 = and <4 x i32> %3, %6
27  %8 = and <4 x i32> %5, %7
28  %9 = call i32 @llvm.vector.reduce.and.v4i32(<4 x i32> %8)
29  ret void
30}
31