1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 2; RUN: opt -S -passes=slp-vectorizer -mtriple=riscv64-unknown-linux-gnu -mattr=+v < %s | FileCheck %s 3 4define i32 @test(ptr %p) { 5; CHECK-LABEL: define i32 @test( 6; CHECK-SAME: ptr [[P:%.*]]) #[[ATTR0:[0-9]+]] { 7; CHECK-NEXT: entry: 8; CHECK-NEXT: [[D_0:%.*]] = load i16, ptr [[P]], align 4 9; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i16> <i16 poison, i16 0, i16 0, i16 0>, i16 [[D_0]], i32 0 10; CHECK-NEXT: [[TMP1:%.*]] = or <4 x i16> [[TMP0]], zeroinitializer 11; CHECK-NEXT: [[TMP2:%.*]] = and <4 x i16> [[TMP1]], zeroinitializer 12; CHECK-NEXT: [[TMP3:%.*]] = zext <4 x i16> [[TMP0]] to <4 x i32> 13; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <4 x i32> [[TMP3]], <4 x i32> <i32 poison, i32 0, i32 0, i32 0>, <4 x i32> <i32 0, i32 5, i32 6, i32 7> 14; CHECK-NEXT: [[TMP5:%.*]] = icmp sgt <4 x i32> [[TMP4]], zeroinitializer 15; CHECK-NEXT: [[TMP6:%.*]] = select <4 x i1> [[TMP5]], <4 x i16> [[TMP2]], <4 x i16> <i16 2, i16 0, i16 0, i16 0> 16; CHECK-NEXT: [[TMP7:%.*]] = call i16 @llvm.vector.reduce.umax.v4i16(<4 x i16> [[TMP6]]) 17; CHECK-NEXT: [[TMP8:%.*]] = zext i16 [[TMP7]] to i32 18; CHECK-NEXT: [[TMP9:%.*]] = call i32 @llvm.umax.i32(i32 [[TMP8]], i32 1) 19; CHECK-NEXT: ret i32 [[TMP9]] 20; 21entry: 22 %d.0 = load i16, ptr %p, align 4 23 %zext.d.0 = zext i16 %d.0 to i32 24 %zero.0 = zext i16 0 to i32 25 %zero.1 = zext i16 0 to i32 26 %zero.2 = zext i16 0 to i32 27 28 %or.d.0 = or i32 %zext.d.0, 0 29 %or.zero.0 = or i32 %zero.0, 0 30 %or.zero.1 = or i32 %zero.1, 0 31 %or.zero.2 = or i32 %zero.2, 0 32 33 %zero.d.0 = and i32 %or.d.0, 0 34 %and.zero.0 = and i32 %or.zero.0, 0 35 %and.zero.1 = and i32 %or.zero.1, 0 36 %and.zero.2 = and i32 %or.zero.2, 0 37 38 %d.0.gt.0 = icmp sgt i32 %zext.d.0, 0 39 %false.0 = icmp sgt i32 0, 0 40 %false.1 = icmp sgt i32 0, 0 41 %false.2 = icmp sgt i32 0, 0 42 43 %select.0.2 = select i1 %d.0.gt.0, i32 %zero.d.0, i32 2 44 %select.1.0 = select i1 %false.0, i32 %and.zero.0, i32 0 45 %select.2.0 = select i1 %false.1, i32 %and.zero.1, i32 0 46 %select.3.0 = select i1 %false.2, i32 %and.zero.2, i32 0 47 48 %max.0 = call i32 @llvm.umax.i32(i32 %select.0.2, i32 %select.1.0) 49 %max.1 = call i32 @llvm.umax.i32(i32 %max.0, i32 %select.2.0) 50 %max.2 = call i32 @llvm.umax.i32(i32 %max.1, i32 %select.3.0) 51 %max.3 = call i32 @llvm.umax.i32(i32 %max.2, i32 1) 52 53 ret i32 %max.3 54} 55 56define i32 @test1(ptr %p) { 57; CHECK-LABEL: define i32 @test1( 58; CHECK-SAME: ptr [[P:%.*]]) #[[ATTR0]] { 59; CHECK-NEXT: entry: 60; CHECK-NEXT: [[D_0:%.*]] = load i16, ptr [[P]], align 4 61; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i16> <i16 poison, i16 0, i16 0, i16 0>, i16 [[D_0]], i32 0 62; CHECK-NEXT: [[TMP3:%.*]] = zext <4 x i16> [[TMP0]] to <4 x i32> 63; CHECK-NEXT: [[TMP2:%.*]] = or <4 x i32> [[TMP3]], zeroinitializer 64; CHECK-NEXT: [[TMP6:%.*]] = and <4 x i32> [[TMP2]], <i32 -1, i32 -16383, i32 65535, i32 -1> 65; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <4 x i32> [[TMP3]], <4 x i32> <i32 -1, i32 -16383, i32 65535, i32 -1>, <4 x i32> <i32 0, i32 5, i32 6, i32 7> 66; CHECK-NEXT: [[TMP5:%.*]] = icmp eq <4 x i32> [[TMP4]], <i32 65535, i32 -16383, i32 65535, i32 65535> 67; CHECK-NEXT: [[TMP7:%.*]] = select <4 x i1> [[TMP5]], <4 x i32> [[TMP6]], <4 x i32> <i32 4, i32 3, i32 2, i32 1> 68; CHECK-NEXT: [[TMP8:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP7]]) 69; CHECK-NEXT: ret i32 [[TMP8]] 70; 71entry: 72 %d.0 = load i16, ptr %p, align 4 73 %zext.d.0 = zext i16 %d.0 to i32 74 %zero.0 = zext i16 0 to i32 75 %zero.1 = zext i16 0 to i32 76 %zero.2 = zext i16 0 to i32 77 78 %or.d.0 = or i32 %zext.d.0, 0 79 %or.zero.0 = or i32 %zero.0, 0 80 %or.zero.1 = or i32 %zero.1, 0 81 %or.zero.2 = or i32 %zero.2, 0 82 83 %szero.00 = sext i16 65535 to i32 84 %szero.0 = sext i16 -16383 to i32 85 %uzero.1 = zext i16 65535 to i32 86 %szero.2 = sext i16 65535 to i32 87 88 %zero.d.0 = and i32 %or.d.0, %szero.00 89 %and.zero.0 = and i32 %or.zero.0, %szero.0 90 %and.zero.1 = and i32 %or.zero.1, %uzero.1 91 %and.zero.2 = and i32 %or.zero.2, %szero.2 92 93 %d.0.gt.0 = icmp eq i32 %zext.d.0, 65535 94 %false.0 = icmp eq i32 %szero.0, -16383 95 %false.1 = icmp eq i32 %uzero.1, 65535 96 %false.2 = icmp eq i32 %szero.2, 65535 97 98 %select.0.2 = select i1 %d.0.gt.0, i32 %zero.d.0, i32 4 99 %select.1.0 = select i1 %false.0, i32 %and.zero.0, i32 3 100 %select.2.0 = select i1 %false.1, i32 %and.zero.1, i32 2 101 %select.3.0 = select i1 %false.2, i32 %and.zero.2, i32 1 102 103 %max.0 = add i32 %select.0.2, %select.1.0 104 %max.1 = add i32 %max.0, %select.2.0 105 %max.2 = add i32 %max.1, %select.3.0 106 107 ret i32 %max.2 108} 109 110