1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 2; RUN: opt -S --passes=slp-vectorizer -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s 3 4define void @h() { 5; CHECK-LABEL: define void @h() { 6; CHECK-NEXT: entry: 7; CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr i8, ptr null, i64 16 8; CHECK-NEXT: store <8 x i16> zeroinitializer, ptr [[ARRAYIDX2]], align 2 9; CHECK-NEXT: ret void 10; 11entry: 12 %arrayidx2 = getelementptr i8, ptr null, i64 16 13 %conv310 = zext i16 0 to i32 14 %add4 = or i32 %conv310, 0 15 %sub = or i32 0, %conv310 16 %conv15 = sext i16 0 to i32 17 %shr = ashr i32 %conv15, 0 18 %arrayidx18 = getelementptr i8, ptr null, i64 24 19 %conv19 = sext i16 0 to i32 20 %sub20 = or i32 %shr, 0 21 %shr29 = ashr i32 %conv19, 0 22 %add30 = or i32 %shr29, %conv15 23 %sub39 = or i32 %sub, %sub20 24 %conv40 = trunc i32 %sub39 to i16 25 store i16 %conv40, ptr %arrayidx2, align 2 26 %sub44 = or i32 %add4, %add30 27 %conv45 = trunc i32 %sub44 to i16 28 store i16 %conv45, ptr %arrayidx18, align 2 29 %arrayidx2.1 = getelementptr i8, ptr null, i64 18 30 %conv3.112 = zext i16 0 to i32 31 %add4.1 = or i32 %conv3.112, 0 32 %sub.1 = or i32 0, %conv3.112 33 %conv15.1 = sext i16 0 to i32 34 %shr.1 = ashr i32 %conv15.1, 0 35 %arrayidx18.1 = getelementptr i8, ptr null, i64 26 36 %conv19.1 = sext i16 0 to i32 37 %sub20.1 = or i32 %shr.1, 0 38 %shr29.1 = ashr i32 %conv19.1, 0 39 %add30.1 = or i32 %shr29.1, 0 40 %sub39.1 = or i32 %sub.1, %sub20.1 41 %conv40.1 = trunc i32 %sub39.1 to i16 42 store i16 %conv40.1, ptr %arrayidx2.1, align 2 43 %sub44.1 = or i32 %add4.1, %add30.1 44 %conv45.1 = trunc i32 %sub44.1 to i16 45 store i16 %conv45.1, ptr %arrayidx18.1, align 2 46 %conv.213 = zext i16 0 to i32 47 %arrayidx2.2 = getelementptr i8, ptr null, i64 20 48 %conv3.214 = zext i16 0 to i32 49 %add4.2 = or i32 0, %conv.213 50 %sub.2 = or i32 0, %conv3.214 51 %conv15.2 = sext i16 0 to i32 52 %shr.2 = ashr i32 %conv15.2, 0 53 %arrayidx18.2 = getelementptr i8, ptr null, i64 28 54 %conv19.2 = sext i16 0 to i32 55 %sub20.2 = or i32 %shr.2, 0 56 %shr29.2 = ashr i32 %conv19.2, 0 57 %add30.2 = or i32 %shr29.2, 0 58 %sub39.2 = or i32 %sub.2, %sub20.2 59 %conv40.2 = trunc i32 %sub39.2 to i16 60 store i16 %conv40.2, ptr %arrayidx2.2, align 2 61 %sub44.2 = or i32 %add4.2, %add30.2 62 %conv45.2 = trunc i32 %sub44.2 to i16 63 store i16 %conv45.2, ptr %arrayidx18.2, align 2 64 %conv.315 = zext i16 0 to i32 65 %arrayidx2.3 = getelementptr i8, ptr null, i64 22 66 %conv3.316 = zext i16 0 to i32 67 %add4.3 = or i32 0, %conv.315 68 %sub.3 = or i32 0, %conv3.316 69 %conv15.3 = sext i16 0 to i32 70 %shr.3 = ashr i32 %conv15.3, 0 71 %arrayidx18.3 = getelementptr i8, ptr null, i64 30 72 %conv19.3 = sext i16 0 to i32 73 %sub20.3 = or i32 %shr.3, 0 74 %shr29.3 = ashr i32 %conv19.3, 0 75 %add30.3 = or i32 %shr29.3, 0 76 %sub39.3 = or i32 %sub.3, %sub20.3 77 %conv40.3 = trunc i32 %sub39.3 to i16 78 store i16 %conv40.3, ptr %arrayidx2.3, align 2 79 %sub44.3 = or i32 %add4.3, %add30.3 80 %conv45.3 = trunc i32 %sub44.3 to i16 81 store i16 %conv45.3, ptr %arrayidx18.3, align 2 82 ret void 83} 84