1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 2; RUN: opt -S -passes=slp-vectorizer < %s | FileCheck %s 3 4target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128" 5target triple = "aarch64--linux-gnu" 6 7; This test ensures that we do not regress due to PR26364. The vectorizer 8; should not compute a smaller size for %k.13 since it is in a use-def cycle 9; and cannot be demoted. 10; 11define fastcc void @PR26364(i1 %arg) { 12; CHECK-LABEL: @PR26364( 13; CHECK-NEXT: entry: 14; CHECK-NEXT: br i1 %arg, label [[FOR_END11:%.*]], label [[FOR_COND4:%.*]] 15; CHECK: for.cond4: 16; CHECK-NEXT: [[K_13:%.*]] = phi i32 [ undef, [[ENTRY:%.*]] ], [ [[K_3:%.*]], [[FOR_COND4]] ] 17; CHECK-NEXT: [[E_02:%.*]] = phi i32 [ 1, [[ENTRY]] ], [ 0, [[FOR_COND4]] ] 18; CHECK-NEXT: [[E_1:%.*]] = select i1 undef, i32 [[E_02]], i32 0 19; CHECK-NEXT: [[K_3]] = select i1 undef, i32 [[K_13]], i32 undef 20; CHECK-NEXT: br label [[FOR_COND4]] 21; CHECK: for.end11: 22; CHECK-NEXT: ret void 23; 24entry: 25 br i1 %arg, label %for.end11, label %for.cond4 26 27for.cond4: 28 %k.13 = phi i32 [ undef, %entry ], [ %k.3, %for.cond4 ] 29 %e.02 = phi i32 [ 1, %entry ], [ 0, %for.cond4 ] 30 %e.1 = select i1 undef, i32 %e.02, i32 0 31 %k.3 = select i1 undef, i32 %k.13, i32 undef 32 br label %for.cond4 33 34for.end11: 35 ret void 36} 37 38; This test ensures that we do not regress due to PR26629. We must look at 39; every root in the vectorizable tree when computing minimum sizes since one 40; root may require fewer bits than another. 41; 42define void @PR26629(ptr %c, i1 %arg) { 43; CHECK-LABEL: @PR26629( 44; CHECK-NEXT: entry: 45; CHECK-NEXT: br i1 %arg, label [[FOR_PH:%.*]], label [[FOR_END:%.*]] 46; CHECK: for.ph: 47; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[C:%.*]], align 4 48; CHECK-NEXT: br label [[FOR_BODY:%.*]] 49; CHECK: for.body: 50; CHECK-NEXT: [[D:%.*]] = phi i72 [ 576507472957710340, [[FOR_PH]] ], [ [[BF_SET17:%.*]], [[FOR_BODY]] ] 51; CHECK-NEXT: [[SUB:%.*]] = sub i32 [[TMP0]], undef 52; CHECK-NEXT: [[BF_CLEAR13:%.*]] = and i72 [[D]], -576460748008464384 53; CHECK-NEXT: [[TMP1:%.*]] = zext i32 [[SUB]] to i72 54; CHECK-NEXT: [[BF_VALUE15:%.*]] = and i72 [[TMP1]], 8191 55; CHECK-NEXT: [[BF_CLEAR16:%.*]] = or i72 [[BF_VALUE15]], [[BF_CLEAR13]] 56; CHECK-NEXT: [[BF_SET17]] = or i72 [[BF_CLEAR16]], undef 57; CHECK-NEXT: br label [[FOR_BODY]] 58; CHECK: for.end: 59; CHECK-NEXT: ret void 60; 61entry: 62 br i1 %arg, label %for.ph, label %for.end 63 64for.ph: 65 %0 = load i32, ptr %c, align 4 66 br label %for.body 67 68for.body: 69 %d = phi i72 [ 576507472957710340, %for.ph ], [ %bf.set17, %for.body ] 70 %sub = sub i32 %0, undef 71 %bf.clear13 = and i72 %d, -576460748008464384 72 %1 = zext i32 %sub to i72 73 %bf.value15 = and i72 %1, 8191 74 %bf.clear16 = or i72 %bf.value15, %bf.clear13 75 %bf.set17 = or i72 %bf.clear16, undef 76 br label %for.body 77 78for.end: 79 ret void 80} 81