1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
2; RUN: opt -S --passes=slp-vectorizer -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s
3
4define void @h() {
5; CHECK-LABEL: define void @h() {
6; CHECK-NEXT:  entry:
7; CHECK-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr i8, ptr null, i64 16
8; CHECK-NEXT:    store <8 x i16> zeroinitializer, ptr [[ARRAYIDX2]], align 2
9; CHECK-NEXT:    ret void
10;
11entry:
12  %conv9 = zext i16 0 to i32
13  %arrayidx2 = getelementptr i8, ptr null, i64 16
14  %conv310 = zext i16 0 to i32
15  %add4 = or i32 %conv310, %conv9
16  %sub = or i32 %conv9, %conv310
17  %conv15 = sext i16 0 to i32
18  %shr = ashr i32 0, 0
19  %arrayidx18 = getelementptr i8, ptr null, i64 24
20  %conv19 = sext i16 0 to i32
21  %sub20 = or i32 %shr, %conv19
22  %shr29 = ashr i32 0, 0
23  %add30 = or i32 %shr29, %conv15
24  %sub39 = or i32 %sub, %sub20
25  %conv40 = trunc i32 %sub39 to i16
26  store i16 %conv40, ptr %arrayidx2, align 2
27  %sub44 = or i32 %add4, %add30
28  %conv45 = trunc i32 %sub44 to i16
29  store i16 %conv45, ptr %arrayidx18, align 2
30  %arrayidx2.1 = getelementptr i8, ptr null, i64 18
31  %conv3.112 = zext i16 0 to i32
32  %add4.1 = or i32 %conv3.112, 0
33  %sub.1 = or i32 0, %conv3.112
34  %conv15.1 = sext i16 0 to i32
35  %shr.1 = ashr i32 0, 0
36  %arrayidx18.1 = getelementptr i8, ptr null, i64 26
37  %conv19.1 = sext i16 0 to i32
38  %sub20.1 = or i32 %shr.1, %conv19.1
39  %shr29.1 = ashr i32 0, 0
40  %add30.1 = or i32 %shr29.1, %conv15.1
41  %sub39.1 = or i32 %sub.1, %sub20.1
42  %conv40.1 = trunc i32 %sub39.1 to i16
43  store i16 %conv40.1, ptr %arrayidx2.1, align 2
44  %sub44.1 = or i32 %add4.1, %add30.1
45  %conv45.1 = trunc i32 %sub44.1 to i16
46  store i16 %conv45.1, ptr %arrayidx18.1, align 2
47  %conv.213 = zext i16 0 to i32
48  %arrayidx2.2 = getelementptr i8, ptr null, i64 20
49  %conv3.214 = zext i16 0 to i32
50  %add4.2 = or i32 0, %conv.213
51  %sub.2 = or i32 0, %conv3.214
52  %conv15.2 = sext i16 0 to i32
53  %shr.2 = ashr i32 0, 0
54  %arrayidx18.2 = getelementptr i8, ptr null, i64 28
55  %conv19.2 = sext i16 0 to i32
56  %sub20.2 = or i32 %shr.2, %conv19.2
57  %shr29.2 = ashr i32 0, 0
58  %add30.2 = or i32 %shr29.2, %conv15.2
59  %sub39.2 = or i32 %sub.2, %sub20.2
60  %conv40.2 = trunc i32 %sub39.2 to i16
61  store i16 %conv40.2, ptr %arrayidx2.2, align 2
62  %sub44.2 = or i32 %add4.2, %add30.2
63  %conv45.2 = trunc i32 %sub44.2 to i16
64  store i16 %conv45.2, ptr %arrayidx18.2, align 2
65  %conv.315 = zext i16 0 to i32
66  %arrayidx2.3 = getelementptr i8, ptr null, i64 22
67  %conv3.316 = zext i16 0 to i32
68  %add4.3 = or i32 0, %conv.315
69  %sub.3 = or i32 0, %conv3.316
70  %conv15.3 = sext i16 0 to i32
71  %shr.3 = ashr i32 0, 0
72  %arrayidx18.3 = getelementptr i8, ptr null, i64 30
73  %conv19.3 = sext i16 0 to i32
74  %sub20.3 = or i32 %shr.3, %conv19.3
75  %shr29.3 = ashr i32 0, 0
76  %add30.3 = or i32 %shr29.3, %conv15.3
77  %sub39.3 = or i32 %sub.3, %sub20.3
78  %conv40.3 = trunc i32 %sub39.3 to i16
79  store i16 %conv40.3, ptr %arrayidx2.3, align 2
80  %sub44.3 = or i32 %add4.3, %add30.3
81  %conv45.3 = trunc i32 %sub44.3 to i16
82  store i16 %conv45.3, ptr %arrayidx18.3, align 2
83  ret void
84}
85