1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 2; RUN: opt -O2 -S < %s | FileCheck %s 3 4define <3 x float> @PR52631(<3 x float> %a, <3 x float> %b, <3 x i32> %c) { 5; CHECK-LABEL: @PR52631( 6; CHECK-NEXT: [[ISNEG3:%.*]] = icmp slt <3 x i32> [[C:%.*]], zeroinitializer 7; CHECK-NEXT: [[OR_V:%.*]] = select <3 x i1> [[ISNEG3]], <3 x float> [[B:%.*]], <3 x float> [[A:%.*]] 8; CHECK-NEXT: ret <3 x float> [[OR_V]] 9; 10 %a.addr = alloca <3 x float>, align 16 11 %b.addr = alloca <3 x float>, align 16 12 %c.addr = alloca <3 x i32>, align 16 13 %zero = alloca <3 x i32>, align 16 14 %mask = alloca <3 x i32>, align 16 15 %res = alloca <3 x i32>, align 16 16 %extractVec = shufflevector <3 x float> %a, <3 x float> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 undef> 17 store <4 x float> %extractVec, ptr %a.addr, align 16 18 %extractVec1 = shufflevector <3 x float> %b, <3 x float> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 undef> 19 store <4 x float> %extractVec1, ptr %b.addr, align 16 20 %extractVec3 = shufflevector <3 x i32> %c, <3 x i32> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 undef> 21 store <4 x i32> %extractVec3, ptr %c.addr, align 16 22 call void @llvm.lifetime.start.p0(i64 16, ptr %zero) #2 23 store <4 x i32> <i32 0, i32 0, i32 0, i32 undef>, ptr %zero, align 16 24 call void @llvm.lifetime.start.p0(i64 16, ptr %mask) #2 25 %loadVec4 = load <4 x i32>, ptr %zero, align 16 26 %extractVec6 = shufflevector <4 x i32> %loadVec4, <4 x i32> poison, <3 x i32> <i32 0, i32 1, i32 2> 27 %loadVec48 = load <4 x i32>, ptr %c.addr, align 16 28 %extractVec9 = shufflevector <4 x i32> %loadVec48, <4 x i32> poison, <3 x i32> <i32 0, i32 1, i32 2> 29 %cmp = icmp sgt <3 x i32> %extractVec6, %extractVec9 30 %sext = sext <3 x i1> %cmp to <3 x i32> 31 %extractVec10 = shufflevector <3 x i32> %sext, <3 x i32> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 undef> 32 store <4 x i32> %extractVec10, ptr %mask, align 16 33 call void @llvm.lifetime.start.p0(i64 16, ptr %res) #2 34 %loadVec413 = load <4 x i32>, ptr %mask, align 16 35 %extractVec14 = shufflevector <4 x i32> %loadVec413, <4 x i32> poison, <3 x i32> <i32 0, i32 1, i32 2> 36 %loadVec416 = load <4 x float>, ptr %b.addr, align 16 37 %extractVec17 = shufflevector <4 x float> %loadVec416, <4 x float> poison, <3 x i32> <i32 0, i32 1, i32 2> 38 %astype = bitcast <3 x float> %extractVec17 to <3 x i32> 39 %and = and <3 x i32> %extractVec14, %astype 40 %extractVec18 = shufflevector <3 x i32> %and, <3 x i32> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 undef> 41 store <4 x i32> %extractVec18, ptr %res, align 16 42 %loadVec421 = load <4 x i32>, ptr %mask, align 16 43 %extractVec22 = shufflevector <4 x i32> %loadVec421, <4 x i32> poison, <3 x i32> <i32 0, i32 1, i32 2> 44 %cmp23 = icmp eq <3 x i32> %extractVec22, zeroinitializer 45 %sext24 = sext <3 x i1> %cmp23 to <3 x i32> 46 %loadVec426 = load <4 x float>, ptr %a.addr, align 16 47 %extractVec27 = shufflevector <4 x float> %loadVec426, <4 x float> poison, <3 x i32> <i32 0, i32 1, i32 2> 48 %astype28 = bitcast <3 x float> %extractVec27 to <3 x i32> 49 %and29 = and <3 x i32> %sext24, %astype28 50 %loadVec431 = load <4 x i32>, ptr %res, align 16 51 %extractVec32 = shufflevector <4 x i32> %loadVec431, <4 x i32> poison, <3 x i32> <i32 0, i32 1, i32 2> 52 %or = or <3 x i32> %and29, %extractVec32 53 %astype33 = bitcast <3 x i32> %or to <3 x float> 54 call void @llvm.lifetime.end.p0(i64 16, ptr %res) #2 55 call void @llvm.lifetime.end.p0(i64 16, ptr %mask) #2 56 call void @llvm.lifetime.end.p0(i64 16, ptr %zero) #2 57 ret <3 x float> %astype33 58} 59 60define <4 x i8> @allSignBits_vec(<4 x i8> %cond, <4 x i8> %tval, <4 x i8> %fval) { 61; CHECK-LABEL: @allSignBits_vec( 62; CHECK-NEXT: [[ISNEG1:%.*]] = icmp slt <4 x i8> [[COND:%.*]], zeroinitializer 63; CHECK-NEXT: [[SEL:%.*]] = select <4 x i1> [[ISNEG1]], <4 x i8> [[TVAL:%.*]], <4 x i8> [[FVAL:%.*]] 64; CHECK-NEXT: ret <4 x i8> [[SEL]] 65; 66 %bitmask = ashr <4 x i8> %cond, <i8 7, i8 7, i8 7, i8 7> 67 %not_bitmask = xor <4 x i8> %bitmask, <i8 -1, i8 -1, i8 -1, i8 -1> 68 %a1 = and <4 x i8> %tval, %bitmask 69 %a2 = and <4 x i8> %fval, %not_bitmask 70 %sel = or <4 x i8> %a2, %a1 71 ret <4 x i8> %sel 72} 73 74define <4 x i32> @PR42100(<4 x i32> noundef %x, <4 x i32> noundef %min) { 75; CHECK-LABEL: @PR42100( 76; CHECK-NEXT: entry: 77; CHECK-NEXT: [[TMP0:%.*]] = tail call <4 x i32> @llvm.smin.v4i32(<4 x i32> [[X:%.*]], <4 x i32> [[MIN:%.*]]) 78; CHECK-NEXT: ret <4 x i32> [[TMP0]] 79; 80entry: 81 br label %for.cond 82 83for.cond: 84 %min.addr.0 = phi <4 x i32> [ %min, %entry ], [ %min.addr.1, %for.inc ] 85 %i.0 = phi i32 [ 0, %entry ], [ %inc, %for.inc ] 86 %cmp = icmp ne i32 %i.0, 4 87 br i1 %cmp, label %for.body, label %for.cond.cleanup 88 89for.cond.cleanup: 90 br label %for.end 91 92for.body: 93 %vecext = extractelement <4 x i32> %x, i32 %i.0 94 %vecext1 = extractelement <4 x i32> %min.addr.0, i32 %i.0 95 %cmp2 = icmp slt i32 %vecext, %vecext1 96 br i1 %cmp2, label %if.then, label %if.end 97 98if.then: 99 %vecext3 = extractelement <4 x i32> %x, i32 %i.0 100 %vecins = insertelement <4 x i32> %min.addr.0, i32 %vecext3, i32 %i.0 101 br label %if.end 102 103if.end: 104 %min.addr.1 = phi <4 x i32> [ %vecins, %if.then ], [ %min.addr.0, %for.body ] 105 br label %for.inc 106 107for.inc: 108 %inc = add nsw i32 %i.0, 1 109 br label %for.cond 110 111for.end: 112 ret <4 x i32> %min.addr.0 113} 114 115declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1 116declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1 117