xref: /llvm-project/llvm/test/Transforms/PhaseOrdering/switch_with_geps.ll (revision 29441e4f5fa5f5c7709f7cf180815ba97f611297)
1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 3
2; RUN: opt -S -passes='default<O1>' < %s | FileCheck %s
3; RUN: opt -S -passes='default<O2>' < %s | FileCheck %s
4; RUN: opt -S -passes="default<O3>" < %s | FileCheck %s
5
6target datalayout = "n64"
7
8%"OpKind::Zero" = type { [1 x i32], i32 }
9%"OpKind::One" = type { [1 x i32], i32, i16, [1 x i16] }
10%"OpKind::Two" = type { [1 x i32], i32, i16, i16 }
11%"OpKind::Three" = type { [1 x i32], i32, i16, i16, i16, [1 x i16] }
12
13define i32 @test(ptr %ptr) {
14; CHECK-LABEL: define i32 @test(
15; CHECK-SAME: ptr readonly captures(none) [[PTR:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] {
16; CHECK-NEXT:  start:
17; CHECK-NEXT:    [[PHI:%.*]] = getelementptr inbounds nuw i8, ptr [[PTR]], i64 4
18; CHECK-NEXT:    [[RET:%.*]] = load i32, ptr [[PHI]], align 4
19; CHECK-NEXT:    ret i32 [[RET]]
20;
21start:
22  %t = load i32, ptr %ptr, align 4
23  switch i32 %t, label %default [
24  i32 0, label %bb4
25  i32 1, label %bb5
26  i32 2, label %bb6
27  i32 3, label %bb7
28  ]
29
30default:
31  unreachable
32
33bb4:
34  %gep0 = getelementptr inbounds %"OpKind::Zero", ptr %ptr, i64 0, i32 1
35  br label %exit
36
37bb5:
38  %gep1 = getelementptr inbounds %"OpKind::One", ptr %ptr, i64 0, i32 1
39  br label %exit
40
41bb6:
42  %gep2 = getelementptr inbounds %"OpKind::Two", ptr %ptr, i64 0, i32 1
43  br label %exit
44
45bb7:
46  %gep3 = getelementptr inbounds %"OpKind::Three", ptr %ptr, i64 0, i32 1
47  br label %exit
48
49exit:
50  %phi = phi ptr [ %gep3, %bb7 ], [ %gep2, %bb6 ], [ %gep1, %bb5 ], [ %gep0, %bb4 ]
51  %ret = load i32, ptr %phi, align 4
52  ret i32 %ret
53}
54
55%X = type { i64, i64, i64, i64, i64, i64 }
56
57define void @test2(ptr %self, i64 %v, i64 %ix) {
58; CHECK-LABEL: define void @test2(
59; CHECK-SAME: ptr writeonly captures(none) [[SELF:%.*]], i64 [[V:%.*]], i64 [[IX:%.*]]) local_unnamed_addr #[[ATTR1:[0-9]+]] {
60; CHECK-NEXT:  start:
61; CHECK-NEXT:    [[SWITCH_TABLEIDX:%.*]] = shl i64 [[IX]], 3
62; CHECK-NEXT:    [[GEP5:%.*]] = getelementptr inbounds nuw i8, ptr [[SELF]], i64 [[SWITCH_TABLEIDX]]
63; CHECK-NEXT:    store i64 [[V]], ptr [[GEP5]], align 8
64; CHECK-NEXT:    ret void
65;
66start:
67  switch i64 %ix, label %default [
68  i64 1, label %bb3
69  i64 2, label %bb4
70  i64 3, label %bb5
71  i64 4, label %bb6
72  i64 5, label %bb7
73  ]
74
75default:
76  unreachable
77
78bb3:
79  %gep1 = getelementptr inbounds %X, ptr %self, i64 0, i32 1
80  br label %bb8
81
82bb4:
83  %gep2 = getelementptr inbounds %X, ptr %self, i64 0, i32 2
84  br label %bb8
85
86bb5:
87  %gep3 = getelementptr inbounds %X, ptr %self, i64 0, i32 3
88  br label %bb8
89
90bb6:
91  %gep4 = getelementptr inbounds %X, ptr %self, i64 0, i32 4
92  br label %bb8
93
94bb7:
95  %gep5 = getelementptr inbounds %X, ptr %self, i64 0, i32 5
96  br label %bb8
97
98bb8:
99  %ptr = phi ptr [ %gep5, %bb7 ], [ %gep4, %bb6 ], [ %gep3, %bb5 ], [ %gep2, %bb4 ], [ %gep1, %bb3 ]
100  store i64 %v, ptr %ptr, align 8
101  ret void
102}
103