xref: /llvm-project/llvm/test/Transforms/PhaseOrdering/cmp-logic.ll (revision 08c2f4eb7ab3e75eb9d2048f73ea9874c663fb5a)
1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2; RUN: opt -passes='default<O1>' -S < %s | FileCheck %s --check-prefixes=CHECK,O1
3; RUN: opt -passes='default<Oz>' -S < %s | FileCheck %s --check-prefixes=CHECK,OZ
4
5target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
6
7%struct.a = type { i32 }
8
9define i32 @PR38781(i32 noundef %a, i32 noundef %b) {
10; CHECK-LABEL: @PR38781(
11; CHECK-NEXT:    [[TMP1:%.*]] = or i32 [[B:%.*]], [[A:%.*]]
12; CHECK-NEXT:    [[AND1:%.*]] = icmp sgt i32 [[TMP1]], -1
13; CHECK-NEXT:    [[AND:%.*]] = zext i1 [[AND1]] to i32
14; CHECK-NEXT:    ret i32 [[AND]]
15;
16  %cmp = icmp sge i32 %a, 0
17  %conv = zext i1 %cmp to i32
18  %cmp1 = icmp sge i32 %b, 0
19  %conv2 = zext i1 %cmp1 to i32
20  %and = and i32 %conv, %conv2
21  ret i32 %and
22}
23
24define i1 @PR54692_a(i8 noundef signext %c) #0 {
25; CHECK-LABEL: @PR54692_a(
26; CHECK-NEXT:  entry:
27; CHECK-NEXT:    [[TMP0:%.*]] = icmp ult i8 [[C:%.*]], 32
28; CHECK-NEXT:    [[CMP5:%.*]] = icmp eq i8 [[C]], 127
29; CHECK-NEXT:    [[OR1:%.*]] = or i1 [[TMP0]], [[CMP5]]
30; CHECK-NEXT:    ret i1 [[OR1]]
31;
32entry:
33  %conv = sext i8 %c to i32
34  %cmp = icmp sge i32 %conv, 0
35  br i1 %cmp, label %land.rhs, label %land.end
36
37land.rhs:
38  %conv1 = sext i8 %c to i32
39  %cmp2 = icmp sle i32 %conv1, 31
40  br label %land.end
41
42land.end:
43  %0 = phi i1 [ false, %entry ], [ %cmp2, %land.rhs ]
44  %conv3 = zext i1 %0 to i32
45  %conv4 = sext i8 %c to i32
46  %cmp5 = icmp eq i32 %conv4, 127
47  %conv6 = zext i1 %cmp5 to i32
48  %or = or i32 %conv3, %conv6
49  %tobool = icmp ne i32 %or, 0
50  ret i1 %tobool
51}
52
53define i1 @PR54692_b(i8 noundef signext %c) {
54; CHECK-LABEL: @PR54692_b(
55; CHECK-NEXT:  entry:
56; CHECK-NEXT:    [[AND1:%.*]] = icmp ult i8 [[C:%.*]], 32
57; CHECK-NEXT:    [[CMP6:%.*]] = icmp eq i8 [[C]], 127
58; CHECK-NEXT:    [[OR2:%.*]] = or i1 [[AND1]], [[CMP6]]
59; CHECK-NEXT:    ret i1 [[OR2]]
60;
61entry:
62  %conv = sext i8 %c to i32
63  %cmp = icmp sge i32 %conv, 0
64  %conv1 = zext i1 %cmp to i32
65  %conv2 = sext i8 %c to i32
66  %cmp3 = icmp sle i32 %conv2, 31
67  %conv4 = zext i1 %cmp3 to i32
68  %and = and i32 %conv1, %conv4
69  %conv5 = sext i8 %c to i32
70  %cmp6 = icmp eq i32 %conv5, 127
71  %conv7 = zext i1 %cmp6 to i32
72  %or = or i32 %and, %conv7
73  %tobool = icmp ne i32 %or, 0
74  ret i1 %tobool
75}
76
77define i1 @PR54692_c(i8 noundef signext %c) {
78; CHECK-LABEL: @PR54692_c(
79; CHECK-NEXT:  entry:
80; CHECK-NEXT:    [[AND1:%.*]] = icmp ult i8 [[C:%.*]], 32
81; CHECK-NEXT:    [[CMP6:%.*]] = icmp eq i8 [[C]], 127
82; CHECK-NEXT:    [[T0:%.*]] = or i1 [[AND1]], [[CMP6]]
83; CHECK-NEXT:    ret i1 [[T0]]
84;
85entry:
86  %conv = sext i8 %c to i32
87  %cmp = icmp sge i32 %conv, 0
88  %conv1 = zext i1 %cmp to i32
89  %conv2 = sext i8 %c to i32
90  %cmp3 = icmp sle i32 %conv2, 31
91  %conv4 = zext i1 %cmp3 to i32
92  %and = and i32 %conv1, %conv4
93  %tobool = icmp ne i32 %and, 0
94  br i1 %tobool, label %lor.end, label %lor.rhs
95
96lor.rhs:
97  %conv5 = sext i8 %c to i32
98  %cmp6 = icmp eq i32 %conv5, 127
99  br label %lor.end
100
101lor.end:
102  %t0 = phi i1 [ true, %entry ], [ %cmp6, %lor.rhs ]
103  ret i1 %t0
104}
105
106@c = global i32 0, align 4
107
108declare void @foo(...) #3
109
110define i32 @PR56119(i32 %e.coerce) {
111; O1-LABEL: @PR56119(
112; O1-NEXT:  entry:
113; O1-NEXT:    [[CONV2:%.*]] = and i32 [[E_COERCE:%.*]], 255
114; O1-NEXT:    [[REM:%.*]] = urem i32 [[CONV2]], 255
115; O1-NEXT:    [[CMP:%.*]] = icmp eq i32 [[REM]], 7
116; O1-NEXT:    br i1 [[CMP]], label [[IF_THEN:%.*]], label [[IF_END:%.*]]
117; O1:       if.then:
118; O1-NEXT:    tail call void (...) @foo()
119; O1-NEXT:    br label [[IF_END]]
120; O1:       if.end:
121; O1-NEXT:    [[TMP0:%.*]] = load i32, ptr @c, align 4
122; O1-NEXT:    ret i32 [[TMP0]]
123;
124; OZ-LABEL: @PR56119(
125; OZ-NEXT:  entry:
126; OZ-NEXT:    [[E_COERCE_FR:%.*]] = freeze i32 [[E_COERCE:%.*]]
127; OZ-NEXT:    [[CONV2:%.*]] = and i32 [[E_COERCE_FR]], 255
128; OZ-NEXT:    [[CMP1:%.*]] = icmp eq i32 [[CONV2]], 7
129; OZ-NEXT:    br i1 [[CMP1]], label [[IF_THEN:%.*]], label [[IF_END:%.*]]
130; OZ:       if.then:
131; OZ-NEXT:    tail call void (...) @foo()
132; OZ-NEXT:    br label [[IF_END]]
133; OZ:       if.end:
134; OZ-NEXT:    [[TMP0:%.*]] = load i32, ptr @c, align 4
135; OZ-NEXT:    ret i32 [[TMP0]]
136;
137entry:
138  %e = alloca %struct.a, align 4
139  store i32 %e.coerce, ptr %e, align 4
140  %0 = load i32, ptr %e, align 4
141  %conv = trunc i32 %0 to i8
142  %conv1 = trunc i64 -1 to i8
143  %conv2 = zext i8 %conv to i32
144  %conv3 = zext i8 %conv1 to i32
145  %rem = srem i32 %conv2, %conv3
146  %conv4 = trunc i32 %rem to i8
147  %conv5 = sext i8 %conv4 to i32
148  %cmp = icmp eq i32 7, %conv5
149  br i1 %cmp, label %if.then, label %if.end
150
151if.then:
152  call void (...) @foo() #5
153  br label %if.end
154
155if.end:
156  %1 = load i32, ptr @c, align 4
157  ret i32 %1
158}
159