1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 2; RUN: opt -O2 -S -mattr=avx < %s | FileCheck %s 3; RUN: opt -passes="default<O2>" -S -mattr=avx < %s | FileCheck %s 4 5target triple = "x86_64--" 6target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" 7 8define i32 @ext_ext_or_reduction_v4i32(<4 x i32> %x, <4 x i32> %y) { 9; CHECK-LABEL: @ext_ext_or_reduction_v4i32( 10; CHECK-NEXT: [[Z:%.*]] = and <4 x i32> [[Y:%.*]], [[X:%.*]] 11; CHECK-NEXT: [[TMP1:%.*]] = tail call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> [[Z]]) 12; CHECK-NEXT: ret i32 [[TMP1]] 13; 14 %z = and <4 x i32> %x, %y 15 %z0 = extractelement <4 x i32> %z, i32 0 16 %z1 = extractelement <4 x i32> %z, i32 1 17 %z01 = or i32 %z0, %z1 18 %z2 = extractelement <4 x i32> %z, i32 2 19 %z012 = or i32 %z01, %z2 20 %z3 = extractelement <4 x i32> %z, i32 3 21 %z0123 = or i32 %z3, %z012 22 ret i32 %z0123 23} 24 25define i32 @ext_ext_partial_add_reduction_v4i32(<4 x i32> %x) { 26; CHECK-LABEL: @ext_ext_partial_add_reduction_v4i32( 27; CHECK-NEXT: [[SHIFT:%.*]] = shufflevector <4 x i32> [[X:%.*]], <4 x i32> poison, <4 x i32> <i32 1, i32 poison, i32 poison, i32 poison> 28; CHECK-NEXT: [[TMP1:%.*]] = add <4 x i32> [[SHIFT]], [[X]] 29; CHECK-NEXT: [[SHIFT1:%.*]] = shufflevector <4 x i32> [[X]], <4 x i32> poison, <4 x i32> <i32 2, i32 poison, i32 poison, i32 poison> 30; CHECK-NEXT: [[TMP2:%.*]] = add <4 x i32> [[TMP1]], [[SHIFT1]] 31; CHECK-NEXT: [[X210:%.*]] = extractelement <4 x i32> [[TMP2]], i64 0 32; CHECK-NEXT: ret i32 [[X210]] 33; 34 %x0 = extractelement <4 x i32> %x, i32 0 35 %x1 = extractelement <4 x i32> %x, i32 1 36 %x10 = add i32 %x1, %x0 37 %x2 = extractelement <4 x i32> %x, i32 2 38 %x210 = add i32 %x2, %x10 39 ret i32 %x210 40} 41 42define i32 @ext_ext_partial_add_reduction_and_extra_add_v4i32(<4 x i32> %x, <4 x i32> %y) { 43; CHECK-LABEL: @ext_ext_partial_add_reduction_and_extra_add_v4i32( 44; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[Y:%.*]], <4 x i32> [[X:%.*]], <4 x i32> <i32 0, i32 1, i32 2, i32 6> 45; CHECK-NEXT: [[TMP2:%.*]] = tail call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP1]]) 46; CHECK-NEXT: ret i32 [[TMP2]] 47; 48 %y0 = extractelement <4 x i32> %y, i32 0 49 %y1 = extractelement <4 x i32> %y, i32 1 50 %y10 = add i32 %y1, %y0 51 %y2 = extractelement <4 x i32> %y, i32 2 52 %y210 = add i32 %y2, %y10 53 %x2 = extractelement <4 x i32> %x, i32 2 54 %x2y210 = add i32 %x2, %y210 55 ret i32 %x2y210 56} 57 58; PR43953 - https://bugs.llvm.org/show_bug.cgi?id=43953 59; We want to end up with a single reduction on the next 4 tests. 60 61define i32 @TestVectorsEqual(ptr noalias %Vec0, ptr noalias %Vec1, i32 %Tolerance) { 62; CHECK-LABEL: @TestVectorsEqual( 63; CHECK-NEXT: entry: 64; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i32>, ptr [[VEC0:%.*]], align 4 65; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr [[VEC1:%.*]], align 4 66; CHECK-NEXT: [[TMP2:%.*]] = sub nsw <4 x i32> [[TMP0]], [[TMP1]] 67; CHECK-NEXT: [[TMP3:%.*]] = tail call <4 x i32> @llvm.abs.v4i32(<4 x i32> [[TMP2]], i1 true) 68; CHECK-NEXT: [[TMP4:%.*]] = tail call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP3]]) 69; CHECK-NEXT: [[CMP5_NOT:%.*]] = icmp sle i32 [[TMP4]], [[TOLERANCE:%.*]] 70; CHECK-NEXT: [[COND6:%.*]] = zext i1 [[CMP5_NOT]] to i32 71; CHECK-NEXT: ret i32 [[COND6]] 72; 73entry: 74 br label %for.cond 75 76for.cond: 77 %sum.0 = phi i32 [ 0, %entry ], [ %add, %for.inc ] 78 %Component.0 = phi i32 [ 0, %entry ], [ %inc, %for.inc ] 79 %cmp = icmp slt i32 %Component.0, 4 80 br i1 %cmp, label %for.body, label %for.cond.cleanup 81 82for.cond.cleanup: 83 br label %for.end 84 85for.body: 86 %idxprom = sext i32 %Component.0 to i64 87 %arrayidx = getelementptr inbounds i32, ptr %Vec0, i64 %idxprom 88 %0 = load i32, ptr %arrayidx, align 4 89 %idxprom1 = sext i32 %Component.0 to i64 90 %arrayidx2 = getelementptr inbounds i32, ptr %Vec1, i64 %idxprom1 91 %1 = load i32, ptr %arrayidx2, align 4 92 %sub = sub nsw i32 %0, %1 93 %cmp3 = icmp sge i32 %sub, 0 94 br i1 %cmp3, label %cond.true, label %cond.false 95 96cond.true: 97 br label %cond.end 98 99cond.false: 100 %sub4 = sub nsw i32 0, %sub 101 br label %cond.end 102 103cond.end: 104 %cond = phi i32 [ %sub, %cond.true ], [ %sub4, %cond.false ] 105 %add = add nsw i32 %sum.0, %cond 106 br label %for.inc 107 108for.inc: 109 %inc = add nsw i32 %Component.0, 1 110 br label %for.cond 111 112for.end: 113 %cmp5 = icmp sle i32 %sum.0, %Tolerance 114 %2 = zext i1 %cmp5 to i64 115 %cond6 = select i1 %cmp5, i32 1, i32 0 116 ret i32 %cond6 117} 118 119define i32 @TestVectorsEqual_alt(ptr noalias %Vec0, ptr noalias %Vec1, i32 %Tolerance) { 120; CHECK-LABEL: @TestVectorsEqual_alt( 121; CHECK-NEXT: entry: 122; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i32>, ptr [[VEC0:%.*]], align 4 123; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr [[VEC1:%.*]], align 4 124; CHECK-NEXT: [[TMP2:%.*]] = sub <4 x i32> [[TMP0]], [[TMP1]] 125; CHECK-NEXT: [[ADD_3:%.*]] = tail call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP2]]) 126; CHECK-NEXT: [[CMP3_NOT:%.*]] = icmp ule i32 [[ADD_3]], [[TOLERANCE:%.*]] 127; CHECK-NEXT: [[COND:%.*]] = zext i1 [[CMP3_NOT]] to i32 128; CHECK-NEXT: ret i32 [[COND]] 129; 130entry: 131 br label %for.cond 132 133for.cond: 134 %sum.0 = phi i32 [ 0, %entry ], [ %add, %for.inc ] 135 %Component.0 = phi i32 [ 0, %entry ], [ %inc, %for.inc ] 136 %cmp = icmp slt i32 %Component.0, 4 137 br i1 %cmp, label %for.body, label %for.cond.cleanup 138 139for.cond.cleanup: 140 br label %for.end 141 142for.body: 143 %idxprom = sext i32 %Component.0 to i64 144 %arrayidx = getelementptr inbounds i32, ptr %Vec0, i64 %idxprom 145 %0 = load i32, ptr %arrayidx, align 4 146 %idxprom1 = sext i32 %Component.0 to i64 147 %arrayidx2 = getelementptr inbounds i32, ptr %Vec1, i64 %idxprom1 148 %1 = load i32, ptr %arrayidx2, align 4 149 %sub = sub i32 %0, %1 150 %add = add i32 %sum.0, %sub 151 br label %for.inc 152 153for.inc: 154 %inc = add nsw i32 %Component.0, 1 155 br label %for.cond 156 157for.end: 158 %cmp3 = icmp ule i32 %sum.0, %Tolerance 159 %2 = zext i1 %cmp3 to i64 160 %cond = select i1 %cmp3, i32 1, i32 0 161 ret i32 %cond 162} 163 164define i32 @TestVectorsEqualFP(ptr noalias %Vec0, ptr noalias %Vec1, float %Tolerance) { 165; CHECK-LABEL: @TestVectorsEqualFP( 166; CHECK-NEXT: entry: 167; CHECK-NEXT: [[TMP0:%.*]] = load <4 x float>, ptr [[VEC0:%.*]], align 4 168; CHECK-NEXT: [[TMP1:%.*]] = load <4 x float>, ptr [[VEC1:%.*]], align 4 169; CHECK-NEXT: [[TMP2:%.*]] = fsub fast <4 x float> [[TMP0]], [[TMP1]] 170; CHECK-NEXT: [[TMP3:%.*]] = tail call fast <4 x float> @llvm.fabs.v4f32(<4 x float> [[TMP2]]) 171; CHECK-NEXT: [[TMP4:%.*]] = tail call fast float @llvm.vector.reduce.fadd.v4f32(float 0.000000e+00, <4 x float> [[TMP3]]) 172; CHECK-NEXT: [[CMP4:%.*]] = fcmp fast ole float [[TMP4]], [[TOLERANCE:%.*]] 173; CHECK-NEXT: [[COND5:%.*]] = zext i1 [[CMP4]] to i32 174; CHECK-NEXT: ret i32 [[COND5]] 175; 176entry: 177 br label %for.cond 178 179for.cond: 180 %sum.0 = phi float [ 0.000000e+00, %entry ], [ %add, %for.inc ] 181 %Component.0 = phi i32 [ 0, %entry ], [ %inc, %for.inc ] 182 %cmp = icmp slt i32 %Component.0, 4 183 br i1 %cmp, label %for.body, label %for.cond.cleanup 184 185for.cond.cleanup: 186 br label %for.end 187 188for.body: 189 %idxprom = sext i32 %Component.0 to i64 190 %arrayidx = getelementptr inbounds float, ptr %Vec0, i64 %idxprom 191 %0 = load float, ptr %arrayidx, align 4 192 %idxprom1 = sext i32 %Component.0 to i64 193 %arrayidx2 = getelementptr inbounds float, ptr %Vec1, i64 %idxprom1 194 %1 = load float, ptr %arrayidx2, align 4 195 %sub = fsub fast float %0, %1 196 %cmp3 = fcmp fast oge float %sub, 0.000000e+00 197 br i1 %cmp3, label %cond.true, label %cond.false 198 199cond.true: 200 br label %cond.end 201 202cond.false: 203 %fneg = fneg fast float %sub 204 br label %cond.end 205 206cond.end: 207 %cond = phi fast float [ %sub, %cond.true ], [ %fneg, %cond.false ] 208 %add = fadd fast float %sum.0, %cond 209 br label %for.inc 210 211for.inc: 212 %inc = add nsw i32 %Component.0, 1 213 br label %for.cond 214 215for.end: 216 %cmp4 = fcmp fast ole float %sum.0, %Tolerance 217 %2 = zext i1 %cmp4 to i64 218 %cond5 = select i1 %cmp4, i32 1, i32 0 219 ret i32 %cond5 220} 221 222define i32 @TestVectorsEqualFP_alt(ptr noalias %Vec0, ptr noalias %Vec1, float %Tolerance) { 223; CHECK-LABEL: @TestVectorsEqualFP_alt( 224; CHECK-NEXT: entry: 225; CHECK-NEXT: [[TMP0:%.*]] = load <4 x float>, ptr [[VEC0:%.*]], align 4 226; CHECK-NEXT: [[TMP1:%.*]] = load <4 x float>, ptr [[VEC1:%.*]], align 4 227; CHECK-NEXT: [[TMP2:%.*]] = fsub fast <4 x float> [[TMP0]], [[TMP1]] 228; CHECK-NEXT: [[TMP3:%.*]] = tail call fast float @llvm.vector.reduce.fadd.v4f32(float 0.000000e+00, <4 x float> [[TMP2]]) 229; CHECK-NEXT: [[CMP3:%.*]] = fcmp fast ole float [[TMP3]], [[TOLERANCE:%.*]] 230; CHECK-NEXT: [[COND:%.*]] = zext i1 [[CMP3]] to i32 231; CHECK-NEXT: ret i32 [[COND]] 232; 233entry: 234 br label %for.cond 235 236for.cond: 237 %sum.0 = phi float [ 0.000000e+00, %entry ], [ %add, %for.inc ] 238 %Component.0 = phi i32 [ 0, %entry ], [ %inc, %for.inc ] 239 %cmp = icmp slt i32 %Component.0, 4 240 br i1 %cmp, label %for.body, label %for.cond.cleanup 241 242for.cond.cleanup: 243 br label %for.end 244 245for.body: 246 %idxprom = sext i32 %Component.0 to i64 247 %arrayidx = getelementptr inbounds float, ptr %Vec0, i64 %idxprom 248 %0 = load float, ptr %arrayidx, align 4 249 %idxprom1 = sext i32 %Component.0 to i64 250 %arrayidx2 = getelementptr inbounds float, ptr %Vec1, i64 %idxprom1 251 %1 = load float, ptr %arrayidx2, align 4 252 %sub = fsub fast float %0, %1 253 %add = fadd fast float %sum.0, %sub 254 br label %for.inc 255 256for.inc: 257 %inc = add nsw i32 %Component.0, 1 258 br label %for.cond 259 260for.end: 261 %cmp3 = fcmp fast ole float %sum.0, %Tolerance 262 %2 = zext i1 %cmp3 to i64 263 %cond = select i1 %cmp3, i32 1, i32 0 264 ret i32 %cond 265} 266 267; PR43745 - https://bugs.llvm.org/show_bug.cgi?id=43745 268 269; FIXME: this should be vectorized 270define i1 @cmp_lt_gt(double %a, double %b, double %c) { 271; CHECK-LABEL: @cmp_lt_gt( 272; CHECK-NEXT: entry: 273; CHECK-NEXT: [[FNEG:%.*]] = fneg double [[B:%.*]] 274; CHECK-NEXT: [[MUL:%.*]] = fmul double [[A:%.*]], 2.000000e+00 275; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x double> poison, double [[C:%.*]], i64 0 276; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x double> [[TMP0]], double [[FNEG]], i64 1 277; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x double> poison, double [[B]], i64 0 278; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x double> [[TMP2]], double [[C]], i64 1 279; CHECK-NEXT: [[TMP4:%.*]] = fsub <2 x double> [[TMP1]], [[TMP3]] 280; CHECK-NEXT: [[TMP5:%.*]] = insertelement <2 x double> poison, double [[MUL]], i64 0 281; CHECK-NEXT: [[TMP6:%.*]] = shufflevector <2 x double> [[TMP5]], <2 x double> poison, <2 x i32> zeroinitializer 282; CHECK-NEXT: [[TMP7:%.*]] = fdiv <2 x double> [[TMP4]], [[TMP6]] 283; CHECK-NEXT: [[TMP8:%.*]] = fcmp olt <2 x double> [[TMP7]], splat (double 0x3EB0C6F7A0B5ED8D) 284; CHECK-NEXT: [[SHIFT:%.*]] = shufflevector <2 x i1> [[TMP8]], <2 x i1> poison, <2 x i32> <i32 1, i32 poison> 285; CHECK-NEXT: [[TMP9:%.*]] = and <2 x i1> [[TMP8]], [[SHIFT]] 286; CHECK-NEXT: [[OR_COND:%.*]] = extractelement <2 x i1> [[TMP9]], i64 0 287; CHECK-NEXT: [[TMP10:%.*]] = fcmp ule <2 x double> [[TMP7]], splat (double 1.000000e+00) 288; CHECK-NEXT: [[SHIFT2:%.*]] = shufflevector <2 x i1> [[TMP10]], <2 x i1> poison, <2 x i32> <i32 1, i32 poison> 289; CHECK-NEXT: [[TMP11:%.*]] = or <2 x i1> [[TMP10]], [[SHIFT2]] 290; CHECK-NEXT: [[OR_COND1_NOT:%.*]] = extractelement <2 x i1> [[TMP11]], i64 0 291; CHECK-NEXT: [[RETVAL_0:%.*]] = select i1 [[OR_COND]], i1 false, i1 [[OR_COND1_NOT]] 292; CHECK-NEXT: ret i1 [[RETVAL_0]] 293; 294entry: 295 %fneg = fneg double %b 296 %add = fadd double %fneg, %c 297 %mul = fmul double 2.0, %a 298 %div = fdiv double %add, %mul 299 %fneg1 = fneg double %b 300 %sub = fsub double %fneg1, %c 301 %mul2 = fmul double 2.0, %a 302 %div3 = fdiv double %sub, %mul2 303 %cmp = fcmp olt double %div, 0x3EB0C6F7A0B5ED8D 304 br i1 %cmp, label %land.lhs.true, label %lor.lhs.false 305 306land.lhs.true: 307 %cmp4 = fcmp olt double %div3, 0x3EB0C6F7A0B5ED8D 308 br i1 %cmp4, label %if.then, label %lor.lhs.false 309 310lor.lhs.false: 311 %cmp5 = fcmp ogt double %div, 1.0 312 br i1 %cmp5, label %land.lhs.true6, label %if.end 313 314land.lhs.true6: 315 %cmp7 = fcmp ogt double %div3, 1.0 316 br i1 %cmp7, label %if.then, label %if.end 317 318if.then: 319 br label %cleanup 320 321if.end: 322 br label %cleanup 323 324cleanup: 325 %retval.0 = phi i1 [ false, %if.then ], [ true, %if.end ] 326 ret i1 %retval.0 327} 328