1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 2; RUN: opt -O3 -S < %s | FileCheck %s 3; RUN: opt -passes="default<O3>" -S < %s | FileCheck %s 4 5target triple = "x86_64--" 6target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" 7 8; PR42174 - https://bugs.llvm.org/show_bug.cgi?id=42174 9; This test should match the IR produced by clang after running -mem2reg. 10; All math before the final 'add' should be scalarized. 11 12define <4 x i32> @square(<4 x i32> %num, i32 %y, i32 %x, i32 %h, i32 %k, i32 %w, i32 %p, i32 %j, i32 %u) { 13; CHECK-LABEL: @square( 14; CHECK-NEXT: [[DIV:%.*]] = sdiv i32 [[K:%.*]], 2 15; CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[P:%.*]], 6234 16; CHECK-NEXT: [[MUL5:%.*]] = mul nsw i32 [[H:%.*]], 75 17; CHECK-NEXT: [[DIV9:%.*]] = sdiv i32 [[J:%.*]], 3452 18; CHECK-NEXT: [[MUL13:%.*]] = mul nsw i32 [[W:%.*]], 53 19; CHECK-NEXT: [[DIV17:%.*]] = sdiv i32 [[X:%.*]], 820 20; CHECK-NEXT: [[MUL21:%.*]] = shl nsw i32 [[U:%.*]], 2 21; CHECK-NEXT: [[OP_RDX:%.*]] = add nsw i32 [[DIV17]], 317426 22; CHECK-NEXT: [[OP_RDX9:%.*]] = add nsw i32 [[DIV]], [[DIV9]] 23; CHECK-NEXT: [[OP_RDX10:%.*]] = add i32 [[MUL5]], [[MUL13]] 24; CHECK-NEXT: [[OP_RDX11:%.*]] = add i32 [[MUL]], [[MUL21]] 25; CHECK-NEXT: [[OP_RDX12:%.*]] = add i32 [[OP_RDX]], [[OP_RDX9]] 26; CHECK-NEXT: [[OP_RDX13:%.*]] = add i32 [[OP_RDX10]], [[OP_RDX11]] 27; CHECK-NEXT: [[OP_RDX14:%.*]] = add i32 [[OP_RDX12]], [[OP_RDX13]] 28; CHECK-NEXT: [[OP_RDX15:%.*]] = add i32 [[OP_RDX14]], [[Y:%.*]] 29; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> poison, i32 [[OP_RDX15]], i64 0 30; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> poison, <4 x i32> zeroinitializer 31; CHECK-NEXT: [[ADD29:%.*]] = add <4 x i32> [[TMP2]], [[NUM:%.*]] 32; CHECK-NEXT: ret <4 x i32> [[ADD29]] 33; 34 %add = add <4 x i32> %num, <i32 1, i32 1, i32 1, i32 1> 35 %div = sdiv i32 %k, 2 36 %splatinsert = insertelement <4 x i32> undef, i32 %div, i32 0 37 %splat = shufflevector <4 x i32> %splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 38 %add1 = add <4 x i32> %add, %splat 39 %mul = mul nsw i32 %p, 6234 40 %splatinsert2 = insertelement <4 x i32> undef, i32 %mul, i32 0 41 %splat3 = shufflevector <4 x i32> %splatinsert2, <4 x i32> undef, <4 x i32> zeroinitializer 42 %add4 = add <4 x i32> %add1, %splat3 43 %mul5 = mul nsw i32 75, %h 44 %splatinsert6 = insertelement <4 x i32> undef, i32 %mul5, i32 0 45 %splat7 = shufflevector <4 x i32> %splatinsert6, <4 x i32> undef, <4 x i32> zeroinitializer 46 %add8 = add <4 x i32> %add4, %splat7 47 %div9 = sdiv i32 %j, 3452 48 %splatinsert10 = insertelement <4 x i32> undef, i32 %div9, i32 0 49 %splat11 = shufflevector <4 x i32> %splatinsert10, <4 x i32> undef, <4 x i32> zeroinitializer 50 %add12 = add <4 x i32> %add8, %splat11 51 %mul13 = mul nsw i32 53, %w 52 %splatinsert14 = insertelement <4 x i32> undef, i32 %mul13, i32 0 53 %splat15 = shufflevector <4 x i32> %splatinsert14, <4 x i32> undef, <4 x i32> zeroinitializer 54 %add16 = add <4 x i32> %add12, %splat15 55 %div17 = sdiv i32 %x, 820 56 %splatinsert18 = insertelement <4 x i32> undef, i32 %div17, i32 0 57 %splat19 = shufflevector <4 x i32> %splatinsert18, <4 x i32> undef, <4 x i32> zeroinitializer 58 %add20 = add <4 x i32> %add16, %splat19 59 %mul21 = mul nsw i32 4, %u 60 %splatinsert22 = insertelement <4 x i32> undef, i32 %mul21, i32 0 61 %splat23 = shufflevector <4 x i32> %splatinsert22, <4 x i32> undef, <4 x i32> zeroinitializer 62 %add24 = add <4 x i32> %add20, %splat23 63 %splatinsert25 = insertelement <4 x i32> undef, i32 %y, i32 0 64 %splat26 = shufflevector <4 x i32> %splatinsert25, <4 x i32> undef, <4 x i32> zeroinitializer 65 %add27 = add <4 x i32> %add24, %splat26 66 %add28 = add <4 x i32> %add27, <i32 25, i32 25, i32 25, i32 25> 67 %add29 = add <4 x i32> %add28, <i32 317400, i32 317400, i32 317400, i32 317400> 68 ret <4 x i32> %add29 69} 70 71