1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5 2; RUN: opt -passes="default<O3>" -enable-merge-functions -S < %s | FileCheck %s 3 4target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128" 5target triple = "x86_64-apple-macosx12.0.0" 6 7define i32 @f(i32 noundef %x) { 8; CHECK-LABEL: define range(i32 0, 2) i32 @f( 9; CHECK-SAME: i32 noundef [[X:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] { 10; CHECK-NEXT: [[ENTRY:.*]]: 11; CHECK-NEXT: [[TMP0:%.*]] = icmp ult i32 [[X]], 8 12; CHECK-NEXT: br i1 [[TMP0]], label %[[SWITCH_LOOKUP:.*]], label %[[SW_EPILOG:.*]] 13; CHECK: [[SWITCH_LOOKUP]]: 14; CHECK-NEXT: [[TMP1:%.*]] = zext nneg i32 [[X]] to i64 15; CHECK-NEXT: [[SWITCH_GEP:%.*]] = getelementptr inbounds nuw [8 x i32], ptr @switch.table.g, i64 0, i64 [[TMP1]] 16; CHECK-NEXT: [[SWITCH_LOAD:%.*]] = load i32, ptr [[SWITCH_GEP]], align 4 17; CHECK-NEXT: br label %[[SW_EPILOG]] 18; CHECK: [[SW_EPILOG]]: 19; CHECK-NEXT: [[X_ADDR_0:%.*]] = phi i32 [ [[SWITCH_LOAD]], %[[SWITCH_LOOKUP]] ], [ 0, %[[ENTRY]] ] 20; CHECK-NEXT: ret i32 [[X_ADDR_0]] 21; 22entry: 23 %x.addr = alloca i32, align 4 24 store i32 %x, ptr %x.addr, align 4 25 %0 = load i32, ptr %x.addr, align 4 26 switch i32 %0, label %sw.default [ 27 i32 0, label %sw.bb 28 i32 2, label %sw.bb 29 i32 4, label %sw.bb 30 i32 6, label %sw.bb 31 i32 7, label %sw.bb 32 ] 33 34sw.bb: ; preds = %entry, %entry, %entry, %entry, %entry 35 store i32 1, ptr %x.addr, align 4 36 br label %sw.epilog 37 38sw.default: ; preds = %entry 39 store i32 0, ptr %x.addr, align 4 40 br label %sw.epilog 41 42sw.epilog: ; preds = %sw.default, %sw.bb 43 %1 = load i32, ptr %x.addr, align 4 44 ret i32 %1 45} 46 47define i32 @g(i32 noundef %x) { 48; CHECK-LABEL: define range(i32 0, 2) i32 @g( 49; CHECK-SAME: i32 noundef [[TMP0:%.*]]) local_unnamed_addr #[[ATTR0]] { 50; CHECK-NEXT: [[TMP2:%.*]] = tail call range(i32 0, 2) i32 @f(i32 noundef [[TMP0]]) #[[ATTR0]] 51; CHECK-NEXT: ret i32 [[TMP2]] 52; 53entry: 54 %x.addr = alloca i32, align 4 55 store i32 %x, ptr %x.addr, align 4 56 %0 = load i32, ptr %x.addr, align 4 57 switch i32 %0, label %sw.default [ 58 i32 0, label %sw.bb 59 i32 2, label %sw.bb 60 i32 4, label %sw.bb 61 i32 6, label %sw.bb 62 i32 7, label %sw.bb 63 ] 64 65sw.bb: ; preds = %entry, %entry, %entry, %entry, %entry 66 store i32 1, ptr %x.addr, align 4 67 br label %sw.epilog 68 69sw.default: ; preds = %entry 70 store i32 0, ptr %x.addr, align 4 71 br label %sw.epilog 72 73sw.epilog: ; preds = %sw.default, %sw.bb 74 %1 = load i32, ptr %x.addr, align 4 75 ret i32 %1 76} 77