1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 2; RUN: opt < %s -passes="default<O3>" -S | FileCheck %s 3 4target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" 5target triple = "thumbv6m-none-none-eabi" 6 7; Make sure we don't make a mess of vectorization/unrolling of the remainder loop. 8 9define void @arm_mean_q7(ptr noundef %pSrc, i32 noundef %blockSize, ptr noundef %pResult) #0 { 10; CHECK-LABEL: @arm_mean_q7( 11; CHECK-NEXT: entry: 12; CHECK-NEXT: [[CMP_NOT10:%.*]] = icmp ult i32 [[BLOCKSIZE:%.*]], 16 13; CHECK-NEXT: br i1 [[CMP_NOT10]], label [[WHILE_END:%.*]], label [[WHILE_BODY_PREHEADER:%.*]] 14; CHECK: while.body.preheader: 15; CHECK-NEXT: [[SHR:%.*]] = lshr i32 [[BLOCKSIZE]], 4 16; CHECK-NEXT: [[TMP0:%.*]] = and i32 [[BLOCKSIZE]], -16 17; CHECK-NEXT: br label [[WHILE_BODY:%.*]] 18; CHECK: while.body: 19; CHECK-NEXT: [[SUM_013:%.*]] = phi i32 [ [[TMP3:%.*]], [[WHILE_BODY]] ], [ 0, [[WHILE_BODY_PREHEADER]] ] 20; CHECK-NEXT: [[PSRC_ADDR_012:%.*]] = phi ptr [ [[ADD_PTR:%.*]], [[WHILE_BODY]] ], [ [[PSRC:%.*]], [[WHILE_BODY_PREHEADER]] ] 21; CHECK-NEXT: [[BLKCNT_011:%.*]] = phi i32 [ [[DEC:%.*]], [[WHILE_BODY]] ], [ [[SHR]], [[WHILE_BODY_PREHEADER]] ] 22; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr [[PSRC_ADDR_012]], align 1 23; CHECK-NEXT: [[TMP2:%.*]] = tail call i32 @llvm.arm.mve.addv.v16i8(<16 x i8> [[TMP1]], i32 0) 24; CHECK-NEXT: [[TMP3]] = add i32 [[TMP2]], [[SUM_013]] 25; CHECK-NEXT: [[DEC]] = add nsw i32 [[BLKCNT_011]], -1 26; CHECK-NEXT: [[ADD_PTR]] = getelementptr inbounds nuw i8, ptr [[PSRC_ADDR_012]], i32 16 27; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[DEC]], 0 28; CHECK-NEXT: br i1 [[CMP_NOT]], label [[WHILE_END_LOOPEXIT:%.*]], label [[WHILE_BODY]] 29; CHECK: while.end.loopexit: 30; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[PSRC]], i32 [[TMP0]] 31; CHECK-NEXT: br label [[WHILE_END]] 32; CHECK: while.end: 33; CHECK-NEXT: [[PSRC_ADDR_0_LCSSA:%.*]] = phi ptr [ [[PSRC]], [[ENTRY:%.*]] ], [ [[SCEVGEP]], [[WHILE_END_LOOPEXIT]] ] 34; CHECK-NEXT: [[SUM_0_LCSSA:%.*]] = phi i32 [ 0, [[ENTRY]] ], [ [[TMP3]], [[WHILE_END_LOOPEXIT]] ] 35; CHECK-NEXT: [[AND:%.*]] = and i32 [[BLOCKSIZE]], 15 36; CHECK-NEXT: [[CMP2_NOT15:%.*]] = icmp eq i32 [[AND]], 0 37; CHECK-NEXT: br i1 [[CMP2_NOT15]], label [[WHILE_END5:%.*]], label [[MIDDLE_BLOCK:%.*]] 38; CHECK: middle.block: 39; CHECK-NEXT: [[ACTIVE_LANE_MASK:%.*]] = tail call <16 x i1> @llvm.get.active.lane.mask.v16i1.i32(i32 0, i32 [[AND]]) 40; CHECK-NEXT: [[WIDE_MASKED_LOAD:%.*]] = tail call <16 x i8> @llvm.masked.load.v16i8.p0(ptr [[PSRC_ADDR_0_LCSSA]], i32 1, <16 x i1> [[ACTIVE_LANE_MASK]], <16 x i8> poison) 41; CHECK-NEXT: [[TMP4:%.*]] = sext <16 x i8> [[WIDE_MASKED_LOAD]] to <16 x i32> 42; CHECK-NEXT: [[TMP5:%.*]] = select <16 x i1> [[ACTIVE_LANE_MASK]], <16 x i32> [[TMP4]], <16 x i32> zeroinitializer 43; CHECK-NEXT: [[TMP6:%.*]] = tail call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> [[TMP5]]) 44; CHECK-NEXT: [[TMP7:%.*]] = add i32 [[TMP6]], [[SUM_0_LCSSA]] 45; CHECK-NEXT: br label [[WHILE_END5]] 46; CHECK: while.end5: 47; CHECK-NEXT: [[SUM_1_LCSSA:%.*]] = phi i32 [ [[SUM_0_LCSSA]], [[WHILE_END]] ], [ [[TMP7]], [[MIDDLE_BLOCK]] ] 48; CHECK-NEXT: [[DIV:%.*]] = sdiv i32 [[SUM_1_LCSSA]], [[BLOCKSIZE]] 49; CHECK-NEXT: [[CONV6:%.*]] = trunc i32 [[DIV]] to i8 50; CHECK-NEXT: store i8 [[CONV6]], ptr [[PRESULT:%.*]], align 1 51; CHECK-NEXT: ret void 52; 53entry: 54 %pSrc.addr = alloca ptr, align 4 55 %blockSize.addr = alloca i32, align 4 56 %pResult.addr = alloca ptr, align 4 57 %blkCnt = alloca i32, align 4 58 %vecSrc = alloca <16 x i8>, align 1 59 %sum = alloca i32, align 4 60 store ptr %pSrc, ptr %pSrc.addr, align 4 61 store i32 %blockSize, ptr %blockSize.addr, align 4 62 store ptr %pResult, ptr %pResult.addr, align 4 63 call void @llvm.lifetime.start.p0(i64 4, ptr %blkCnt) #3 64 call void @llvm.lifetime.start.p0(i64 16, ptr %vecSrc) #3 65 call void @llvm.lifetime.start.p0(i64 4, ptr %sum) #3 66 store i32 0, ptr %sum, align 4 67 %0 = load i32, ptr %blockSize.addr, align 4 68 %shr = lshr i32 %0, 4 69 store i32 %shr, ptr %blkCnt, align 4 70 br label %while.cond 71 72while.cond: ; preds = %while.body, %entry 73 %1 = load i32, ptr %blkCnt, align 4 74 %cmp = icmp ugt i32 %1, 0 75 br i1 %cmp, label %while.body, label %while.end 76 77while.body: ; preds = %while.cond 78 %2 = load ptr, ptr %pSrc.addr, align 4 79 %3 = load <16 x i8>, ptr %2, align 1 80 store <16 x i8> %3, ptr %vecSrc, align 1 81 %4 = load <16 x i8>, ptr %vecSrc, align 1 82 %5 = call i32 @llvm.arm.mve.addv.v16i8(<16 x i8> %4, i32 0) 83 %6 = load i32, ptr %sum, align 4 84 %7 = add i32 %5, %6 85 store i32 %7, ptr %sum, align 4 86 %8 = load i32, ptr %blkCnt, align 4 87 %dec = add i32 %8, -1 88 store i32 %dec, ptr %blkCnt, align 4 89 %9 = load ptr, ptr %pSrc.addr, align 4 90 %add.ptr = getelementptr inbounds i8, ptr %9, i32 16 91 store ptr %add.ptr, ptr %pSrc.addr, align 4 92 br label %while.cond 93 94while.end: ; preds = %while.cond 95 %10 = load i32, ptr %blockSize.addr, align 4 96 %and = and i32 %10, 15 97 store i32 %and, ptr %blkCnt, align 4 98 br label %while.cond1 99 100while.cond1: ; preds = %while.body3, %while.end 101 %11 = load i32, ptr %blkCnt, align 4 102 %cmp2 = icmp ugt i32 %11, 0 103 br i1 %cmp2, label %while.body3, label %while.end5 104 105while.body3: ; preds = %while.cond1 106 %12 = load ptr, ptr %pSrc.addr, align 4 107 %incdec.ptr = getelementptr inbounds i8, ptr %12, i32 1 108 store ptr %incdec.ptr, ptr %pSrc.addr, align 4 109 %13 = load i8, ptr %12, align 1 110 %conv = sext i8 %13 to i32 111 %14 = load i32, ptr %sum, align 4 112 %add = add nsw i32 %14, %conv 113 store i32 %add, ptr %sum, align 4 114 %15 = load i32, ptr %blkCnt, align 4 115 %dec4 = add i32 %15, -1 116 store i32 %dec4, ptr %blkCnt, align 4 117 br label %while.cond1 118 119while.end5: ; preds = %while.cond1 120 %16 = load i32, ptr %sum, align 4 121 %17 = load i32, ptr %blockSize.addr, align 4 122 %div = sdiv i32 %16, %17 123 %conv6 = trunc i32 %div to i8 124 %18 = load ptr, ptr %pResult.addr, align 4 125 store i8 %conv6, ptr %18, align 1 126 call void @llvm.lifetime.end.p0(i64 4, ptr %sum) #3 127 call void @llvm.lifetime.end.p0(i64 16, ptr %vecSrc) #3 128 call void @llvm.lifetime.end.p0(i64 4, ptr %blkCnt) #3 129 ret void 130} 131 132declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1 133declare i32 @llvm.arm.mve.addv.v16i8(<16 x i8>, i32) #2 134declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1 135 136attributes #0 = { nounwind "approx-func-fp-math"="true" "frame-pointer"="all" "min-legal-vector-width"="0" "no-infs-fp-math"="true" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="cortex-m55" "target-features"="+armv8.1-m.main,+dsp,+fp-armv8d16,+fp-armv8d16sp,+fp16,+fp64,+fullfp16,+hwdiv,+lob,+mve,+mve.fp,+ras,+strict-align,+thumb-mode,+vfp2,+vfp2sp,+vfp3d16,+vfp3d16sp,+vfp4d16,+vfp4d16sp,-aes,-bf16,-cdecp0,-cdecp1,-cdecp2,-cdecp3,-cdecp4,-cdecp5,-cdecp6,-cdecp7,-crc,-crypto,-d32,-dotprod,-fp-armv8,-fp-armv8sp,-fp16fml,-hwdiv-arm,-i8mm,-neon,-pacbti,-sb,-sha2,-vfp3,-vfp3sp,-vfp4,-vfp4sp" "unsafe-fp-math"="true" } 137attributes #1 = { argmemonly nocallback nofree nosync nounwind willreturn } 138attributes #2 = { nounwind readnone } 139attributes #3 = { nounwind } 140