1; RUN: opt < %s -passes=loop-vectorize -enable-vplan-native-path -vplan-build-stress-test -debug-only=loop-vectorize -disable-output 2>&1 | FileCheck %s 2; REQUIRES: asserts 3 4; Verify that the stress testing flag for the VPlan H-CFG builder works as 5; expected with and without enabling the VPlan H-CFG Verifier. 6 7; CHECK: VPlan 'HCFGBuilder: Plain CFG 8 9target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" 10 11define void @foo(ptr nocapture %a, ptr nocapture readonly %b, i32 %N, i32 %M) { 12entry: 13 %cmp32 = icmp sgt i32 %N, 0 14 br i1 %cmp32, label %outer.ph, label %for.end15 15 16outer.ph: 17 %cmp230 = icmp sgt i32 %M, 0 18 %0 = sext i32 %M to i64 19 %wide.trip.count = zext i32 %M to i64 20 %wide.trip.count38 = zext i32 %N to i64 21 br label %outer.body 22 23outer.body: 24 %indvars.iv35 = phi i64 [ 0, %outer.ph ], [ %indvars.iv.next36, %outer.inc ] 25 br i1 %cmp230, label %inner.ph, label %outer.inc 26 27inner.ph: 28 %1 = mul nsw i64 %indvars.iv35, %0 29 br label %inner.body 30 31inner.body: 32 %indvars.iv = phi i64 [ 0, %inner.ph ], [ %indvars.iv.next, %inner.body ] 33 %2 = add nsw i64 %indvars.iv, %1 34 %arrayidx = getelementptr inbounds i32, ptr %b, i64 %2 35 %3 = load i32, ptr %arrayidx, align 4 36 %arrayidx12 = getelementptr inbounds i32, ptr %a, i64 %2 37 store i32 %3, ptr %arrayidx12, align 4 38 %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 39 %exitcond = icmp eq i64 %indvars.iv.next, %wide.trip.count 40 br i1 %exitcond, label %outer.inc, label %inner.body 41 42outer.inc: 43 %indvars.iv.next36 = add nuw nsw i64 %indvars.iv35, 1 44 %exitcond39 = icmp eq i64 %indvars.iv.next36, %wide.trip.count38 45 br i1 %exitcond39, label %for.end15, label %outer.body 46 47for.end15: 48 ret void 49} 50