1; RUN: opt -passes=loop-vectorize -force-vector-width=8 -force-vector-interleave=2 -disable-output -debug -S %s 2>&1 | FileCheck --check-prefixes=CHECK %s 2 3target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" 4 5; REQUIRES: asserts 6 7; Check if the vector loop condition can be simplified to true for a given 8; VF/IC combination. 9define void @test_tc_less_than_16(ptr %A, i64 %N) { 10; CHECK: LV: Scalarizing: %cmp = 11; CHECK: VPlan 'Initial VPlan for VF={8},UF>=1' { 12; CHECK-NEXT: Live-in vp<[[VFxUF:%.+]]> = VF * UF 13; CHECK-NEXT: Live-in vp<[[VTC:%.+]]> = vector-trip-count 14; CHECK-NEXT: vp<[[TC:%.+]]> = original trip-count 15; CHECK-EMPTY: 16; CHECK-NEXT: ir-bb<entry>: 17; CHECK-NEXT: IR %and = and i64 %N, 15 18; CHECK-NEXT: EMIT vp<[[TC]]> = EXPAND SCEV (zext i4 (trunc i64 %N to i4) to i64) 19; CHECK-NEXT: Successor(s): vector.ph 20; CHECK-EMPTY: 21; CHECK-NEXT: vector.ph: 22; CHECK-NEXT: vp<[[END1:%.+]]> = DERIVED-IV ir<%and> + vp<[[VTC]]> * ir<-1> 23; CHECK-NEXT: vp<[[END2:%.+]]> = DERIVED-IV ir<%A> + vp<[[VTC]]> * ir<1> 24; CHECK-NEXT: Successor(s): vector loop 25; CHECK-EMPTY: 26; CHECK-NEXT: <x1> vector loop: { 27; CHECK-NEXT: vector.body: 28; CHECK-NEXT: EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION ir<0>, vp<[[CAN_IV_NEXT:%.+]]> 29; CHECK-NEXT: vp<[[STEPS:%.+]]> = SCALAR-STEPS vp<[[CAN_IV]]>, ir<1> 30; CHECK-NEXT: EMIT vp<[[PADD:%.+]]> = ptradd ir<%A>, vp<[[STEPS]]> 31; CHECK-NEXT: vp<[[VPTR:%.]]> = vector-pointer vp<[[PADD]]> 32; CHECK-NEXT: WIDEN ir<%l> = load vp<[[VPTR]]> 33; CHECK-NEXT: WIDEN ir<%add> = add nsw ir<%l>, ir<10> 34; CHECK-NEXT: vp<[[VPTR2:%.+]]> = vector-pointer vp<[[PADD]]> 35; CHECK-NEXT: WIDEN store vp<[[VPTR2]]>, ir<%add> 36; CHECK-NEXT: EMIT vp<[[CAN_IV_NEXT]]> = add nuw vp<[[CAN_IV:%.+]]>, vp<[[VFxUF]]> 37; CHECK-NEXT: EMIT branch-on-count vp<[[CAN_IV_NEXT]]>, vp<[[VTC]]> 38; CHECK-NEXT: No successors 39; CHECK-NEXT: } 40; CHECK-NEXT: Successor(s): middle.block 41; CHECK-EMPTY: 42; CHECK-NEXT: middle.block: 43; CHECK-NEXT: EMIT vp<[[C:%.+]]> = icmp eq vp<[[TC]]>, vp<[[VTC]]> 44; CHECK-NEXT: EMIT branch-on-cond vp<[[C]]> 45; CHECK-NEXT: Successor(s): ir-bb<exit>, scalar.ph 46; CHECK-EMPTY: 47; CHECK-NEXT: scalar.ph: 48; CHECK-NEXT: EMIT vp<[[RESUME1:%.+]]> = resume-phi vp<[[END1]]>, ir<%and> 49; CHECK-NEXT: EMIT vp<[[RESUME2:%.+]]>.1 = resume-phi vp<[[END2]]>, ir<%A> 50; CHECK-NEXT: Successor(s): ir-bb<loop> 51; CHECK-EMPTY: 52; CHECK-NEXT: ir-bb<loop>: 53; CHECK-NEXT: IR %iv = phi i64 [ %and, %entry ], [ %iv.next, %loop ] (extra operand: vp<[[RESUME1]]> from scalar.ph) 54; CHECK-NEXT: IR %p.src = phi ptr [ %A, %entry ], [ %p.src.next, %loop ] (extra operand: vp<[[RESUME2]]>.1 from scalar.ph) 55; CHECK: IR %cmp = icmp eq i64 %iv.next, 0 56; CHECK-NEXT: No successors 57; CHECK-EMPTY: 58; CHECK-NEXT: ir-bb<exit>: 59; CHECK-NEXT: No successors 60; CHECK-NEXT: } 61; 62; CHECK: Executing best plan with VF=8, UF=2 63; CHECK-NEXT: VPlan 'Final VPlan for VF={8},UF={2}' { 64; CHECK-NEXT: Live-in ir<[[VTC:%.+]]> = vector-trip-count 65; CHECK-NEXT: vp<[[TC:%.+]]> = original trip-count 66; CHECK-EMPTY: 67; CHECK-NEXT: ir-bb<entry>: 68; CHECK-NEXT: IR %and = and i64 %N, 15 69; CHECK-NEXT: EMIT vp<[[TC]]> = EXPAND SCEV (zext i4 (trunc i64 %N to i4) to i64) 70; CHECK-NEXT: Successor(s): ir-bb<scalar.ph>, ir-bb<vector.ph> 71; CHECK-EMPTY: 72; CHECK-NEXT: ir-bb<vector.ph>: 73; CHECK-NEXT: IR %n.mod.vf = urem i64 %and, 16 74; CHECK-NEXT: IR %n.vec = sub i64 %and, %n.mod.vf 75; CHECK-NEXT: vp<[[END1:%.+]]> = DERIVED-IV ir<%and> + ir<[[VTC]]> * ir<-1> 76; CHECK-NEXT: vp<[[END2:%.+]]> = DERIVED-IV ir<%A> + ir<[[VTC]]> * ir<1> 77; CHECK-NEXT: Successor(s): vector.body 78; CHECK-EMPTY: 79; CHECK-NEXT: vector.body: 80; CHECK-NEXT: vp<[[STEPS1:%.+]]> = SCALAR-STEPS ir<0>, ir<1> 81; CHECK-NEXT: EMIT vp<[[PADD1:%.+]]> = ptradd ir<%A>, vp<[[STEPS1]]> 82; CHECK-NEXT: vp<[[VPTR1:%.]]> = vector-pointer vp<[[PADD1]]> 83; CHECK-NEXT: vp<[[VPTR2:%.]]> = vector-pointer vp<[[PADD1]]>, ir<1> 84; CHECK-NEXT: WIDEN ir<%l> = load vp<[[VPTR1]]> 85; CHECK-NEXT: WIDEN ir<%l>.1 = load vp<[[VPTR2]]> 86; CHECK-NEXT: WIDEN ir<%add> = add nsw ir<%l>, ir<10> 87; CHECK-NEXT: WIDEN ir<%add>.1 = add nsw ir<%l>.1, ir<10> 88; CHECK-NEXT: vp<[[VPTR3:%.+]]> = vector-pointer vp<[[PADD1]]> 89; CHECK-NEXT: vp<[[VPTR4:%.+]]> = vector-pointer vp<[[PADD1]]>, ir<1> 90; CHECK-NEXT: WIDEN store vp<[[VPTR3]]>, ir<%add> 91; CHECK-NEXT: WIDEN store vp<[[VPTR4]]>, ir<%add>.1 92; CHECK-NEXT: Successor(s): ir-bb<middle.block> 93; CHECK-EMPTY: 94; CHECK-NEXT: ir-bb<middle.block>: 95; CHECK-NEXT: EMIT vp<[[C:%.+]]> = icmp eq vp<[[TC]]>, ir<[[VTC]]> 96; CHECK-NEXT: EMIT branch-on-cond vp<[[C]]> 97; CHECK-NEXT: Successor(s): ir-bb<exit>, ir-bb<scalar.ph> 98; CHECK-EMPTY: 99; CHECK-NEXT: ir-bb<exit>: 100; CHECK-NEXT: No successors 101; CHECK-EMPTY: 102; CHECK-NEXT: ir-bb<scalar.ph>: 103; CHECK-NEXT: EMIT vp<[[RESUME1:%.+]]> = resume-phi vp<[[END1]]>, ir<%and> 104; CHECK-NEXT: EMIT vp<[[RESUME2:%.+]]>.1 = resume-phi vp<[[END2]]>, ir<%A> 105; CHECK-NEXT: Successor(s): ir-bb<loop> 106; CHECK-EMPTY: 107; CHECK-NEXT: ir-bb<loop>: 108; CHECK-NEXT: IR %iv = phi i64 [ %and, %scalar.ph ], [ %iv.next, %loop ] (extra operand: vp<[[RESUME1]]> from ir-bb<scalar.ph>) 109; CHECK-NEXT: IR %p.src = phi ptr [ %A, %scalar.ph ], [ %p.src.next, %loop ] (extra operand: vp<[[RESUME2]]>.1 from ir-bb<scalar.ph>) 110; CHECK: IR %cmp = icmp eq i64 %iv.next, 0 111; CHECK-NEXT: No successors 112; CHECK-NEXT: } 113; 114entry: 115 %and = and i64 %N, 15 116 br label %loop 117 118loop: 119 %iv = phi i64 [ %and, %entry ], [ %iv.next, %loop ] 120 %p.src = phi ptr [ %A, %entry ], [ %p.src.next, %loop ] 121 %p.src.next = getelementptr inbounds i8, ptr %p.src, i64 1 122 %l = load i8, ptr %p.src, align 1 123 %add = add nsw i8 %l, 10 124 store i8 %add, ptr %p.src 125 %iv.next = add nsw i64 %iv, -1 126 %cmp = icmp eq i64 %iv.next, 0 127 br i1 %cmp, label %exit, label %loop 128 129exit: 130 ret void 131} 132