1; RUN: opt -passes=loop-vectorize -force-vector-width=2 -force-vector-interleave=1 -S < %s | FileCheck %s 2 3; This test is to ensure that SCEV checks (which are costly performancewise) are 4; not generated when appropriate aliasing checks are sufficient. 5 6define void @foo(ptr %pout, ptr %pin, i64 %val0, i64 %val1, i64 %val2) { 7; CHECK-LABEL: @foo( 8; CHECK-NOT: vector.scevcheck 9; CHECK: vector.body 10entry: 11 %0 = getelementptr double, ptr %pin, i64 %val0 12 br label %loop1.header 13 14loop1.header: ; preds = %loop1.latch, %entry 15 %i = phi i64 [ %i.next, %loop1.latch ], [ 0, %entry ] 16 %mul0 = mul nsw i64 %i, %val2 17 %arrayidx0 = getelementptr inbounds double, ptr %0, i64 %mul0 18 %mul1 = mul nsw i64 %i, %val1 19 br label %loop2.header 20 21loop2.header: ; preds = %loop1.header, %loop2.header 22 %j = phi i64 [ 0, %loop1.header ], [ %j.next, %loop2.header ] 23 %1 = load double, ptr %arrayidx0, align 8 24 %arrayidx1 = getelementptr inbounds double, ptr %0, i64 %j 25 %2 = load double, ptr %arrayidx1, align 8 26 %sum = fadd contract double %1, %2 27 %3 = getelementptr double, ptr %pout, i64 %mul1 28 %arrayidx2 = getelementptr inbounds double, ptr %3, i64 %j 29 store double %sum, ptr %arrayidx2, align 8 30 %j.next = add nuw nsw i64 %j, 1 31 %cmp = icmp slt i64 %j.next, %val1 32 br i1 %cmp, label %loop2.header, label %loop1.latch 33 34loop1.latch: ; preds = %loop2.header 35 %i.next = add nuw nsw i64 %i, 1 36 %exitcond = icmp eq i64 %i.next, %val1 37 br i1 %exitcond, label %exit, label %loop1.header 38 39exit: ; preds = %loop1.latch 40 ret void 41} 42 43; Similar test to the above but with the %arrayidx0 moved to the loop2.header 44 45define void @bar(ptr %pout, ptr %pin, i64 %val0, i64 %val1, i64 %val2) { 46; CHECK-LABEL: @bar( 47; CHECK-NOT: vector.scevcheck 48; CHECK: vector.body 49entry: 50 %0 = getelementptr double, ptr %pin, i64 %val0 51 br label %loop1.header 52 53loop1.header: ; preds = %loop1.latch, %entry 54 %i = phi i64 [ %i.next, %loop1.latch ], [ 0, %entry ] 55 %mul0 = mul nsw i64 %i, %val2 56 %mul1 = mul nsw i64 %i, %val1 57 br label %loop2.header 58 59loop2.header: ; preds = %loop1.header, %loop2.header 60 %j = phi i64 [ 0, %loop1.header ], [ %j.next, %loop2.header ] 61 %arrayidx0 = getelementptr inbounds double, ptr %0, i64 %mul0 62 %1 = load double, ptr %arrayidx0, align 8 63 %arrayidx1 = getelementptr inbounds double, ptr %0, i64 %j 64 %2 = load double, ptr %arrayidx1, align 8 65 %sum = fadd contract double %1, %2 66 %3 = getelementptr double, ptr %pout, i64 %mul1 67 %arrayidx2 = getelementptr inbounds double, ptr %3, i64 %j 68 store double %sum, ptr %arrayidx2, align 8 69 %j.next = add nuw nsw i64 %j, 1 70 %cmp = icmp slt i64 %j.next, %val1 71 br i1 %cmp, label %loop2.header, label %loop1.latch 72 73loop1.latch: ; preds = %loop2.header 74 %i.next = add nuw nsw i64 %i, 1 75 %exitcond = icmp eq i64 %i.next, %val1 76 br i1 %exitcond, label %exit, label %loop1.header 77 78exit: ; preds = %loop1.latch 79 ret void 80} 81