1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 2; RUN: opt -p loop-vectorize -force-vector-width=4 -force-vector-interleave=1 -S %s | FileCheck %s 3 4target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" 5 6define i32 @test_icmp_constant_op_zext(ptr %dst) { 7; CHECK-LABEL: define i32 @test_icmp_constant_op_zext( 8; CHECK-SAME: ptr [[DST:%.*]]) { 9; CHECK-NEXT: entry: 10; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] 11; CHECK: vector.ph: 12; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] 13; CHECK: vector.body: 14; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] 15; CHECK-NEXT: [[DOTCAST:%.*]] = trunc i32 [[INDEX]] to i16 16; CHECK-NEXT: [[OFFSET_IDX:%.*]] = add i16 1, [[DOTCAST]] 17; CHECK-NEXT: [[TMP0:%.*]] = add i16 [[OFFSET_IDX]], 0 18; CHECK-NEXT: [[TMP1:%.*]] = getelementptr i8, ptr [[DST]], i16 [[TMP0]] 19; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[TMP1]], i32 0 20; CHECK-NEXT: store <4 x i8> splat (i8 109), ptr [[TMP2]], align 1 21; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4 22; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[INDEX_NEXT]], 996 23; CHECK-NEXT: br i1 [[TMP3]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] 24; CHECK: middle.block: 25; CHECK-NEXT: br i1 false, label [[EXIT:%.*]], label [[SCALAR_PH]] 26; CHECK: scalar.ph: 27; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i16 [ 997, [[MIDDLE_BLOCK]] ], [ 1, [[ENTRY:%.*]] ] 28; CHECK-NEXT: br label [[LOOP:%.*]] 29; CHECK: loop: 30; CHECK-NEXT: [[IV:%.*]] = phi i16 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ] 31; CHECK-NEXT: [[C:%.*]] = icmp ne i64 7304878031173690989, 0 32; CHECK-NEXT: [[C_EXT:%.*]] = zext i1 [[C]] to i64 33; CHECK-NEXT: [[OR:%.*]] = or i64 7304878031173690989, [[C_EXT]] 34; CHECK-NEXT: [[OR_TRUNC:%.*]] = trunc i64 [[OR]] to i8 35; CHECK-NEXT: [[GEP:%.*]] = getelementptr i8, ptr [[DST]], i16 [[IV]] 36; CHECK-NEXT: store i8 [[OR_TRUNC]], ptr [[GEP]], align 1 37; CHECK-NEXT: [[IV_NEXT]] = add i16 [[IV]], 1 38; CHECK-NEXT: [[EC:%.*]] = icmp eq i16 [[IV_NEXT]], 1000 39; CHECK-NEXT: br i1 [[EC]], label [[EXIT]], label [[LOOP]], !llvm.loop [[LOOP3:![0-9]+]] 40; CHECK: exit: 41; CHECK-NEXT: ret i32 0 42; 43entry: 44 br label %loop 45 46loop: 47 %iv = phi i16 [ 1, %entry ], [ %iv.next, %loop ] 48 %c = icmp ne i64 7304878031173690989, 0 49 %c.ext = zext i1 %c to i64 50 %or = or i64 7304878031173690989, %c.ext 51 %or.trunc = trunc i64 %or to i8 52 %gep = getelementptr i8, ptr %dst, i16 %iv 53 store i8 %or.trunc, ptr %gep, align 1 54 %iv.next = add i16 %iv, 1 55 %ec = icmp eq i16 %iv.next, 1000 56 br i1 %ec, label %exit, label %loop 57 58exit: 59 ret i32 0 60} 61 62 63define i32 @test_icmp_and_op_zext(ptr %dst, i64 %a) { 64; CHECK-LABEL: define i32 @test_icmp_and_op_zext( 65; CHECK-SAME: ptr [[DST:%.*]], i64 [[A:%.*]]) { 66; CHECK-NEXT: entry: 67; CHECK-NEXT: [[AND:%.*]] = and i64 [[A]], 7304878031173690989 68; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] 69; CHECK: vector.ph: 70; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i64> poison, i64 [[AND]], i64 0 71; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i64> [[BROADCAST_SPLATINSERT]], <4 x i64> poison, <4 x i32> zeroinitializer 72; CHECK-NEXT: [[TMP1:%.*]] = icmp ne <4 x i64> [[BROADCAST_SPLAT]], zeroinitializer 73; CHECK-NEXT: [[TMP2:%.*]] = zext <4 x i1> [[TMP1]] to <4 x i64> 74; CHECK-NEXT: [[TMP3:%.*]] = or <4 x i64> [[BROADCAST_SPLAT]], [[TMP2]] 75; CHECK-NEXT: [[TMP4:%.*]] = trunc <4 x i64> [[TMP3]] to <4 x i8> 76; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] 77; CHECK: vector.body: 78; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] 79; CHECK-NEXT: [[DOTCAST:%.*]] = trunc i32 [[INDEX]] to i16 80; CHECK-NEXT: [[OFFSET_IDX:%.*]] = add i16 1, [[DOTCAST]] 81; CHECK-NEXT: [[TMP0:%.*]] = add i16 [[OFFSET_IDX]], 0 82; CHECK-NEXT: [[TMP5:%.*]] = getelementptr i8, ptr [[DST]], i16 [[TMP0]] 83; CHECK-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr [[TMP5]], i32 0 84; CHECK-NEXT: store <4 x i8> [[TMP4]], ptr [[TMP6]], align 1 85; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4 86; CHECK-NEXT: [[TMP7:%.*]] = icmp eq i32 [[INDEX_NEXT]], 996 87; CHECK-NEXT: br i1 [[TMP7]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]] 88; CHECK: middle.block: 89; CHECK-NEXT: br i1 false, label [[EXIT:%.*]], label [[SCALAR_PH]] 90; CHECK: scalar.ph: 91; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i16 [ 997, [[MIDDLE_BLOCK]] ], [ 1, [[ENTRY:%.*]] ] 92; CHECK-NEXT: br label [[LOOP:%.*]] 93; CHECK: loop: 94; CHECK-NEXT: [[IV:%.*]] = phi i16 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ] 95; CHECK-NEXT: [[C:%.*]] = icmp ne i64 [[AND]], 0 96; CHECK-NEXT: [[C_EXT:%.*]] = zext i1 [[C]] to i64 97; CHECK-NEXT: [[OR:%.*]] = or i64 [[AND]], [[C_EXT]] 98; CHECK-NEXT: [[OR_TRUNC:%.*]] = trunc i64 [[OR]] to i8 99; CHECK-NEXT: [[GEP:%.*]] = getelementptr i8, ptr [[DST]], i16 [[IV]] 100; CHECK-NEXT: store i8 [[OR_TRUNC]], ptr [[GEP]], align 1 101; CHECK-NEXT: [[IV_NEXT]] = add i16 [[IV]], 1 102; CHECK-NEXT: [[EC:%.*]] = icmp eq i16 [[IV_NEXT]], 1000 103; CHECK-NEXT: br i1 [[EC]], label [[EXIT]], label [[LOOP]], !llvm.loop [[LOOP5:![0-9]+]] 104; CHECK: exit: 105; CHECK-NEXT: ret i32 0 106; 107entry: 108 %and = and i64 %a, 7304878031173690989 109 br label %loop 110 111loop: 112 %iv = phi i16 [ 1, %entry ], [ %iv.next, %loop ] 113 %c = icmp ne i64 %and, 0 114 %c.ext = zext i1 %c to i64 115 %or = or i64 %and, %c.ext 116 %or.trunc = trunc i64 %or to i8 117 %gep = getelementptr i8, ptr %dst, i16 %iv 118 store i8 %or.trunc, ptr %gep, align 1 119 %iv.next = add i16 %iv, 1 120 %ec = icmp eq i16 %iv.next, 1000 121 br i1 %ec, label %exit, label %loop 122 123exit: 124 ret i32 0 125} 126 127define void @ext_cmp(ptr %src.1, ptr %src.2, ptr noalias %dst) { 128; CHECK-LABEL: define void @ext_cmp( 129; CHECK-SAME: ptr [[SRC_1:%.*]], ptr [[SRC_2:%.*]], ptr noalias [[DST:%.*]]) { 130; CHECK-NEXT: entry: 131; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] 132; CHECK: vector.ph: 133; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] 134; CHECK: vector.body: 135; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] 136; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 0 137; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i16, ptr [[SRC_1]], i64 [[TMP0]] 138; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds i16, ptr [[TMP1]], i32 0 139; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i16>, ptr [[TMP2]], align 2 140; CHECK-NEXT: [[TMP3:%.*]] = icmp sgt <4 x i16> zeroinitializer, [[WIDE_LOAD]] 141; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds i8, ptr [[SRC_2]], i64 [[TMP0]] 142; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds i8, ptr [[TMP4]], i32 0 143; CHECK-NEXT: [[WIDE_LOAD1:%.*]] = load <4 x i8>, ptr [[TMP5]], align 2 144; CHECK-NEXT: [[TMP6:%.*]] = zext <4 x i8> [[WIDE_LOAD1]] to <4 x i16> 145; CHECK-NEXT: [[TMP7:%.*]] = select <4 x i1> [[TMP3]], <4 x i16> zeroinitializer, <4 x i16> [[TMP6]] 146; CHECK-NEXT: [[TMP8:%.*]] = and <4 x i16> [[TMP7]], zeroinitializer 147; CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds i16, ptr [[DST]], i64 [[TMP0]] 148; CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds i16, ptr [[TMP9]], i32 0 149; CHECK-NEXT: store <4 x i16> [[TMP8]], ptr [[TMP10]], align 2 150; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 151; CHECK-NEXT: [[TMP11:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1000 152; CHECK-NEXT: br i1 [[TMP11]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]] 153; CHECK: middle.block: 154; CHECK-NEXT: br i1 true, label [[EXIT:%.*]], label [[SCALAR_PH]] 155; CHECK: scalar.ph: 156; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ 1000, [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ] 157; CHECK-NEXT: br label [[LOOP:%.*]] 158; CHECK: loop: 159; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ] 160; CHECK-NEXT: [[GEP_SRC_1:%.*]] = getelementptr inbounds i16, ptr [[SRC_1]], i64 [[IV]] 161; CHECK-NEXT: [[I2:%.*]] = load i16, ptr [[GEP_SRC_1]], align 2 162; CHECK-NEXT: [[I3:%.*]] = sext i16 [[I2]] to i32 163; CHECK-NEXT: [[C_1:%.*]] = icmp sgt i32 0, [[I3]] 164; CHECK-NEXT: [[GEP_SRC_2:%.*]] = getelementptr inbounds i8, ptr [[SRC_2]], i64 [[IV]] 165; CHECK-NEXT: [[I4:%.*]] = load i8, ptr [[GEP_SRC_2]], align 2 166; CHECK-NEXT: [[I5:%.*]] = zext i8 [[I4]] to i32 167; CHECK-NEXT: [[I6:%.*]] = select i1 [[C_1]], i32 0, i32 [[I5]] 168; CHECK-NEXT: [[I7:%.*]] = and i32 [[I6]], 0 169; CHECK-NEXT: [[I8:%.*]] = trunc nuw nsw i32 [[I7]] to i16 170; CHECK-NEXT: [[GEP_DST:%.*]] = getelementptr inbounds i16, ptr [[DST]], i64 [[IV]] 171; CHECK-NEXT: store i16 [[I8]], ptr [[GEP_DST]], align 2 172; CHECK-NEXT: [[IV_NEXT]] = add nsw i64 [[IV]], 1 173; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], 1000 174; CHECK-NEXT: br i1 [[EC]], label [[EXIT]], label [[LOOP]], !llvm.loop [[LOOP7:![0-9]+]] 175; CHECK: exit: 176; CHECK-NEXT: ret void 177; 178entry: 179 br label %loop 180 181loop: 182 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] 183 %gep.src.1 = getelementptr inbounds i16, ptr %src.1, i64 %iv 184 %i2 = load i16, ptr %gep.src.1, align 2 185 %i3 = sext i16 %i2 to i32 186 %c.1 = icmp sgt i32 0, %i3 187 %gep.src.2 = getelementptr inbounds i8, ptr %src.2, i64 %iv 188 %i4 = load i8, ptr %gep.src.2, align 2 189 %i5 = zext i8 %i4 to i32 190 %i6 = select i1 %c.1, i32 0, i32 %i5 191 %i7 = and i32 %i6, 0 192 %i8 = trunc nuw nsw i32 %i7 to i16 193 %gep.dst = getelementptr inbounds i16, ptr %dst, i64 %iv 194 store i16 %i8, ptr %gep.dst, align 2 195 %iv.next = add nsw i64 %iv, 1 196 %ec = icmp eq i64 %iv.next, 1000 197 br i1 %ec, label %exit, label %loop 198 199exit: 200 ret void 201} 202;. 203; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]} 204; CHECK: [[META1]] = !{!"llvm.loop.isvectorized", i32 1} 205; CHECK: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"} 206; CHECK: [[LOOP3]] = distinct !{[[LOOP3]], [[META2]], [[META1]]} 207; CHECK: [[LOOP4]] = distinct !{[[LOOP4]], [[META1]], [[META2]]} 208; CHECK: [[LOOP5]] = distinct !{[[LOOP5]], [[META2]], [[META1]]} 209; CHECK: [[LOOP6]] = distinct !{[[LOOP6]], [[META1]], [[META2]]} 210; CHECK: [[LOOP7]] = distinct !{[[LOOP7]], [[META2]], [[META1]]} 211;. 212