1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 3 2; RUN: opt -passes=loop-vectorize -prefer-predicate-over-epilogue=predicate-else-scalar-epilogue -force-vector-interleave=2 -force-vector-width=1 -force-ordered-reductions -S %s | FileCheck %s 3; RUN: opt -passes=loop-vectorize -prefer-predicate-over-epilogue=predicate-else-scalar-epilogue -force-vector-interleave=2 -force-vector-width=1 -force-ordered-reductions -force-tail-folding-style=data -S %s | FileCheck --check-prefix=CHECK-ALM %s 4 5define float @pr70988() { 6; CHECK-LABEL: define float @pr70988() { 7; CHECK-NEXT: entry: 8; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] 9; CHECK: vector.ph: 10; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] 11; CHECK: vector.body: 12; CHECK-NEXT: [[INDEX1:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT3:%.*]], [[VECTOR_BODY]] ] 13; CHECK-NEXT: [[VEC_PHI:%.*]] = phi float [ 0.000000e+00, [[VECTOR_PH]] ], [ [[TMP5:%.*]], [[VECTOR_BODY]] ] 14; CHECK-NEXT: [[VEC_IV:%.*]] = add i32 [[INDEX1]], 0 15; CHECK-NEXT: [[VEC_IV2:%.*]] = add i32 [[INDEX1]], 1 16; CHECK-NEXT: [[TMP0:%.*]] = icmp ule i32 [[VEC_IV]], 1020 17; CHECK-NEXT: [[TMP1:%.*]] = icmp ule i32 [[VEC_IV2]], 1020 18; CHECK-NEXT: [[TMP2:%.*]] = select contract i1 [[TMP0]], float 1.000000e+00, float -0.000000e+00 19; CHECK-NEXT: [[TMP3:%.*]] = fadd contract float [[VEC_PHI]], [[TMP2]] 20; CHECK-NEXT: [[TMP4:%.*]] = select contract i1 [[TMP1]], float 1.000000e+00, float -0.000000e+00 21; CHECK-NEXT: [[TMP5]] = fadd contract float [[TMP3]], [[TMP4]] 22; CHECK-NEXT: [[INDEX_NEXT3]] = add nuw i32 [[INDEX1]], 2 23; CHECK-NEXT: [[TMP6:%.*]] = icmp eq i32 [[INDEX_NEXT3]], 1022 24; CHECK-NEXT: br i1 [[TMP6]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] 25; CHECK: middle.block: 26; CHECK-NEXT: br i1 true, label [[EXIT:%.*]], label [[SCALAR_PH]] 27; CHECK: scalar.ph: 28; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ 1022, [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ] 29; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi float [ [[TMP5]], [[MIDDLE_BLOCK]] ], [ 0.000000e+00, [[ENTRY]] ] 30; CHECK-NEXT: br label [[LOOP:%.*]] 31; CHECK: loop: 32; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[INDEX_NEXT:%.*]], [[LOOP]] ] 33; CHECK-NEXT: [[RDX:%.*]] = phi float [ [[BC_MERGE_RDX]], [[SCALAR_PH]] ], [ [[RDX_NEXT:%.*]], [[LOOP]] ] 34; CHECK-NEXT: [[RDX_NEXT]] = fadd contract float [[RDX]], 1.000000e+00 35; CHECK-NEXT: [[INDEX_NEXT]] = add nuw nsw i32 [[INDEX]], 1 36; CHECK-NEXT: [[COND:%.*]] = icmp ult i32 [[INDEX_NEXT]], 1021 37; CHECK-NEXT: br i1 [[COND]], label [[LOOP]], label [[EXIT]], !llvm.loop [[LOOP3:![0-9]+]] 38; CHECK: exit: 39; CHECK-NEXT: [[DOTLCSSA:%.*]] = phi float [ [[RDX_NEXT]], [[LOOP]] ], [ [[TMP5]], [[MIDDLE_BLOCK]] ] 40; CHECK-NEXT: ret float [[DOTLCSSA]] 41; 42; CHECK-ALM-LABEL: define float @pr70988() { 43; CHECK-ALM-NEXT: entry: 44; CHECK-ALM-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] 45; CHECK-ALM: vector.ph: 46; CHECK-ALM-NEXT: br label [[VECTOR_BODY:%.*]] 47; CHECK-ALM: vector.body: 48; CHECK-ALM-NEXT: [[INDEX1:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT3:%.*]], [[VECTOR_BODY]] ] 49; CHECK-ALM-NEXT: [[VEC_PHI:%.*]] = phi float [ 0.000000e+00, [[VECTOR_PH]] ], [ [[TMP5:%.*]], [[VECTOR_BODY]] ] 50; CHECK-ALM-NEXT: [[TMP0:%.*]] = add i32 [[INDEX1]], 0 51; CHECK-ALM-NEXT: [[TMP1:%.*]] = add i32 [[INDEX1]], 1 52; CHECK-ALM-NEXT: [[ACTIVE_LANE_MASK:%.*]] = icmp ult i32 [[TMP0]], 1021 53; CHECK-ALM-NEXT: [[ACTIVE_LANE_MASK2:%.*]] = icmp ult i32 [[TMP1]], 1021 54; CHECK-ALM-NEXT: [[TMP2:%.*]] = select contract i1 [[ACTIVE_LANE_MASK]], float 1.000000e+00, float -0.000000e+00 55; CHECK-ALM-NEXT: [[TMP3:%.*]] = fadd contract float [[VEC_PHI]], [[TMP2]] 56; CHECK-ALM-NEXT: [[TMP4:%.*]] = select contract i1 [[ACTIVE_LANE_MASK2]], float 1.000000e+00, float -0.000000e+00 57; CHECK-ALM-NEXT: [[TMP5]] = fadd contract float [[TMP3]], [[TMP4]] 58; CHECK-ALM-NEXT: [[INDEX_NEXT3]] = add nuw i32 [[INDEX1]], 2 59; CHECK-ALM-NEXT: [[TMP6:%.*]] = icmp eq i32 [[INDEX_NEXT3]], 1022 60; CHECK-ALM-NEXT: br i1 [[TMP6]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] 61; CHECK-ALM: middle.block: 62; CHECK-ALM-NEXT: br i1 true, label [[EXIT:%.*]], label [[SCALAR_PH]] 63; CHECK-ALM: scalar.ph: 64; CHECK-ALM-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ 1022, [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ] 65; CHECK-ALM-NEXT: [[BC_MERGE_RDX:%.*]] = phi float [ [[TMP5]], [[MIDDLE_BLOCK]] ], [ 0.000000e+00, [[ENTRY]] ] 66; CHECK-ALM-NEXT: br label [[LOOP:%.*]] 67; CHECK-ALM: loop: 68; CHECK-ALM-NEXT: [[INDEX:%.*]] = phi i32 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[INDEX_NEXT:%.*]], [[LOOP]] ] 69; CHECK-ALM-NEXT: [[RDX:%.*]] = phi float [ [[BC_MERGE_RDX]], [[SCALAR_PH]] ], [ [[RDX_NEXT:%.*]], [[LOOP]] ] 70; CHECK-ALM-NEXT: [[RDX_NEXT]] = fadd contract float [[RDX]], 1.000000e+00 71; CHECK-ALM-NEXT: [[INDEX_NEXT]] = add nuw nsw i32 [[INDEX]], 1 72; CHECK-ALM-NEXT: [[COND:%.*]] = icmp ult i32 [[INDEX_NEXT]], 1021 73; CHECK-ALM-NEXT: br i1 [[COND]], label [[LOOP]], label [[EXIT]], !llvm.loop [[LOOP3:![0-9]+]] 74; CHECK-ALM: exit: 75; CHECK-ALM-NEXT: [[DOTLCSSA:%.*]] = phi float [ [[RDX_NEXT]], [[LOOP]] ], [ [[TMP5]], [[MIDDLE_BLOCK]] ] 76; CHECK-ALM-NEXT: ret float [[DOTLCSSA]] 77; 78entry: 79 br label %loop 80 81loop: 82 %index = phi i32 [ 0, %entry ], [ %index.next, %loop ] 83 %rdx = phi float [ 0.000000e+00, %entry ], [ %rdx.next, %loop ] 84 %rdx.next = fadd contract float %rdx, 1.000000e+00 85 %index.next = add nuw nsw i32 %index, 1 86 %cond = icmp ult i32 %index.next, 1021 87 br i1 %cond, label %loop, label %exit 88 89exit: 90 %.lcssa = phi float [ %rdx.next, %loop ] 91 ret float %.lcssa 92} 93 94define float @pr72720reduction_using_active_lane_mask(ptr %src) { 95; CHECK-LABEL: define float @pr72720reduction_using_active_lane_mask( 96; CHECK-SAME: ptr [[SRC:%.*]]) { 97; CHECK-NEXT: entry: 98; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] 99; CHECK: vector.ph: 100; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] 101; CHECK: vector.body: 102; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[PRED_LOAD_CONTINUE3:%.*]] ] 103; CHECK-NEXT: [[VEC_PHI:%.*]] = phi float [ 0.000000e+00, [[VECTOR_PH]] ], [ [[TMP13:%.*]], [[PRED_LOAD_CONTINUE3]] ] 104; CHECK-NEXT: [[VEC_IV:%.*]] = add i32 [[INDEX]], 0 105; CHECK-NEXT: [[VEC_IV1:%.*]] = add i32 [[INDEX]], 1 106; CHECK-NEXT: [[TMP0:%.*]] = icmp ule i32 [[VEC_IV]], 14 107; CHECK-NEXT: [[TMP1:%.*]] = icmp ule i32 [[VEC_IV1]], 14 108; CHECK-NEXT: br i1 [[TMP0]], label [[PRED_LOAD_IF:%.*]], label [[PRED_LOAD_CONTINUE:%.*]] 109; CHECK: pred.load.if: 110; CHECK-NEXT: [[TMP2:%.*]] = add i32 [[INDEX]], 0 111; CHECK-NEXT: [[TMP3:%.*]] = getelementptr float, ptr [[SRC]], i32 [[TMP2]] 112; CHECK-NEXT: [[TMP4:%.*]] = load float, ptr [[TMP3]], align 4 113; CHECK-NEXT: br label [[PRED_LOAD_CONTINUE]] 114; CHECK: pred.load.continue: 115; CHECK-NEXT: [[TMP5:%.*]] = phi float [ poison, [[VECTOR_BODY]] ], [ [[TMP4]], [[PRED_LOAD_IF]] ] 116; CHECK-NEXT: br i1 [[TMP1]], label [[PRED_LOAD_IF2:%.*]], label [[PRED_LOAD_CONTINUE3]] 117; CHECK: pred.load.if2: 118; CHECK-NEXT: [[TMP6:%.*]] = add i32 [[INDEX]], 1 119; CHECK-NEXT: [[TMP7:%.*]] = getelementptr float, ptr [[SRC]], i32 [[TMP6]] 120; CHECK-NEXT: [[TMP8:%.*]] = load float, ptr [[TMP7]], align 4 121; CHECK-NEXT: br label [[PRED_LOAD_CONTINUE3]] 122; CHECK: pred.load.continue3: 123; CHECK-NEXT: [[TMP9:%.*]] = phi float [ poison, [[PRED_LOAD_CONTINUE]] ], [ [[TMP8]], [[PRED_LOAD_IF2]] ] 124; CHECK-NEXT: [[TMP10:%.*]] = select contract i1 [[TMP0]], float [[TMP5]], float -0.000000e+00 125; CHECK-NEXT: [[TMP11:%.*]] = fadd contract float [[VEC_PHI]], [[TMP10]] 126; CHECK-NEXT: [[TMP12:%.*]] = select contract i1 [[TMP1]], float [[TMP9]], float -0.000000e+00 127; CHECK-NEXT: [[TMP13]] = fadd contract float [[TMP11]], [[TMP12]] 128; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 2 129; CHECK-NEXT: [[TMP14:%.*]] = icmp eq i32 [[INDEX_NEXT]], 16 130; CHECK-NEXT: br i1 [[TMP14]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]] 131; CHECK: middle.block: 132; CHECK-NEXT: br i1 true, label [[EXIT:%.*]], label [[SCALAR_PH]] 133; CHECK: scalar.ph: 134; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ 16, [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ] 135; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi float [ [[TMP13]], [[MIDDLE_BLOCK]] ], [ 0.000000e+00, [[ENTRY]] ] 136; CHECK-NEXT: br label [[LOOP:%.*]] 137; CHECK: loop: 138; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[NARROW:%.*]], [[LOOP]] ] 139; CHECK-NEXT: [[RDX:%.*]] = phi float [ [[BC_MERGE_RDX]], [[SCALAR_PH]] ], [ [[RDX_NEXT:%.*]], [[LOOP]] ] 140; CHECK-NEXT: [[NARROW]] = add nuw nsw i32 [[IV]], 1 141; CHECK-NEXT: [[GEP:%.*]] = getelementptr float, ptr [[SRC]], i32 [[IV]] 142; CHECK-NEXT: [[L:%.*]] = load float, ptr [[GEP]], align 4 143; CHECK-NEXT: [[RDX_NEXT]] = fadd contract float [[RDX]], [[L]] 144; CHECK-NEXT: [[EC:%.*]] = icmp ult i32 [[NARROW]], 15 145; CHECK-NEXT: br i1 [[EC]], label [[LOOP]], label [[EXIT]], !llvm.loop [[LOOP5:![0-9]+]] 146; CHECK: exit: 147; CHECK-NEXT: [[DOTLCSSA:%.*]] = phi float [ [[RDX_NEXT]], [[LOOP]] ], [ [[TMP13]], [[MIDDLE_BLOCK]] ] 148; CHECK-NEXT: ret float [[DOTLCSSA]] 149; 150; CHECK-ALM-LABEL: define float @pr72720reduction_using_active_lane_mask( 151; CHECK-ALM-SAME: ptr [[SRC:%.*]]) { 152; CHECK-ALM-NEXT: entry: 153; CHECK-ALM-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] 154; CHECK-ALM: vector.ph: 155; CHECK-ALM-NEXT: br label [[VECTOR_BODY:%.*]] 156; CHECK-ALM: vector.body: 157; CHECK-ALM-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[PRED_LOAD_CONTINUE3:%.*]] ] 158; CHECK-ALM-NEXT: [[VEC_PHI:%.*]] = phi float [ 0.000000e+00, [[VECTOR_PH]] ], [ [[TMP11:%.*]], [[PRED_LOAD_CONTINUE3]] ] 159; CHECK-ALM-NEXT: [[TMP0:%.*]] = add i32 [[INDEX]], 0 160; CHECK-ALM-NEXT: [[TMP1:%.*]] = add i32 [[INDEX]], 1 161; CHECK-ALM-NEXT: [[ACTIVE_LANE_MASK:%.*]] = icmp ult i32 [[TMP0]], 15 162; CHECK-ALM-NEXT: [[ACTIVE_LANE_MASK1:%.*]] = icmp ult i32 [[TMP1]], 15 163; CHECK-ALM-NEXT: br i1 [[ACTIVE_LANE_MASK]], label [[PRED_LOAD_IF:%.*]], label [[PRED_LOAD_CONTINUE:%.*]] 164; CHECK-ALM: pred.load.if: 165; CHECK-ALM-NEXT: [[TMP2:%.*]] = getelementptr float, ptr [[SRC]], i32 [[TMP0]] 166; CHECK-ALM-NEXT: [[TMP3:%.*]] = load float, ptr [[TMP2]], align 4 167; CHECK-ALM-NEXT: br label [[PRED_LOAD_CONTINUE]] 168; CHECK-ALM: pred.load.continue: 169; CHECK-ALM-NEXT: [[TMP4:%.*]] = phi float [ poison, [[VECTOR_BODY]] ], [ [[TMP3]], [[PRED_LOAD_IF]] ] 170; CHECK-ALM-NEXT: br i1 [[ACTIVE_LANE_MASK1]], label [[PRED_LOAD_IF2:%.*]], label [[PRED_LOAD_CONTINUE3]] 171; CHECK-ALM: pred.load.if2: 172; CHECK-ALM-NEXT: [[TMP5:%.*]] = getelementptr float, ptr [[SRC]], i32 [[TMP1]] 173; CHECK-ALM-NEXT: [[TMP6:%.*]] = load float, ptr [[TMP5]], align 4 174; CHECK-ALM-NEXT: br label [[PRED_LOAD_CONTINUE3]] 175; CHECK-ALM: pred.load.continue3: 176; CHECK-ALM-NEXT: [[TMP7:%.*]] = phi float [ poison, [[PRED_LOAD_CONTINUE]] ], [ [[TMP6]], [[PRED_LOAD_IF2]] ] 177; CHECK-ALM-NEXT: [[TMP8:%.*]] = select contract i1 [[ACTIVE_LANE_MASK]], float [[TMP4]], float -0.000000e+00 178; CHECK-ALM-NEXT: [[TMP9:%.*]] = fadd contract float [[VEC_PHI]], [[TMP8]] 179; CHECK-ALM-NEXT: [[TMP10:%.*]] = select contract i1 [[ACTIVE_LANE_MASK1]], float [[TMP7]], float -0.000000e+00 180; CHECK-ALM-NEXT: [[TMP11]] = fadd contract float [[TMP9]], [[TMP10]] 181; CHECK-ALM-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 2 182; CHECK-ALM-NEXT: [[TMP12:%.*]] = icmp eq i32 [[INDEX_NEXT]], 16 183; CHECK-ALM-NEXT: br i1 [[TMP12]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]] 184; CHECK-ALM: middle.block: 185; CHECK-ALM-NEXT: br i1 true, label [[EXIT:%.*]], label [[SCALAR_PH]] 186; CHECK-ALM: scalar.ph: 187; CHECK-ALM-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ 16, [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ] 188; CHECK-ALM-NEXT: [[BC_MERGE_RDX:%.*]] = phi float [ [[TMP11]], [[MIDDLE_BLOCK]] ], [ 0.000000e+00, [[ENTRY]] ] 189; CHECK-ALM-NEXT: br label [[LOOP:%.*]] 190; CHECK-ALM: loop: 191; CHECK-ALM-NEXT: [[IV:%.*]] = phi i32 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[NARROW:%.*]], [[LOOP]] ] 192; CHECK-ALM-NEXT: [[RDX:%.*]] = phi float [ [[BC_MERGE_RDX]], [[SCALAR_PH]] ], [ [[RDX_NEXT:%.*]], [[LOOP]] ] 193; CHECK-ALM-NEXT: [[NARROW]] = add nuw nsw i32 [[IV]], 1 194; CHECK-ALM-NEXT: [[GEP:%.*]] = getelementptr float, ptr [[SRC]], i32 [[IV]] 195; CHECK-ALM-NEXT: [[L:%.*]] = load float, ptr [[GEP]], align 4 196; CHECK-ALM-NEXT: [[RDX_NEXT]] = fadd contract float [[RDX]], [[L]] 197; CHECK-ALM-NEXT: [[EC:%.*]] = icmp ult i32 [[NARROW]], 15 198; CHECK-ALM-NEXT: br i1 [[EC]], label [[LOOP]], label [[EXIT]], !llvm.loop [[LOOP5:![0-9]+]] 199; CHECK-ALM: exit: 200; CHECK-ALM-NEXT: [[DOTLCSSA:%.*]] = phi float [ [[RDX_NEXT]], [[LOOP]] ], [ [[TMP11]], [[MIDDLE_BLOCK]] ] 201; CHECK-ALM-NEXT: ret float [[DOTLCSSA]] 202; 203entry: 204 br label %loop 205 206loop: 207 %iv = phi i32 [ 0, %entry ], [ %narrow, %loop ] 208 %rdx = phi float [ 0.0, %entry ], [ %rdx.next, %loop ] 209 %narrow = add nuw nsw i32 %iv, 1 210 %gep = getelementptr float, ptr %src, i32 %iv 211 %l = load float, ptr %gep, align 4 212 %rdx.next = fadd contract float %rdx, %l 213 %ec = icmp ult i32 %narrow, 15 214 br i1 %ec, label %loop, label %exit 215 216exit: 217 %.lcssa = phi float [ %rdx.next, %loop ] 218 ret float %.lcssa 219} 220