1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 2; RUN: opt -passes=loop-vectorize -force-vector-width=2 -force-vector-interleave=1 -S %s | FileCheck %s 3 4; Make sure LV does not crash when creating runtime checks involving values from 5; other loops. 6define i16 @test(ptr %arg, i64 %N) { 7; CHECK-LABEL: @test( 8; CHECK-NEXT: entry: 9; CHECK-NEXT: br label [[OUTER:%.*]] 10; CHECK: outer: 11; CHECK-NEXT: [[L_1:%.*]] = load ptr, ptr [[ARG:%.*]], align 8 12; CHECK-NEXT: [[L_2:%.*]] = load ptr, ptr [[ARG]], align 8 13; CHECK-NEXT: [[C_1:%.*]] = call i1 @cond() 14; CHECK-NEXT: br i1 [[C_1]], label [[OUTER_BACKEDGE:%.*]], label [[INNER_PREHEADER:%.*]] 15; CHECK: outer.backedge: 16; CHECK-NEXT: br label [[OUTER]] 17; CHECK: inner.preheader: 18; CHECK-NEXT: br label [[INNER:%.*]] 19; CHECK: inner: 20; CHECK-NEXT: [[C_2:%.*]] = call i1 @cond() 21; CHECK-NEXT: br i1 [[C_2]], label [[OUTER_LATCH:%.*]], label [[INNER_BB:%.*]] 22; CHECK: inner.bb: 23; CHECK-NEXT: [[C_3:%.*]] = call i1 @cond() 24; CHECK-NEXT: br i1 [[C_3]], label [[LOOP_3_PREHEADER:%.*]], label [[INNER_LATCH:%.*]] 25; CHECK: loop.3.preheader: 26; CHECK-NEXT: [[L_1_LCSSA:%.*]] = phi ptr [ [[L_1]], [[INNER_BB]] ] 27; CHECK-NEXT: [[L_2_LCSSA:%.*]] = phi ptr [ [[L_2]], [[INNER_BB]] ] 28; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[N:%.*]], 1 29; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP0]], 2 30; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_MEMCHECK:%.*]] 31; CHECK: vector.memcheck: 32; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[L_2_LCSSA]], i64 2 33; CHECK-NEXT: [[SCEVGEP5:%.*]] = getelementptr i8, ptr [[L_1_LCSSA]], i64 2 34; CHECK-NEXT: [[TMP1:%.*]] = shl i64 [[N]], 1 35; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[TMP1]], 4 36; CHECK-NEXT: [[SCEVGEP6:%.*]] = getelementptr i8, ptr [[L_1_LCSSA]], i64 [[TMP2]] 37; CHECK-NEXT: [[BOUND0:%.*]] = icmp ult ptr [[L_2_LCSSA]], [[SCEVGEP6]] 38; CHECK-NEXT: [[BOUND1:%.*]] = icmp ult ptr [[SCEVGEP5]], [[SCEVGEP]] 39; CHECK-NEXT: [[FOUND_CONFLICT:%.*]] = and i1 [[BOUND0]], [[BOUND1]] 40; CHECK-NEXT: br i1 [[FOUND_CONFLICT]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]] 41; CHECK: vector.ph: 42; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP0]], 2 43; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP0]], [[N_MOD_VF]] 44; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds i16, ptr [[L_2]], i64 0 45; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] 46; CHECK: vector.body: 47; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] 48; CHECK-NEXT: [[TMP3:%.*]] = add i64 [[INDEX]], 0 49; CHECK-NEXT: [[TMP4:%.*]] = add nuw nsw i64 [[TMP3]], 1 50; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds i16, ptr [[L_1]], i64 [[TMP4]] 51; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds i16, ptr [[TMP5]], i32 0 52; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <2 x i16>, ptr [[TMP6]], align 2, !alias.scope [[META0:![0-9]+]] 53; CHECK-NEXT: [[TMP8:%.*]] = extractelement <2 x i16> [[WIDE_LOAD]], i32 1 54; CHECK-NEXT: store i16 [[TMP8]], ptr [[TMP7]], align 2, !alias.scope [[META3:![0-9]+]], !noalias [[META0]] 55; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2 56; CHECK-NEXT: [[TMP9:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] 57; CHECK-NEXT: br i1 [[TMP9]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]] 58; CHECK: middle.block: 59; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP0]], [[N_VEC]] 60; CHECK-NEXT: br i1 [[CMP_N]], label [[EXIT_LOOPEXIT:%.*]], label [[SCALAR_PH]] 61; CHECK: scalar.ph: 62; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], [[MIDDLE_BLOCK]] ], [ 0, [[VECTOR_MEMCHECK]] ], [ 0, [[LOOP_3_PREHEADER]] ] 63; CHECK-NEXT: br label [[LOOP_3:%.*]] 64; CHECK: inner.latch: 65; CHECK-NEXT: [[C_4:%.*]] = call i1 @cond() 66; CHECK-NEXT: br i1 [[C_4]], label [[EXIT_LOOPEXIT1:%.*]], label [[INNER]] 67; CHECK: outer.latch: 68; CHECK-NEXT: br label [[OUTER_BACKEDGE]] 69; CHECK: loop.3: 70; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[IV_NEXT:%.*]], [[LOOP_3]] ], [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ] 71; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1 72; CHECK-NEXT: [[C_5:%.*]] = icmp ult i64 [[IV]], [[N]] 73; CHECK-NEXT: [[GEP_1:%.*]] = getelementptr inbounds i16, ptr [[L_1_LCSSA]], i64 [[IV_NEXT]] 74; CHECK-NEXT: [[LOOP_L_1:%.*]] = load i16, ptr [[GEP_1]], align 2 75; CHECK-NEXT: [[GEP_2:%.*]] = getelementptr inbounds i16, ptr [[L_2_LCSSA]], i64 0 76; CHECK-NEXT: store i16 [[LOOP_L_1]], ptr [[GEP_2]], align 2 77; CHECK-NEXT: br i1 [[C_5]], label [[LOOP_3]], label [[EXIT_LOOPEXIT]], !llvm.loop [[LOOP8:![0-9]+]] 78; CHECK: exit.loopexit: 79; CHECK-NEXT: br label [[EXIT:%.*]] 80; CHECK: exit.loopexit1: 81; CHECK-NEXT: [[L_1_LCSSA3:%.*]] = phi ptr [ [[L_1]], [[INNER_LATCH]] ] 82; CHECK-NEXT: br label [[EXIT]] 83; CHECK: exit: 84; CHECK-NEXT: [[L_14:%.*]] = phi ptr [ [[L_1_LCSSA3]], [[EXIT_LOOPEXIT1]] ], [ [[L_1_LCSSA]], [[EXIT_LOOPEXIT]] ] 85; CHECK-NEXT: [[L_3:%.*]] = load i16, ptr [[L_14]], align 2 86; CHECK-NEXT: ret i16 [[L_3]] 87; 88entry: 89 br label %outer 90 91outer: 92 %l.1 = load ptr, ptr %arg, align 8 93 %l.2 = load ptr, ptr %arg, align 8 94 %c.1 = call i1 @cond() 95 br i1 %c.1, label %outer, label %inner 96 97inner: 98 %c.2 = call i1 @cond() 99 br i1 %c.2, label %outer.latch, label %inner.bb 100 101inner.bb: 102 %c.3 = call i1 @cond() 103 br i1 %c.3, label %loop.3, label %inner.latch 104 105inner.latch: 106 %c.4 = call i1 @cond() 107 br i1 %c.4, label %exit, label %inner 108 109outer.latch: 110 br label %outer 111 112loop.3: 113 %iv = phi i64 [ %iv.next, %loop.3 ], [ 0, %inner.bb ] 114 %iv.next = add nsw nuw i64 %iv, 1 115 %c.5 = icmp ult i64 %iv, %N 116 %gep.1 = getelementptr inbounds i16, ptr %l.1, i64 %iv.next 117 %loop.l.1 = load i16, ptr %gep.1, align 2 118 %gep.2 = getelementptr inbounds i16, ptr %l.2, i64 0 119 store i16 %loop.l.1, ptr %gep.2 , align 2 120 br i1 %c.5, label %loop.3, label %exit 121 122exit: 123 %l.3 = load i16, ptr %l.1, align 2 124 ret i16 %l.3 125} 126 127define void @test2(ptr %dst) { 128; CHECK-LABEL: @test2( 129; CHECK-NEXT: entry: 130; CHECK-NEXT: br label [[LOOP_1_HEADER:%.*]] 131; CHECK: loop.1.header: 132; CHECK-NEXT: br label [[LOOP_2:%.*]] 133; CHECK: loop.2: 134; CHECK-NEXT: [[INDVAR:%.*]] = phi i32 [ [[INDVAR_NEXT:%.*]], [[LOOP_2]] ], [ 0, [[LOOP_1_HEADER]] ] 135; CHECK-NEXT: [[IV_1:%.*]] = phi i64 [ 1000, [[LOOP_1_HEADER]] ], [ [[IV_1_NEXT:%.*]], [[LOOP_2]] ] 136; CHECK-NEXT: [[IV_1_NEXT]] = add i64 [[IV_1]], -1 137; CHECK-NEXT: [[C_1:%.*]] = call i1 @cond() 138; CHECK-NEXT: [[INDVAR_NEXT]] = add i32 [[INDVAR]], 1 139; CHECK-NEXT: br i1 [[C_1]], label [[LOOP_2]], label [[LOOP_3_PH:%.*]] 140; CHECK: loop.3.ph: 141; CHECK-NEXT: [[INDVAR_LCSSA:%.*]] = phi i32 [ [[INDVAR]], [[LOOP_2]] ] 142; CHECK-NEXT: [[IV_1_LCSSA:%.*]] = phi i64 [ [[IV_1]], [[LOOP_2]] ] 143; CHECK-NEXT: [[TMP0:%.*]] = and i64 [[IV_1_LCSSA]], 4294967295 144; CHECK-NEXT: [[TMP1:%.*]] = mul i32 [[INDVAR_LCSSA]], -1 145; CHECK-NEXT: [[TMP2:%.*]] = add i32 [[TMP1]], 1000 146; CHECK-NEXT: [[SMIN:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP2]], i32 1) 147; CHECK-NEXT: [[TMP3:%.*]] = sub i32 [[TMP2]], [[SMIN]] 148; CHECK-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64 149; CHECK-NEXT: [[TMP5:%.*]] = add nuw nsw i64 [[TMP4]], 1 150; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP5]], 2 151; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] 152; CHECK: vector.ph: 153; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP5]], 2 154; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP5]], [[N_MOD_VF]] 155; CHECK-NEXT: [[IND_END:%.*]] = sub i64 [[TMP0]], [[N_VEC]] 156; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] 157; CHECK: vector.body: 158; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] 159; CHECK-NEXT: [[OFFSET_IDX:%.*]] = sub i64 [[TMP0]], [[INDEX]] 160; CHECK-NEXT: [[TMP6:%.*]] = add i64 [[OFFSET_IDX]], 0 161; CHECK-NEXT: [[TMP7:%.*]] = add nsw i64 [[TMP6]], -1 162; CHECK-NEXT: [[TMP8:%.*]] = and i64 [[TMP7]], 4294967295 163; CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds i32, ptr [[DST:%.*]], i64 [[TMP8]] 164; CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds i32, ptr [[TMP9]], i32 0 165; CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds i32, ptr [[TMP10]], i32 -1 166; CHECK-NEXT: store <2 x i32> zeroinitializer, ptr [[TMP11]], align 4 167; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2 168; CHECK-NEXT: [[TMP12:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] 169; CHECK-NEXT: br i1 [[TMP12]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP9:![0-9]+]] 170; CHECK: middle.block: 171; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP5]], [[N_VEC]] 172; CHECK-NEXT: br i1 [[CMP_N]], label [[LOOP_1_LATCH:%.*]], label [[SCALAR_PH]] 173; CHECK: scalar.ph: 174; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[IND_END]], [[MIDDLE_BLOCK]] ], [ [[TMP0]], [[LOOP_3_PH]] ] 175; CHECK-NEXT: br label [[LOOP_3:%.*]] 176; CHECK: loop.3: 177; CHECK-NEXT: [[IV_2:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_2_NEXT:%.*]], [[LOOP_3]] ] 178; CHECK-NEXT: [[IV_2_NEXT]] = add nsw i64 [[IV_2]], -1 179; CHECK-NEXT: [[AND_IV:%.*]] = and i64 [[IV_2_NEXT]], 4294967295 180; CHECK-NEXT: [[GEP_DST:%.*]] = getelementptr inbounds i32, ptr [[DST]], i64 [[AND_IV]] 181; CHECK-NEXT: store i32 0, ptr [[GEP_DST]], align 4 182; CHECK-NEXT: [[IV_2_TRUNC:%.*]] = trunc i64 [[IV_2]] to i32 183; CHECK-NEXT: [[EC:%.*]] = icmp sgt i32 [[IV_2_TRUNC]], 1 184; CHECK-NEXT: br i1 [[EC]], label [[LOOP_3]], label [[LOOP_1_LATCH]], !llvm.loop [[LOOP10:![0-9]+]] 185; CHECK: loop.1.latch: 186; CHECK-NEXT: [[C_2:%.*]] = call i1 @cond() 187; CHECK-NEXT: br i1 [[C_2]], label [[EXIT:%.*]], label [[LOOP_1_HEADER]] 188; CHECK: exit: 189; CHECK-NEXT: ret void 190; 191entry: 192 br label %loop.1.header 193 194loop.1.header: 195 br label %loop.2 196 197loop.2: 198 %iv.1 = phi i64 [ 1000, %loop.1.header ], [ %iv.1.next, %loop.2 ] 199 %iv.1.next = add i64 %iv.1, -1 200 %c.1 = call i1 @cond() 201 br i1 %c.1, label %loop.2, label %loop.3.ph 202 203loop.3.ph: 204 %iv.1.lcssa = phi i64 [ %iv.1, %loop.2 ] 205 %0 = and i64 %iv.1.lcssa, 4294967295 206 br label %loop.3 207 208loop.3: 209 %iv.2 = phi i64 [ %0, %loop.3.ph ], [ %iv.2.next, %loop.3 ] 210 %iv.2.next = add nsw i64 %iv.2, -1 211 %and.iv = and i64 %iv.2.next, 4294967295 212 %gep.dst = getelementptr inbounds i32, ptr %dst, i64 %and.iv 213 store i32 0, ptr %gep.dst, align 4 214 %iv.2.trunc = trunc i64 %iv.2 to i32 215 %ec = icmp sgt i32 %iv.2.trunc, 1 216 br i1 %ec, label %loop.3, label %loop.1.latch 217 218loop.1.latch: 219 %c.2 = call i1 @cond() 220 br i1 %c.2, label %exit, label %loop.1.header 221 222exit: 223 ret void 224} 225 226declare i1 @cond() 227