xref: /llvm-project/llvm/test/Transforms/LoopVectorize/predicate-switch.ll (revision 38fffa630ee80163dc65e759392ad29798905679) 
1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
2; RUN: opt -p loop-vectorize -force-vector-width=2 -force-vector-interleave=1 -S %s | FileCheck --check-prefixes=IC1 %s
3; RUN: opt -p loop-vectorize -force-vector-width=2 -force-vector-interleave=2 -S %s | FileCheck --check-prefixes=IC2 %s
4
5define void @switch4_default_common_dest_with_case(ptr %start, ptr %end) {
6; IC1-LABEL: define void @switch4_default_common_dest_with_case(
7; IC1-SAME: ptr [[START:%.*]], ptr [[END:%.*]]) {
8; IC1-NEXT:  [[ENTRY:.*]]:
9; IC1-NEXT:    [[START2:%.*]] = ptrtoint ptr [[START]] to i64
10; IC1-NEXT:    [[END1:%.*]] = ptrtoint ptr [[END]] to i64
11; IC1-NEXT:    [[TMP0:%.*]] = sub i64 [[END1]], [[START2]]
12; IC1-NEXT:    [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP0]], 2
13; IC1-NEXT:    br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
14; IC1:       [[VECTOR_PH]]:
15; IC1-NEXT:    [[N_MOD_VF:%.*]] = urem i64 [[TMP0]], 2
16; IC1-NEXT:    [[N_VEC:%.*]] = sub i64 [[TMP0]], [[N_MOD_VF]]
17; IC1-NEXT:    [[IND_END:%.*]] = getelementptr i8, ptr [[START]], i64 [[N_VEC]]
18; IC1-NEXT:    br label %[[VECTOR_BODY:.*]]
19; IC1:       [[VECTOR_BODY]]:
20; IC1-NEXT:    [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[PRED_STORE_CONTINUE13:.*]] ]
21; IC1-NEXT:    [[TMP1:%.*]] = add i64 [[INDEX]], 0
22; IC1-NEXT:    [[TMP2:%.*]] = add i64 [[INDEX]], 1
23; IC1-NEXT:    [[NEXT_GEP:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP1]]
24; IC1-NEXT:    [[NEXT_GEP3:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP2]]
25; IC1-NEXT:    [[TMP3:%.*]] = getelementptr i8, ptr [[NEXT_GEP]], i32 0
26; IC1-NEXT:    [[WIDE_LOAD:%.*]] = load <2 x i8>, ptr [[TMP3]], align 1
27; IC1-NEXT:    [[TMP7:%.*]] = icmp eq <2 x i8> [[WIDE_LOAD]], splat (i8 -12)
28; IC1-NEXT:    [[TMP4:%.*]] = icmp eq <2 x i8> [[WIDE_LOAD]], splat (i8 13)
29; IC1-NEXT:    [[TMP11:%.*]] = or <2 x i1> [[TMP7]], [[TMP4]]
30; IC1-NEXT:    [[TMP10:%.*]] = xor <2 x i1> [[TMP11]], splat (i1 true)
31; IC1-NEXT:    [[TMP5:%.*]] = extractelement <2 x i1> [[TMP4]], i32 0
32; IC1-NEXT:    br i1 [[TMP5]], label %[[PRED_STORE_IF:.*]], label %[[PRED_STORE_CONTINUE:.*]]
33; IC1:       [[PRED_STORE_IF]]:
34; IC1-NEXT:    store i8 0, ptr [[NEXT_GEP]], align 1
35; IC1-NEXT:    br label %[[PRED_STORE_CONTINUE]]
36; IC1:       [[PRED_STORE_CONTINUE]]:
37; IC1-NEXT:    [[TMP6:%.*]] = extractelement <2 x i1> [[TMP4]], i32 1
38; IC1-NEXT:    br i1 [[TMP6]], label %[[PRED_STORE_IF4:.*]], label %[[PRED_STORE_CONTINUE5:.*]]
39; IC1:       [[PRED_STORE_IF4]]:
40; IC1-NEXT:    store i8 0, ptr [[NEXT_GEP3]], align 1
41; IC1-NEXT:    br label %[[PRED_STORE_CONTINUE5]]
42; IC1:       [[PRED_STORE_CONTINUE5]]:
43; IC1-NEXT:    [[TMP8:%.*]] = extractelement <2 x i1> [[TMP7]], i32 0
44; IC1-NEXT:    br i1 [[TMP8]], label %[[PRED_STORE_IF6:.*]], label %[[PRED_STORE_CONTINUE7:.*]]
45; IC1:       [[PRED_STORE_IF6]]:
46; IC1-NEXT:    store i8 42, ptr [[NEXT_GEP]], align 1
47; IC1-NEXT:    br label %[[PRED_STORE_CONTINUE7]]
48; IC1:       [[PRED_STORE_CONTINUE7]]:
49; IC1-NEXT:    [[TMP9:%.*]] = extractelement <2 x i1> [[TMP7]], i32 1
50; IC1-NEXT:    br i1 [[TMP9]], label %[[PRED_STORE_IF8:.*]], label %[[PRED_STORE_CONTINUE9:.*]]
51; IC1:       [[PRED_STORE_IF8]]:
52; IC1-NEXT:    store i8 42, ptr [[NEXT_GEP3]], align 1
53; IC1-NEXT:    br label %[[PRED_STORE_CONTINUE9]]
54; IC1:       [[PRED_STORE_CONTINUE9]]:
55; IC1-NEXT:    [[TMP13:%.*]] = extractelement <2 x i1> [[TMP10]], i32 0
56; IC1-NEXT:    br i1 [[TMP13]], label %[[PRED_STORE_IF10:.*]], label %[[PRED_STORE_CONTINUE11:.*]]
57; IC1:       [[PRED_STORE_IF10]]:
58; IC1-NEXT:    store i8 2, ptr [[NEXT_GEP]], align 1
59; IC1-NEXT:    br label %[[PRED_STORE_CONTINUE11]]
60; IC1:       [[PRED_STORE_CONTINUE11]]:
61; IC1-NEXT:    [[TMP14:%.*]] = extractelement <2 x i1> [[TMP10]], i32 1
62; IC1-NEXT:    br i1 [[TMP14]], label %[[PRED_STORE_IF12:.*]], label %[[PRED_STORE_CONTINUE13]]
63; IC1:       [[PRED_STORE_IF12]]:
64; IC1-NEXT:    store i8 2, ptr [[NEXT_GEP3]], align 1
65; IC1-NEXT:    br label %[[PRED_STORE_CONTINUE13]]
66; IC1:       [[PRED_STORE_CONTINUE13]]:
67; IC1-NEXT:    [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2
68; IC1-NEXT:    [[TMP15:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
69; IC1-NEXT:    br i1 [[TMP15]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
70; IC1:       [[MIDDLE_BLOCK]]:
71; IC1-NEXT:    [[CMP_N:%.*]] = icmp eq i64 [[TMP0]], [[N_VEC]]
72; IC1-NEXT:    br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
73; IC1:       [[SCALAR_PH]]:
74; IC1-NEXT:    [[BC_RESUME_VAL:%.*]] = phi ptr [ [[IND_END]], %[[MIDDLE_BLOCK]] ], [ [[START]], %[[ENTRY]] ]
75; IC1-NEXT:    br label %[[LOOP_HEADER:.*]]
76; IC1:       [[LOOP_HEADER]]:
77; IC1-NEXT:    [[PTR_IV:%.*]] = phi ptr [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[PTR_IV_NEXT:%.*]], %[[LOOP_LATCH:.*]] ]
78; IC1-NEXT:    [[L:%.*]] = load i8, ptr [[PTR_IV]], align 1
79; IC1-NEXT:    switch i8 [[L]], label %[[DEFAULT:.*]] [
80; IC1-NEXT:      i8 -12, label %[[IF_THEN_1:.*]]
81; IC1-NEXT:      i8 13, label %[[IF_THEN_2:.*]]
82; IC1-NEXT:      i8 0, label %[[DEFAULT]]
83; IC1-NEXT:    ]
84; IC1:       [[IF_THEN_1]]:
85; IC1-NEXT:    store i8 42, ptr [[PTR_IV]], align 1
86; IC1-NEXT:    br label %[[LOOP_LATCH]]
87; IC1:       [[IF_THEN_2]]:
88; IC1-NEXT:    store i8 0, ptr [[PTR_IV]], align 1
89; IC1-NEXT:    br label %[[LOOP_LATCH]]
90; IC1:       [[DEFAULT]]:
91; IC1-NEXT:    store i8 2, ptr [[PTR_IV]], align 1
92; IC1-NEXT:    br label %[[LOOP_LATCH]]
93; IC1:       [[LOOP_LATCH]]:
94; IC1-NEXT:    [[PTR_IV_NEXT]] = getelementptr inbounds i8, ptr [[PTR_IV]], i64 1
95; IC1-NEXT:    [[EC:%.*]] = icmp eq ptr [[PTR_IV_NEXT]], [[END]]
96; IC1-NEXT:    br i1 [[EC]], label %[[EXIT]], label %[[LOOP_HEADER]], !llvm.loop [[LOOP3:![0-9]+]]
97; IC1:       [[EXIT]]:
98; IC1-NEXT:    ret void
99;
100; IC2-LABEL: define void @switch4_default_common_dest_with_case(
101; IC2-SAME: ptr [[START:%.*]], ptr [[END:%.*]]) {
102; IC2-NEXT:  [[ENTRY:.*]]:
103; IC2-NEXT:    [[START2:%.*]] = ptrtoint ptr [[START]] to i64
104; IC2-NEXT:    [[END1:%.*]] = ptrtoint ptr [[END]] to i64
105; IC2-NEXT:    [[TMP0:%.*]] = sub i64 [[END1]], [[START2]]
106; IC2-NEXT:    [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP0]], 4
107; IC2-NEXT:    br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
108; IC2:       [[VECTOR_PH]]:
109; IC2-NEXT:    [[N_MOD_VF:%.*]] = urem i64 [[TMP0]], 4
110; IC2-NEXT:    [[N_VEC:%.*]] = sub i64 [[TMP0]], [[N_MOD_VF]]
111; IC2-NEXT:    [[IND_END:%.*]] = getelementptr i8, ptr [[START]], i64 [[N_VEC]]
112; IC2-NEXT:    br label %[[VECTOR_BODY:.*]]
113; IC2:       [[VECTOR_BODY]]:
114; IC2-NEXT:    [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[PRED_STORE_CONTINUE28:.*]] ]
115; IC2-NEXT:    [[TMP1:%.*]] = add i64 [[INDEX]], 0
116; IC2-NEXT:    [[TMP2:%.*]] = add i64 [[INDEX]], 1
117; IC2-NEXT:    [[TMP3:%.*]] = add i64 [[INDEX]], 2
118; IC2-NEXT:    [[TMP4:%.*]] = add i64 [[INDEX]], 3
119; IC2-NEXT:    [[NEXT_GEP:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP1]]
120; IC2-NEXT:    [[NEXT_GEP3:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP2]]
121; IC2-NEXT:    [[NEXT_GEP4:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP3]]
122; IC2-NEXT:    [[NEXT_GEP5:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP4]]
123; IC2-NEXT:    [[TMP5:%.*]] = getelementptr i8, ptr [[NEXT_GEP]], i32 0
124; IC2-NEXT:    [[TMP6:%.*]] = getelementptr i8, ptr [[NEXT_GEP]], i32 2
125; IC2-NEXT:    [[WIDE_LOAD:%.*]] = load <2 x i8>, ptr [[TMP5]], align 1
126; IC2-NEXT:    [[WIDE_LOAD6:%.*]] = load <2 x i8>, ptr [[TMP6]], align 1
127; IC2-NEXT:    [[TMP13:%.*]] = icmp eq <2 x i8> [[WIDE_LOAD]], splat (i8 -12)
128; IC2-NEXT:    [[TMP14:%.*]] = icmp eq <2 x i8> [[WIDE_LOAD6]], splat (i8 -12)
129; IC2-NEXT:    [[TMP7:%.*]] = icmp eq <2 x i8> [[WIDE_LOAD]], splat (i8 13)
130; IC2-NEXT:    [[TMP8:%.*]] = icmp eq <2 x i8> [[WIDE_LOAD6]], splat (i8 13)
131; IC2-NEXT:    [[TMP21:%.*]] = or <2 x i1> [[TMP13]], [[TMP7]]
132; IC2-NEXT:    [[TMP22:%.*]] = or <2 x i1> [[TMP14]], [[TMP8]]
133; IC2-NEXT:    [[TMP19:%.*]] = xor <2 x i1> [[TMP21]], splat (i1 true)
134; IC2-NEXT:    [[TMP20:%.*]] = xor <2 x i1> [[TMP22]], splat (i1 true)
135; IC2-NEXT:    [[TMP9:%.*]] = extractelement <2 x i1> [[TMP7]], i32 0
136; IC2-NEXT:    br i1 [[TMP9]], label %[[PRED_STORE_IF:.*]], label %[[PRED_STORE_CONTINUE:.*]]
137; IC2:       [[PRED_STORE_IF]]:
138; IC2-NEXT:    store i8 0, ptr [[NEXT_GEP]], align 1
139; IC2-NEXT:    br label %[[PRED_STORE_CONTINUE]]
140; IC2:       [[PRED_STORE_CONTINUE]]:
141; IC2-NEXT:    [[TMP10:%.*]] = extractelement <2 x i1> [[TMP7]], i32 1
142; IC2-NEXT:    br i1 [[TMP10]], label %[[PRED_STORE_IF7:.*]], label %[[PRED_STORE_CONTINUE8:.*]]
143; IC2:       [[PRED_STORE_IF7]]:
144; IC2-NEXT:    store i8 0, ptr [[NEXT_GEP3]], align 1
145; IC2-NEXT:    br label %[[PRED_STORE_CONTINUE8]]
146; IC2:       [[PRED_STORE_CONTINUE8]]:
147; IC2-NEXT:    [[TMP11:%.*]] = extractelement <2 x i1> [[TMP8]], i32 0
148; IC2-NEXT:    br i1 [[TMP11]], label %[[PRED_STORE_IF9:.*]], label %[[PRED_STORE_CONTINUE10:.*]]
149; IC2:       [[PRED_STORE_IF9]]:
150; IC2-NEXT:    store i8 0, ptr [[NEXT_GEP4]], align 1
151; IC2-NEXT:    br label %[[PRED_STORE_CONTINUE10]]
152; IC2:       [[PRED_STORE_CONTINUE10]]:
153; IC2-NEXT:    [[TMP12:%.*]] = extractelement <2 x i1> [[TMP8]], i32 1
154; IC2-NEXT:    br i1 [[TMP12]], label %[[PRED_STORE_IF11:.*]], label %[[PRED_STORE_CONTINUE12:.*]]
155; IC2:       [[PRED_STORE_IF11]]:
156; IC2-NEXT:    store i8 0, ptr [[NEXT_GEP5]], align 1
157; IC2-NEXT:    br label %[[PRED_STORE_CONTINUE12]]
158; IC2:       [[PRED_STORE_CONTINUE12]]:
159; IC2-NEXT:    [[TMP15:%.*]] = extractelement <2 x i1> [[TMP13]], i32 0
160; IC2-NEXT:    br i1 [[TMP15]], label %[[PRED_STORE_IF13:.*]], label %[[PRED_STORE_CONTINUE14:.*]]
161; IC2:       [[PRED_STORE_IF13]]:
162; IC2-NEXT:    store i8 42, ptr [[NEXT_GEP]], align 1
163; IC2-NEXT:    br label %[[PRED_STORE_CONTINUE14]]
164; IC2:       [[PRED_STORE_CONTINUE14]]:
165; IC2-NEXT:    [[TMP16:%.*]] = extractelement <2 x i1> [[TMP13]], i32 1
166; IC2-NEXT:    br i1 [[TMP16]], label %[[PRED_STORE_IF15:.*]], label %[[PRED_STORE_CONTINUE16:.*]]
167; IC2:       [[PRED_STORE_IF15]]:
168; IC2-NEXT:    store i8 42, ptr [[NEXT_GEP3]], align 1
169; IC2-NEXT:    br label %[[PRED_STORE_CONTINUE16]]
170; IC2:       [[PRED_STORE_CONTINUE16]]:
171; IC2-NEXT:    [[TMP17:%.*]] = extractelement <2 x i1> [[TMP14]], i32 0
172; IC2-NEXT:    br i1 [[TMP17]], label %[[PRED_STORE_IF17:.*]], label %[[PRED_STORE_CONTINUE18:.*]]
173; IC2:       [[PRED_STORE_IF17]]:
174; IC2-NEXT:    store i8 42, ptr [[NEXT_GEP4]], align 1
175; IC2-NEXT:    br label %[[PRED_STORE_CONTINUE18]]
176; IC2:       [[PRED_STORE_CONTINUE18]]:
177; IC2-NEXT:    [[TMP18:%.*]] = extractelement <2 x i1> [[TMP14]], i32 1
178; IC2-NEXT:    br i1 [[TMP18]], label %[[PRED_STORE_IF19:.*]], label %[[PRED_STORE_CONTINUE20:.*]]
179; IC2:       [[PRED_STORE_IF19]]:
180; IC2-NEXT:    store i8 42, ptr [[NEXT_GEP5]], align 1
181; IC2-NEXT:    br label %[[PRED_STORE_CONTINUE20]]
182; IC2:       [[PRED_STORE_CONTINUE20]]:
183; IC2-NEXT:    [[TMP25:%.*]] = extractelement <2 x i1> [[TMP19]], i32 0
184; IC2-NEXT:    br i1 [[TMP25]], label %[[PRED_STORE_IF21:.*]], label %[[PRED_STORE_CONTINUE22:.*]]
185; IC2:       [[PRED_STORE_IF21]]:
186; IC2-NEXT:    store i8 2, ptr [[NEXT_GEP]], align 1
187; IC2-NEXT:    br label %[[PRED_STORE_CONTINUE22]]
188; IC2:       [[PRED_STORE_CONTINUE22]]:
189; IC2-NEXT:    [[TMP26:%.*]] = extractelement <2 x i1> [[TMP19]], i32 1
190; IC2-NEXT:    br i1 [[TMP26]], label %[[PRED_STORE_IF23:.*]], label %[[PRED_STORE_CONTINUE24:.*]]
191; IC2:       [[PRED_STORE_IF23]]:
192; IC2-NEXT:    store i8 2, ptr [[NEXT_GEP3]], align 1
193; IC2-NEXT:    br label %[[PRED_STORE_CONTINUE24]]
194; IC2:       [[PRED_STORE_CONTINUE24]]:
195; IC2-NEXT:    [[TMP27:%.*]] = extractelement <2 x i1> [[TMP20]], i32 0
196; IC2-NEXT:    br i1 [[TMP27]], label %[[PRED_STORE_IF25:.*]], label %[[PRED_STORE_CONTINUE26:.*]]
197; IC2:       [[PRED_STORE_IF25]]:
198; IC2-NEXT:    store i8 2, ptr [[NEXT_GEP4]], align 1
199; IC2-NEXT:    br label %[[PRED_STORE_CONTINUE26]]
200; IC2:       [[PRED_STORE_CONTINUE26]]:
201; IC2-NEXT:    [[TMP28:%.*]] = extractelement <2 x i1> [[TMP20]], i32 1
202; IC2-NEXT:    br i1 [[TMP28]], label %[[PRED_STORE_IF27:.*]], label %[[PRED_STORE_CONTINUE28]]
203; IC2:       [[PRED_STORE_IF27]]:
204; IC2-NEXT:    store i8 2, ptr [[NEXT_GEP5]], align 1
205; IC2-NEXT:    br label %[[PRED_STORE_CONTINUE28]]
206; IC2:       [[PRED_STORE_CONTINUE28]]:
207; IC2-NEXT:    [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
208; IC2-NEXT:    [[TMP29:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
209; IC2-NEXT:    br i1 [[TMP29]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
210; IC2:       [[MIDDLE_BLOCK]]:
211; IC2-NEXT:    [[CMP_N:%.*]] = icmp eq i64 [[TMP0]], [[N_VEC]]
212; IC2-NEXT:    br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
213; IC2:       [[SCALAR_PH]]:
214; IC2-NEXT:    [[BC_RESUME_VAL:%.*]] = phi ptr [ [[IND_END]], %[[MIDDLE_BLOCK]] ], [ [[START]], %[[ENTRY]] ]
215; IC2-NEXT:    br label %[[LOOP_HEADER:.*]]
216; IC2:       [[LOOP_HEADER]]:
217; IC2-NEXT:    [[PTR_IV:%.*]] = phi ptr [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[PTR_IV_NEXT:%.*]], %[[LOOP_LATCH:.*]] ]
218; IC2-NEXT:    [[L:%.*]] = load i8, ptr [[PTR_IV]], align 1
219; IC2-NEXT:    switch i8 [[L]], label %[[DEFAULT:.*]] [
220; IC2-NEXT:      i8 -12, label %[[IF_THEN_1:.*]]
221; IC2-NEXT:      i8 13, label %[[IF_THEN_2:.*]]
222; IC2-NEXT:      i8 0, label %[[DEFAULT]]
223; IC2-NEXT:    ]
224; IC2:       [[IF_THEN_1]]:
225; IC2-NEXT:    store i8 42, ptr [[PTR_IV]], align 1
226; IC2-NEXT:    br label %[[LOOP_LATCH]]
227; IC2:       [[IF_THEN_2]]:
228; IC2-NEXT:    store i8 0, ptr [[PTR_IV]], align 1
229; IC2-NEXT:    br label %[[LOOP_LATCH]]
230; IC2:       [[DEFAULT]]:
231; IC2-NEXT:    store i8 2, ptr [[PTR_IV]], align 1
232; IC2-NEXT:    br label %[[LOOP_LATCH]]
233; IC2:       [[LOOP_LATCH]]:
234; IC2-NEXT:    [[PTR_IV_NEXT]] = getelementptr inbounds i8, ptr [[PTR_IV]], i64 1
235; IC2-NEXT:    [[EC:%.*]] = icmp eq ptr [[PTR_IV_NEXT]], [[END]]
236; IC2-NEXT:    br i1 [[EC]], label %[[EXIT]], label %[[LOOP_HEADER]], !llvm.loop [[LOOP3:![0-9]+]]
237; IC2:       [[EXIT]]:
238; IC2-NEXT:    ret void
239;
240entry:
241  br label %loop.header
242
243loop.header:
244  %ptr.iv = phi ptr [ %start, %entry ], [ %ptr.iv.next, %loop.latch ]
245  %l = load i8, ptr %ptr.iv, align 1
246  switch i8 %l, label %default [
247  i8 -12, label %if.then.1
248  i8 13, label %if.then.2
249  i8 0, label %default
250  ]
251
252if.then.1:
253  store i8 42, ptr %ptr.iv, align 1
254  br label %loop.latch
255
256if.then.2:
257  store i8 0, ptr %ptr.iv, align 1
258  br label %loop.latch
259
260default:
261  store i8 2, ptr %ptr.iv, align 1
262  br label %loop.latch
263
264loop.latch:
265  %ptr.iv.next = getelementptr inbounds i8, ptr %ptr.iv, i64 1
266  %ec = icmp eq ptr %ptr.iv.next, %end
267  br i1 %ec, label %exit, label %loop.header
268
269exit:
270  ret void
271}
272
273define void @switch_exiting(ptr %start) {
274; IC1-LABEL: define void @switch_exiting(
275; IC1-SAME: ptr [[START:%.*]]) {
276; IC1-NEXT:  [[ENTRY:.*]]:
277; IC1-NEXT:    br label %[[LOOP_HEADER:.*]]
278; IC1:       [[LOOP_HEADER]]:
279; IC1-NEXT:    [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP_LATCH:.*]] ]
280; IC1-NEXT:    switch i64 [[IV]], label %[[LOOP_LATCH]] [
281; IC1-NEXT:      i64 -12, label %[[IF_THEN:.*]]
282; IC1-NEXT:      i64 100, label %[[EXIT:.*]]
283; IC1-NEXT:    ]
284; IC1:       [[IF_THEN]]:
285; IC1-NEXT:    [[GEP:%.*]] = getelementptr inbounds i64, ptr [[START]], i64 [[IV]]
286; IC1-NEXT:    store i64 42, ptr [[GEP]], align 1
287; IC1-NEXT:    br label %[[LOOP_LATCH]]
288; IC1:       [[LOOP_LATCH]]:
289; IC1-NEXT:    [[IV_NEXT]] = add i64 [[IV]], 1
290; IC1-NEXT:    br label %[[LOOP_HEADER]]
291; IC1:       [[EXIT]]:
292; IC1-NEXT:    ret void
293;
294; IC2-LABEL: define void @switch_exiting(
295; IC2-SAME: ptr [[START:%.*]]) {
296; IC2-NEXT:  [[ENTRY:.*]]:
297; IC2-NEXT:    br label %[[LOOP_HEADER:.*]]
298; IC2:       [[LOOP_HEADER]]:
299; IC2-NEXT:    [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP_LATCH:.*]] ]
300; IC2-NEXT:    switch i64 [[IV]], label %[[LOOP_LATCH]] [
301; IC2-NEXT:      i64 -12, label %[[IF_THEN:.*]]
302; IC2-NEXT:      i64 100, label %[[EXIT:.*]]
303; IC2-NEXT:    ]
304; IC2:       [[IF_THEN]]:
305; IC2-NEXT:    [[GEP:%.*]] = getelementptr inbounds i64, ptr [[START]], i64 [[IV]]
306; IC2-NEXT:    store i64 42, ptr [[GEP]], align 1
307; IC2-NEXT:    br label %[[LOOP_LATCH]]
308; IC2:       [[LOOP_LATCH]]:
309; IC2-NEXT:    [[IV_NEXT]] = add i64 [[IV]], 1
310; IC2-NEXT:    br label %[[LOOP_HEADER]]
311; IC2:       [[EXIT]]:
312; IC2-NEXT:    ret void
313;
314entry:
315  br label %loop.header
316
317loop.header:
318  %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop.latch ]
319  switch i64 %iv, label %loop.latch [
320  i64 -12, label %if.then
321  i64 100, label %exit
322  ]
323
324if.then:
325  %gep = getelementptr inbounds i64, ptr %start, i64 %iv
326  store i64 42, ptr %gep, align 1
327  br label %loop.latch
328
329loop.latch:
330  %iv.next = add i64 %iv, 1
331  br label %loop.header
332
333exit:
334  ret void
335}
336
337define void @switch_to_header(ptr %start) {
338; IC1-LABEL: define void @switch_to_header(
339; IC1-SAME: ptr [[START:%.*]]) {
340; IC1-NEXT:  [[ENTRY:.*]]:
341; IC1-NEXT:    br label %[[LOOP_HEADER:.*]]
342; IC1:       [[LOOP_HEADER]]:
343; IC1-NEXT:    [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[IF_THEN1:.*]] ]
344; IC1-NEXT:    [[IV_NEXT]] = add i64 [[IV]], 1
345; IC1-NEXT:    switch i64 [[IV]], label %[[LOOP_LATCH:.*]] [
346; IC1-NEXT:      i64 120, label %[[IF_THEN1]]
347; IC1-NEXT:      i64 100, label %[[LOOP_LATCH]]
348; IC1-NEXT:    ]
349; IC1:       [[IF_THEN1]]:
350; IC1-NEXT:    br label %[[LOOP_HEADER]]
351; IC1:       [[IF_THEN:.*:]]
352; IC1-NEXT:    [[GEP:%.*]] = getelementptr inbounds i64, ptr [[START]], i64 poison
353; IC1-NEXT:    store i64 42, ptr [[GEP]], align 1
354; IC1-NEXT:    unreachable
355; IC1:       [[LOOP_LATCH]]:
356; IC1-NEXT:    [[CMP:%.*]] = icmp eq i64 [[IV_NEXT]], 100
357; IC1-NEXT:    br i1 [[CMP]], label %[[EXIT:.*]], label %[[IF_THEN1]]
358; IC1:       [[EXIT]]:
359; IC1-NEXT:    ret void
360;
361; IC2-LABEL: define void @switch_to_header(
362; IC2-SAME: ptr [[START:%.*]]) {
363; IC2-NEXT:  [[ENTRY:.*]]:
364; IC2-NEXT:    br label %[[LOOP_HEADER:.*]]
365; IC2:       [[LOOP_HEADER]]:
366; IC2-NEXT:    [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[IF_THEN1:.*]] ]
367; IC2-NEXT:    [[IV_NEXT]] = add i64 [[IV]], 1
368; IC2-NEXT:    switch i64 [[IV]], label %[[LOOP_LATCH:.*]] [
369; IC2-NEXT:      i64 120, label %[[IF_THEN1]]
370; IC2-NEXT:      i64 100, label %[[LOOP_LATCH]]
371; IC2-NEXT:    ]
372; IC2:       [[IF_THEN1]]:
373; IC2-NEXT:    br label %[[LOOP_HEADER]]
374; IC2:       [[IF_THEN:.*:]]
375; IC2-NEXT:    [[GEP:%.*]] = getelementptr inbounds i64, ptr [[START]], i64 poison
376; IC2-NEXT:    store i64 42, ptr [[GEP]], align 1
377; IC2-NEXT:    unreachable
378; IC2:       [[LOOP_LATCH]]:
379; IC2-NEXT:    [[CMP:%.*]] = icmp eq i64 [[IV_NEXT]], 100
380; IC2-NEXT:    br i1 [[CMP]], label %[[EXIT:.*]], label %[[IF_THEN1]]
381; IC2:       [[EXIT]]:
382; IC2-NEXT:    ret void
383;
384entry:
385  br label %loop.header
386
387loop.header:
388  %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop.latch ], [ %iv.next, %loop.header ]
389  %iv.next = add i64 %iv, 1
390  switch i64 %iv, label %loop.latch [
391  i64 120, label %loop.header
392  i64 100, label %loop.latch
393  ]
394
395if.then:
396  %gep = getelementptr inbounds i64, ptr %start, i64 %iv
397  store i64 42, ptr %gep, align 1
398  br label %loop.latch
399
400loop.latch:
401  %cmp = icmp eq i64 %iv.next, 100
402  br i1 %cmp, label %exit, label %loop.header
403
404exit:
405  ret void
406}
407
408define void @switch_all_to_default(ptr %start) {
409; IC1-LABEL: define void @switch_all_to_default(
410; IC1-SAME: ptr [[START:%.*]]) {
411; IC1-NEXT:  [[ENTRY:.*]]:
412; IC1-NEXT:    br i1 false, label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
413; IC1:       [[VECTOR_PH]]:
414; IC1-NEXT:    br label %[[VECTOR_BODY:.*]]
415; IC1:       [[VECTOR_BODY]]:
416; IC1-NEXT:    [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
417; IC1-NEXT:    [[TMP0:%.*]] = add i64 [[INDEX]], 0
418; IC1-NEXT:    [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[START]], i64 [[TMP0]]
419; IC1-NEXT:    [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 0
420; IC1-NEXT:    store <2 x i64> splat (i64 42), ptr [[TMP2]], align 1
421; IC1-NEXT:    [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2
422; IC1-NEXT:    [[TMP3:%.*]] = icmp eq i64 [[INDEX_NEXT]], 100
423; IC1-NEXT:    br i1 [[TMP3]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
424; IC1:       [[MIDDLE_BLOCK]]:
425; IC1-NEXT:    br i1 true, label %[[EXIT:.*]], label %[[SCALAR_PH]]
426; IC1:       [[SCALAR_PH]]:
427; IC1-NEXT:    [[BC_RESUME_VAL:%.*]] = phi i64 [ 100, %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
428; IC1-NEXT:    br label %[[LOOP_HEADER:.*]]
429; IC1:       [[LOOP_HEADER]]:
430; IC1-NEXT:    [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP_LATCH:.*]] ]
431; IC1-NEXT:    [[IV_NEXT]] = add i64 [[IV]], 1
432; IC1-NEXT:    switch i64 [[IV]], label %[[LOOP_LATCH]] [
433; IC1-NEXT:      i64 120, label %[[LOOP_LATCH]]
434; IC1-NEXT:      i64 100, label %[[LOOP_LATCH]]
435; IC1-NEXT:    ]
436; IC1:       [[LOOP_LATCH]]:
437; IC1-NEXT:    [[GEP:%.*]] = getelementptr inbounds i64, ptr [[START]], i64 [[IV]]
438; IC1-NEXT:    store i64 42, ptr [[GEP]], align 1
439; IC1-NEXT:    [[CMP:%.*]] = icmp eq i64 [[IV_NEXT]], 100
440; IC1-NEXT:    br i1 [[CMP]], label %[[EXIT]], label %[[LOOP_HEADER]], !llvm.loop [[LOOP5:![0-9]+]]
441; IC1:       [[EXIT]]:
442; IC1-NEXT:    ret void
443;
444; IC2-LABEL: define void @switch_all_to_default(
445; IC2-SAME: ptr [[START:%.*]]) {
446; IC2-NEXT:  [[ENTRY:.*]]:
447; IC2-NEXT:    br i1 false, label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
448; IC2:       [[VECTOR_PH]]:
449; IC2-NEXT:    br label %[[VECTOR_BODY:.*]]
450; IC2:       [[VECTOR_BODY]]:
451; IC2-NEXT:    [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
452; IC2-NEXT:    [[TMP0:%.*]] = add i64 [[INDEX]], 0
453; IC2-NEXT:    [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[START]], i64 [[TMP0]]
454; IC2-NEXT:    [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[TMP2]], i32 0
455; IC2-NEXT:    [[TMP5:%.*]] = getelementptr inbounds i64, ptr [[TMP2]], i32 2
456; IC2-NEXT:    store <2 x i64> splat (i64 42), ptr [[TMP4]], align 1
457; IC2-NEXT:    store <2 x i64> splat (i64 42), ptr [[TMP5]], align 1
458; IC2-NEXT:    [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
459; IC2-NEXT:    [[TMP6:%.*]] = icmp eq i64 [[INDEX_NEXT]], 100
460; IC2-NEXT:    br i1 [[TMP6]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
461; IC2:       [[MIDDLE_BLOCK]]:
462; IC2-NEXT:    br i1 true, label %[[EXIT:.*]], label %[[SCALAR_PH]]
463; IC2:       [[SCALAR_PH]]:
464; IC2-NEXT:    [[BC_RESUME_VAL:%.*]] = phi i64 [ 100, %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
465; IC2-NEXT:    br label %[[LOOP_HEADER:.*]]
466; IC2:       [[LOOP_HEADER]]:
467; IC2-NEXT:    [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP_LATCH:.*]] ]
468; IC2-NEXT:    [[IV_NEXT]] = add i64 [[IV]], 1
469; IC2-NEXT:    switch i64 [[IV]], label %[[LOOP_LATCH]] [
470; IC2-NEXT:      i64 120, label %[[LOOP_LATCH]]
471; IC2-NEXT:      i64 100, label %[[LOOP_LATCH]]
472; IC2-NEXT:    ]
473; IC2:       [[LOOP_LATCH]]:
474; IC2-NEXT:    [[GEP:%.*]] = getelementptr inbounds i64, ptr [[START]], i64 [[IV]]
475; IC2-NEXT:    store i64 42, ptr [[GEP]], align 1
476; IC2-NEXT:    [[CMP:%.*]] = icmp eq i64 [[IV_NEXT]], 100
477; IC2-NEXT:    br i1 [[CMP]], label %[[EXIT]], label %[[LOOP_HEADER]], !llvm.loop [[LOOP5:![0-9]+]]
478; IC2:       [[EXIT]]:
479; IC2-NEXT:    ret void
480;
481entry:
482  br label %loop.header
483
484loop.header:
485  %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop.latch ]
486  %iv.next = add i64 %iv, 1
487  switch i64 %iv, label %loop.latch [
488  i64 120, label %loop.latch
489  i64 100, label %loop.latch
490  ]
491
492loop.latch:
493  %gep = getelementptr inbounds i64, ptr %start, i64 %iv
494  store i64 42, ptr %gep, align 1
495  %cmp = icmp eq i64 %iv.next, 100
496  br i1 %cmp, label %exit, label %loop.header
497
498exit:
499  ret void
500}
501;.
502; IC1: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}
503; IC1: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}
504; IC1: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"}
505; IC1: [[LOOP3]] = distinct !{[[LOOP3]], [[META2]], [[META1]]}
506; IC1: [[LOOP4]] = distinct !{[[LOOP4]], [[META1]], [[META2]]}
507; IC1: [[LOOP5]] = distinct !{[[LOOP5]], [[META2]], [[META1]]}
508;.
509; IC2: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}
510; IC2: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}
511; IC2: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"}
512; IC2: [[LOOP3]] = distinct !{[[LOOP3]], [[META2]], [[META1]]}
513; IC2: [[LOOP4]] = distinct !{[[LOOP4]], [[META1]], [[META2]]}
514; IC2: [[LOOP5]] = distinct !{[[LOOP5]], [[META2]], [[META1]]}
515;.
516