1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 2; RUN: opt -passes=loop-distribute,loop-vectorize -enable-loop-distribute -force-vector-width=4 -force-vector-interleave=1 -S \ 3; RUN: %s | FileCheck %s 4 5; This test is to assure LoopAccessInfo invalidation after LoopVectorize 6; modifies the IR. 7define void @reduced(ptr %0, ptr %1, i64 %iv, ptr %2, i64 %iv76, i64 %iv93) { 8; CHECK-LABEL: @reduced( 9; CHECK-NEXT: entry: 10; CHECK-NEXT: [[TMP3:%.*]] = add i64 [[IV:%.*]], 1 11; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP3]], 4 12; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] 13; CHECK: vector.ph: 14; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP3]], 4 15; CHECK-NEXT: [[IND_END:%.*]] = sub i64 [[TMP3]], [[N_MOD_VF]] 16; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] 17; CHECK: vector.body: 18; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] 19; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 20; CHECK-NEXT: [[TMP8:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[IND_END]] 21; CHECK-NEXT: br i1 [[TMP8]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] 22; CHECK: middle.block: 23; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP3]], [[IND_END]] 24; CHECK-NEXT: [[IND_ESCAPE:%.*]] = sub i64 [[IND_END]], 1 25; CHECK-NEXT: br i1 [[CMP_N]], label [[LOOP_2_PREHEADER:%.*]], label [[SCALAR_PH]] 26; CHECK: scalar.ph: 27; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[IND_END]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ] 28; CHECK-NEXT: [[BC_RESUME_VAL1:%.*]] = phi i64 [ [[IND_END]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY]] ] 29; CHECK-NEXT: br label [[LOOP_1:%.*]] 30; CHECK: loop.1: 31; CHECK-NEXT: [[IV761:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT77:%.*]], [[LOOP_1]] ] 32; CHECK-NEXT: [[IV4:%.*]] = phi i64 [ [[BC_RESUME_VAL1]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LOOP_1]] ] 33; CHECK-NEXT: [[IV_NEXT77]] = add i64 [[IV761]], 1 34; CHECK-NEXT: [[ARRAYIDX_I_I50:%.*]] = getelementptr i32, ptr [[TMP0:%.*]], i64 [[IV76:%.*]] 35; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV4]], 1 36; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV4]], [[IV]] 37; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label [[LOOP_2_PREHEADER]], label [[LOOP_1]], !llvm.loop [[LOOP3:![0-9]+]] 38; CHECK: loop.2.preheader: 39; CHECK-NEXT: [[IV761_LCSSA:%.*]] = phi i64 [ [[IV761]], [[LOOP_1]] ], [ [[IND_ESCAPE]], [[MIDDLE_BLOCK]] ] 40; CHECK-NEXT: [[MIN_ITERS_CHECK6:%.*]] = icmp ult i64 [[TMP3]], 4 41; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK6]], label [[SCALAR_PH5:%.*]], label [[VECTOR_MEMCHECK:%.*]] 42; CHECK: vector.memcheck: 43; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[TMP1:%.*]], i64 4 44; CHECK-NEXT: [[TMP9:%.*]] = shl i64 [[IV761_LCSSA]], 2 45; CHECK-NEXT: [[SCEVGEP2:%.*]] = getelementptr i8, ptr [[TMP0]], i64 [[TMP9]] 46; CHECK-NEXT: [[TMP10:%.*]] = add i64 [[TMP9]], 4 47; CHECK-NEXT: [[SCEVGEP3:%.*]] = getelementptr i8, ptr [[TMP0]], i64 [[TMP10]] 48; CHECK-NEXT: [[BOUND0:%.*]] = icmp ult ptr [[TMP1]], [[SCEVGEP3]] 49; CHECK-NEXT: [[BOUND1:%.*]] = icmp ult ptr [[SCEVGEP2]], [[SCEVGEP]] 50; CHECK-NEXT: [[FOUND_CONFLICT:%.*]] = and i1 [[BOUND0]], [[BOUND1]] 51; CHECK-NEXT: br i1 [[FOUND_CONFLICT]], label [[SCALAR_PH5]], label [[VECTOR_PH7:%.*]] 52; CHECK: vector.ph7: 53; CHECK-NEXT: [[N_MOD_VF8:%.*]] = urem i64 [[TMP3]], 4 54; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP3]], [[N_MOD_VF8]] 55; CHECK-NEXT: br label [[VECTOR_BODY10:%.*]] 56; CHECK: vector.body10: 57; CHECK-NEXT: [[INDEX12:%.*]] = phi i64 [ 0, [[VECTOR_PH7]] ], [ [[INDEX_NEXT13:%.*]], [[VECTOR_BODY10]] ] 58; CHECK-NEXT: store i32 0, ptr [[TMP1]], align 4, !alias.scope !4, !noalias !7 59; CHECK-NEXT: [[INDEX_NEXT13]] = add nuw i64 [[INDEX12]], 4 60; CHECK-NEXT: [[TMP11:%.*]] = icmp eq i64 [[INDEX_NEXT13]], [[N_VEC]] 61; CHECK-NEXT: br i1 [[TMP11]], label [[MIDDLE_BLOCK4:%.*]], label [[VECTOR_BODY10]], !llvm.loop [[LOOP9:![0-9]+]] 62; CHECK: middle.block4: 63; CHECK-NEXT: [[CMP_N10:%.*]] = icmp eq i64 [[TMP3]], [[N_VEC]] 64; CHECK-NEXT: br i1 [[CMP_N10]], label [[LOOP_3_LR_PH:%.*]], label [[SCALAR_PH5]] 65; CHECK: scalar.ph5: 66; CHECK-NEXT: [[BC_RESUME_VAL13:%.*]] = phi i64 [ [[N_VEC]], [[MIDDLE_BLOCK4]] ], [ 0, [[VECTOR_MEMCHECK]] ], [ 0, [[LOOP_2_PREHEADER]] ] 67; CHECK-NEXT: br label [[LOOP_2:%.*]] 68; CHECK: loop.3.lr.ph: 69; CHECK-NEXT: [[IDXPROM_I_I61:%.*]] = and i64 [[IV761_LCSSA]], 1 70; CHECK-NEXT: [[ARRAYIDX_I_I62:%.*]] = getelementptr i32, ptr [[TMP0]], i64 [[IDXPROM_I_I61]] 71; CHECK-NEXT: [[MIN_ITERS_CHECK22:%.*]] = icmp ult i64 [[TMP3]], 4 72; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK22]], label [[SCALAR_PH22:%.*]], label [[VECTOR_MEMCHECK15:%.*]] 73; CHECK: vector.memcheck15: 74; CHECK-NEXT: [[SCEVGEP15:%.*]] = getelementptr i8, ptr [[TMP1]], i64 4 75; CHECK-NEXT: [[TMP12:%.*]] = shl nuw nsw i64 [[IDXPROM_I_I61]], 2 76; CHECK-NEXT: [[TMP13:%.*]] = add nuw nsw i64 [[TMP12]], 4 77; CHECK-NEXT: [[SCEVGEP16:%.*]] = getelementptr i8, ptr [[TMP0]], i64 [[TMP13]] 78; CHECK-NEXT: [[BOUND017:%.*]] = icmp ult ptr [[TMP1]], [[SCEVGEP16]] 79; CHECK-NEXT: [[BOUND118:%.*]] = icmp ult ptr [[ARRAYIDX_I_I62]], [[SCEVGEP15]] 80; CHECK-NEXT: [[FOUND_CONFLICT19:%.*]] = and i1 [[BOUND017]], [[BOUND118]] 81; CHECK-NEXT: br i1 [[FOUND_CONFLICT19]], label [[SCALAR_PH22]], label [[VECTOR_PH24:%.*]] 82; CHECK: vector.ph24: 83; CHECK-NEXT: [[N_MOD_VF24:%.*]] = urem i64 [[TMP3]], 4 84; CHECK-NEXT: [[N_VEC25:%.*]] = sub i64 [[TMP3]], [[N_MOD_VF24]] 85; CHECK-NEXT: br label [[VECTOR_BODY27:%.*]] 86; CHECK: vector.body27: 87; CHECK-NEXT: [[INDEX29:%.*]] = phi i64 [ 0, [[VECTOR_PH24]] ], [ [[INDEX_NEXT29:%.*]], [[VECTOR_BODY27]] ] 88; CHECK-NEXT: store i32 0, ptr [[TMP1]], align 4, !alias.scope !10, !noalias !13 89; CHECK-NEXT: [[INDEX_NEXT29]] = add nuw i64 [[INDEX29]], 4 90; CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[INDEX_NEXT29]], [[N_VEC25]] 91; CHECK-NEXT: br i1 [[TMP10]], label [[MIDDLE_BLOCK21:%.*]], label [[VECTOR_BODY27]], !llvm.loop [[LOOP15:![0-9]+]] 92; CHECK: middle.block21: 93; CHECK-NEXT: [[CMP_N27:%.*]] = icmp eq i64 [[TMP3]], [[N_VEC25]] 94; CHECK-NEXT: br i1 [[CMP_N27]], label [[LOOP_CLEANUP:%.*]], label [[SCALAR_PH22]] 95; CHECK: scalar.ph22: 96; CHECK-NEXT: [[BC_RESUME_VAL26:%.*]] = phi i64 [ [[N_VEC25]], [[MIDDLE_BLOCK21]] ], [ 0, [[VECTOR_MEMCHECK15]] ], [ 0, [[LOOP_3_LR_PH]] ] 97; CHECK-NEXT: br label [[LOOP_3:%.*]] 98; CHECK: loop.2: 99; CHECK-NEXT: [[IV846:%.*]] = phi i64 [ [[IV_NEXT85:%.*]], [[LOOP_2]] ], [ [[BC_RESUME_VAL13]], [[SCALAR_PH5]] ] 100; CHECK-NEXT: [[IV_NEXT87:%.*]] = add i64 0, 0 101; CHECK-NEXT: [[ARRAYIDX_I_I56:%.*]] = getelementptr i32, ptr [[TMP0]], i64 [[IV761_LCSSA]] 102; CHECK-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX_I_I56]], align 4 103; CHECK-NEXT: store i32 0, ptr [[TMP1]], align 4 104; CHECK-NEXT: [[IV_NEXT85]] = add i64 [[IV846]], 1 105; CHECK-NEXT: [[EXITCOND92_NOT:%.*]] = icmp eq i64 [[IV846]], [[IV]] 106; CHECK-NEXT: br i1 [[EXITCOND92_NOT]], label [[LOOP_3_LR_PH]], label [[LOOP_2]], !llvm.loop [[LOOP16:![0-9]+]] 107; CHECK: loop.3: 108; CHECK-NEXT: [[IV932:%.*]] = phi i64 [ [[BC_RESUME_VAL26]], [[SCALAR_PH22]] ], [ [[IV_NEXT94:%.*]], [[LOOP_3]] ] 109; CHECK-NEXT: [[TMP16:%.*]] = load i32, ptr [[ARRAYIDX_I_I62]], align 4 110; CHECK-NEXT: [[ARRAYIDX_I_I653:%.*]] = getelementptr i32, ptr [[TMP2:%.*]], i64 [[IV93:%.*]] 111; CHECK-NEXT: store i32 0, ptr [[TMP1]], align 4 112; CHECK-NEXT: [[IV_NEXT94]] = add i64 [[IV932]], 1 113; CHECK-NEXT: [[EXITCOND97_NOT:%.*]] = icmp eq i64 [[IV932]], [[IV]] 114; CHECK-NEXT: br i1 [[EXITCOND97_NOT]], label [[LOOP_CLEANUP]], label [[LOOP_3]], !llvm.loop [[LOOP17:![0-9]+]] 115; CHECK: loop.cleanup: 116; CHECK-NEXT: ret void 117; 118entry: 119 br label %loop.1 120 121loop.1: ; preds = %loop.1, %entry 122 %iv761 = phi i64 [ 0, %entry ], [ %iv.next77, %loop.1 ] 123 %iv4 = phi i64 [ 0, %entry ], [ %iv.next, %loop.1 ] 124 %iv.next77 = add i64 %iv761, 1 125 %arrayidx.i.i50 = getelementptr i32, ptr %0, i64 %iv76 126 %iv.next = add i64 %iv4, 1 127 %exitcond.not = icmp eq i64 %iv4, %iv 128 br i1 %exitcond.not, label %loop.2.preheader, label %loop.1 129 130loop.2.preheader: ; preds = %loop.1 131 br label %loop.2 132 133loop.3.lr.ph: ; preds = %loop.2 134 %idxprom.i.i61 = and i64 %iv761, 1 135 %arrayidx.i.i62 = getelementptr i32, ptr %0, i64 %idxprom.i.i61 136 br label %loop.3 137 138loop.2: ; preds = %loop.2, %loop.2.preheader 139 %iv846 = phi i64 [ %iv.next85, %loop.2 ], [ 0, %loop.2.preheader ] 140 %iv.next87 = add i64 0, 0 141 %arrayidx.i.i56 = getelementptr i32, ptr %0, i64 %iv761 142 %3 = load i32, ptr %arrayidx.i.i56, align 4 143 store i32 0, ptr %1, align 4 144 %iv.next85 = add i64 %iv846, 1 145 %exitcond92.not = icmp eq i64 %iv846, %iv 146 br i1 %exitcond92.not, label %loop.3.lr.ph, label %loop.2 147 148loop.3: ; preds = %loop.3, %loop.3.lr.ph 149 %iv932 = phi i64 [ 0, %loop.3.lr.ph ], [ %iv.next94, %loop.3 ] 150 %4 = load i32, ptr %arrayidx.i.i62, align 4 151 %arrayidx.i.i653 = getelementptr i32, ptr %2, i64 %iv93 152 store i32 0, ptr %1, align 4 153 %iv.next94 = add i64 %iv932, 1 154 %exitcond97.not = icmp eq i64 %iv932, %iv 155 br i1 %exitcond97.not, label %loop.cleanup, label %loop.3 156 157loop.cleanup: ; preds = %loop.3 158 ret void 159} 160