1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 2; RUN: opt < %s -force-vector-width=2 -force-vector-interleave=1 -force-widen-divrem-via-safe-divisor=0 -passes=loop-vectorize -S | FileCheck %s 3 4; Test case for PR44488. Checks that the correct predicates are created for 5; branches where true and false successors are equal. See the checks involving 6; CMP1 and CMP2. 7 8@v_38 = global i16 12061, align 1 9@v_39 = global i16 11333, align 1 10 11define i16 @test_true_and_false_branch_equal() { 12; CHECK-LABEL: @test_true_and_false_branch_equal( 13; CHECK-NEXT: entry: 14; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] 15; CHECK: vector.ph: 16; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] 17; CHECK: vector.body: 18; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[PRED_SREM_CONTINUE2:%.*]] ] 19; CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr @v_38, align 1 20; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <2 x i16> poison, i16 [[TMP0]], i64 0 21; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <2 x i16> [[BROADCAST_SPLATINSERT]], <2 x i16> poison, <2 x i32> zeroinitializer 22; CHECK-NEXT: [[TMP1:%.*]] = icmp eq <2 x i16> [[BROADCAST_SPLAT]], zeroinitializer 23; CHECK-NEXT: [[TMP2:%.*]] = xor <2 x i1> [[TMP1]], splat (i1 true) 24; CHECK-NEXT: [[TMP3:%.*]] = extractelement <2 x i1> [[TMP2]], i32 0 25; CHECK-NEXT: br i1 [[TMP3]], label [[PRED_SREM_IF:%.*]], label [[PRED_SREM_CONTINUE:%.*]] 26; CHECK: pred.srem.if: 27; CHECK-NEXT: [[TMP4:%.*]] = srem i16 5786, [[TMP0]] 28; CHECK-NEXT: [[TMP5:%.*]] = insertelement <2 x i16> poison, i16 [[TMP4]], i32 0 29; CHECK-NEXT: br label [[PRED_SREM_CONTINUE]] 30; CHECK: pred.srem.continue: 31; CHECK-NEXT: [[TMP6:%.*]] = phi <2 x i16> [ poison, [[VECTOR_BODY]] ], [ [[TMP5]], [[PRED_SREM_IF]] ] 32; CHECK-NEXT: [[TMP7:%.*]] = extractelement <2 x i1> [[TMP2]], i32 1 33; CHECK-NEXT: br i1 [[TMP7]], label [[PRED_SREM_IF1:%.*]], label [[PRED_SREM_CONTINUE2]] 34; CHECK: pred.srem.if1: 35; CHECK-NEXT: [[TMP8:%.*]] = srem i16 5786, [[TMP0]] 36; CHECK-NEXT: [[TMP9:%.*]] = insertelement <2 x i16> [[TMP6]], i16 [[TMP8]], i32 1 37; CHECK-NEXT: br label [[PRED_SREM_CONTINUE2]] 38; CHECK: pred.srem.continue2: 39; CHECK-NEXT: [[TMP10:%.*]] = phi <2 x i16> [ [[TMP6]], [[PRED_SREM_CONTINUE]] ], [ [[TMP9]], [[PRED_SREM_IF1]] ] 40; CHECK-NEXT: [[PREDPHI:%.*]] = select <2 x i1> [[TMP1]], <2 x i16> splat (i16 5786), <2 x i16> [[TMP10]] 41; CHECK-NEXT: [[TMP11:%.*]] = extractelement <2 x i16> [[PREDPHI]], i32 1 42; CHECK-NEXT: store i16 [[TMP11]], ptr @v_39, align 1 43; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 2 44; CHECK-NEXT: [[TMP12:%.*]] = icmp eq i32 [[INDEX_NEXT]], 12 45; CHECK-NEXT: br i1 [[TMP12]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] 46; CHECK: middle.block: 47; CHECK-NEXT: br i1 true, label [[EXIT:%.*]], label [[SCALAR_PH]] 48; CHECK: scalar.ph: 49; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i16 [ 111, [[MIDDLE_BLOCK]] ], [ 99, [[ENTRY:%.*]] ] 50; CHECK-NEXT: br label [[FOR_BODY:%.*]] 51; CHECK: for.body: 52; CHECK-NEXT: [[I_07:%.*]] = phi i16 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[INC7:%.*]], [[FOR_LATCH:%.*]] ] 53; CHECK-NEXT: [[LV:%.*]] = load i16, ptr @v_38, align 1 54; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i16 [[LV]], 32767 55; CHECK-NEXT: br i1 [[CMP1]], label [[COND_END:%.*]], label [[COND_END]] 56; CHECK: cond.end: 57; CHECK-NEXT: [[CMP2:%.*]] = icmp eq i16 [[LV]], 0 58; CHECK-NEXT: br i1 [[CMP2]], label [[FOR_LATCH]], label [[COND_FALSE4:%.*]] 59; CHECK: cond.false4: 60; CHECK-NEXT: [[REM:%.*]] = srem i16 5786, [[LV]] 61; CHECK-NEXT: br label [[FOR_LATCH]] 62; CHECK: for.latch: 63; CHECK-NEXT: [[COND6:%.*]] = phi i16 [ [[REM]], [[COND_FALSE4]] ], [ 5786, [[COND_END]] ] 64; CHECK-NEXT: store i16 [[COND6]], ptr @v_39, align 1 65; CHECK-NEXT: [[INC7]] = add nsw i16 [[I_07]], 1 66; CHECK-NEXT: [[CMP:%.*]] = icmp slt i16 [[INC7]], 111 67; CHECK-NEXT: br i1 [[CMP]], label [[FOR_BODY]], label [[EXIT]], !llvm.loop [[LOOP3:![0-9]+]] 68; CHECK: exit: 69; CHECK-NEXT: [[RV:%.*]] = load i16, ptr @v_39, align 1 70; CHECK-NEXT: ret i16 [[RV]] 71; 72entry: 73 br label %for.body 74 75for.body: ; preds = %entry, %for.latch 76 %i.07 = phi i16 [ 99, %entry ], [ %inc7, %for.latch ] 77 %lv = load i16, ptr @v_38, align 1 78 %cmp1 = icmp eq i16 %lv, 32767 79 br i1 %cmp1, label %cond.end, label %cond.end 80 81cond.end: ; preds = %for.body, %for.body 82 %cmp2 = icmp eq i16 %lv, 0 83 br i1 %cmp2, label %for.latch, label %cond.false4 84 85cond.false4: ; preds = %cond.end 86 %rem = srem i16 5786, %lv 87 br label %for.latch 88 89for.latch: ; preds = %cond.end, %cond.false4 90 %cond6 = phi i16 [ %rem, %cond.false4 ], [ 5786, %cond.end ] 91 store i16 %cond6, ptr @v_39, align 1 92 %inc7 = add nsw i16 %i.07, 1 93 %cmp = icmp slt i16 %inc7, 111 94 br i1 %cmp, label %for.body, label %exit 95 96exit: ; preds = %for.latch 97 %rv = load i16, ptr @v_39, align 1 98 ret i16 %rv 99} 100