xref: /llvm-project/llvm/test/Transforms/LoopVectorize/pr39099.ll (revision eecb99c5f66c8491766628a2925587e20f3b1dbd)
1; REQUIRES: asserts
2; RUN: opt -S -passes=loop-vectorize -force-vector-width=8 -force-vector-interleave=1 -enable-interleaved-mem-accesses -debug-only=loop-vectorize,vectorutils -disable-output < %s 2>&1 | FileCheck %s
3
4target datalayout = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"
5
6; Ensure that we don't create interleave groups for predicated
7; strided accesses.
8
9; CHECK: LV: Checking a loop in 'masked_strided'
10; CHECK: LV: Analyzing interleaved accesses...
11; CHECK-NOT: LV: Creating an interleave group
12
13define dso_local void @masked_strided(ptr noalias nocapture readonly %p, ptr noalias nocapture %q, i8 zeroext %guard) local_unnamed_addr {
14entry:
15  %conv = zext i8 %guard to i32
16  br label %for.body
17
18for.body:
19  %ix.017 = phi i32 [ 0, %entry ], [ %inc, %for.inc ]
20  %cmp1 = icmp ugt i32 %ix.017, %conv
21  br i1 %cmp1, label %if.then, label %for.inc
22
23if.then:
24  %mul = shl nuw nsw i32 %ix.017, 1
25  %arrayidx = getelementptr inbounds i8, ptr %p, i32 %mul
26  %0 = load i8, ptr %arrayidx, align 1
27  %arrayidx4 = getelementptr inbounds i8, ptr %q, i32 %mul
28  store i8 %0, ptr %arrayidx4, align 1
29  %sub = sub i8 0, %0
30  %add = or disjoint i32 %mul, 1
31  %arrayidx8 = getelementptr inbounds i8, ptr %q, i32 %add
32  store i8 %sub, ptr %arrayidx8, align 1
33  br label %for.inc
34
35for.inc:
36  %inc = add nuw nsw i32 %ix.017, 1
37  %exitcond = icmp eq i32 %inc, 1024
38  br i1 %exitcond, label %for.end, label %for.body
39
40for.end:
41  ret void
42}
43