1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --prefix-filecheck-ir-name VAR_ --version 2 2; RUN: opt -S -passes=loop-vectorize -force-vector-interleave=1 -force-vector-width=2 < %s | FileCheck %s 3 4@global = local_unnamed_addr global i32 0, align 4 5@global.1 = local_unnamed_addr global i32 0, align 4 6@global.2 = local_unnamed_addr global float 0x3EF0000000000000, align 4 7 8define void @PR33706(ptr nocapture readonly %arg, ptr nocapture %arg1, i32 %arg2) local_unnamed_addr { 9; CHECK-LABEL: define void @PR33706 10; CHECK-SAME: (ptr readonly captures(none) [[ARG:%.*]], ptr captures(none) [[ARG1:%.*]], i32 [[ARG2:%.*]]) local_unnamed_addr { 11; CHECK-NEXT: bb: 12; CHECK-NEXT: [[TMP:%.*]] = load i32, ptr @global.1, align 4 13; CHECK-NEXT: [[VAR_TMP3:%.*]] = getelementptr inbounds float, ptr [[ARG]], i64 190 14; CHECK-NEXT: [[VAR_TMP4:%.*]] = getelementptr inbounds float, ptr [[ARG1]], i64 512 15; CHECK-NEXT: [[VAR_TMP5:%.*]] = and i32 [[TMP]], 65535 16; CHECK-NEXT: [[VAR_TMP6:%.*]] = icmp ugt i32 [[ARG2]], 65536 17; CHECK-NEXT: br i1 [[VAR_TMP6]], label [[BB7:%.*]], label [[BB9:%.*]] 18; CHECK: bb7: 19; CHECK-NEXT: [[VAR_TMP8:%.*]] = load i32, ptr @global, align 4 20; CHECK-NEXT: br label [[BB27:%.*]] 21; CHECK: bb9: 22; CHECK-NEXT: [[VAR_TMP10:%.*]] = udiv i32 65536, [[ARG2]] 23; CHECK-NEXT: br label [[BB11:%.*]] 24; CHECK: bb11: 25; CHECK-NEXT: [[VAR_TMP12:%.*]] = phi i32 [ [[VAR_TMP20:%.*]], [[BB11]] ], [ [[VAR_TMP5]], [[BB9]] ] 26; CHECK-NEXT: [[VAR_TMP13:%.*]] = phi ptr [ [[VAR_TMP18:%.*]], [[BB11]] ], [ [[VAR_TMP4]], [[BB9]] ] 27; CHECK-NEXT: [[VAR_TMP14:%.*]] = phi i32 [ [[VAR_TMP16:%.*]], [[BB11]] ], [ [[VAR_TMP10]], [[BB9]] ] 28; CHECK-NEXT: [[VAR_TMP15:%.*]] = phi i32 [ [[VAR_TMP19:%.*]], [[BB11]] ], [ [[TMP]], [[BB9]] ] 29; CHECK-NEXT: [[VAR_TMP16]] = add nsw i32 [[VAR_TMP14]], -1 30; CHECK-NEXT: [[VAR_TMP17:%.*]] = sitofp i32 [[VAR_TMP12]] to float 31; CHECK-NEXT: store float [[VAR_TMP17]], ptr [[VAR_TMP13]], align 4 32; CHECK-NEXT: [[VAR_TMP18]] = getelementptr inbounds float, ptr [[VAR_TMP13]], i64 1 33; CHECK-NEXT: [[VAR_TMP19]] = add i32 [[VAR_TMP15]], [[ARG2]] 34; CHECK-NEXT: [[VAR_TMP20]] = and i32 [[VAR_TMP19]], 65535 35; CHECK-NEXT: [[VAR_TMP21:%.*]] = icmp eq i32 [[VAR_TMP16]], 0 36; CHECK-NEXT: br i1 [[VAR_TMP21]], label [[BB22:%.*]], label [[BB11]] 37; CHECK: bb22: 38; CHECK-NEXT: [[VAR_TMP23:%.*]] = phi ptr [ [[VAR_TMP18]], [[BB11]] ] 39; CHECK-NEXT: [[VAR_TMP24:%.*]] = phi i32 [ [[VAR_TMP19]], [[BB11]] ] 40; CHECK-NEXT: [[VAR_TMP25:%.*]] = phi i32 [ [[VAR_TMP20]], [[BB11]] ] 41; CHECK-NEXT: [[VAR_TMP26:%.*]] = ashr i32 [[VAR_TMP24]], 16 42; CHECK-NEXT: store i32 [[VAR_TMP26]], ptr @global, align 4 43; CHECK-NEXT: br label [[BB27]] 44; CHECK: bb27: 45; CHECK-NEXT: [[VAR_TMP28:%.*]] = phi i32 [ [[VAR_TMP26]], [[BB22]] ], [ [[VAR_TMP8]], [[BB7]] ] 46; CHECK-NEXT: [[VAR_TMP29:%.*]] = phi ptr [ [[VAR_TMP23]], [[BB22]] ], [ [[VAR_TMP4]], [[BB7]] ] 47; CHECK-NEXT: [[VAR_TMP30:%.*]] = phi i32 [ [[VAR_TMP25]], [[BB22]] ], [ [[VAR_TMP5]], [[BB7]] ] 48; CHECK-NEXT: [[VAR_TMP31:%.*]] = sext i32 [[VAR_TMP28]] to i64 49; CHECK-NEXT: [[VAR_TMP32:%.*]] = getelementptr inbounds float, ptr [[VAR_TMP3]], i64 [[VAR_TMP31]] 50; CHECK-NEXT: [[VAR_TMP33:%.*]] = load float, ptr [[VAR_TMP32]], align 4 51; CHECK-NEXT: [[VAR_TMP34:%.*]] = sitofp i32 [[VAR_TMP30]] to float 52; CHECK-NEXT: [[VAR_TMP35:%.*]] = load float, ptr @global.2, align 4 53; CHECK-NEXT: [[VAR_TMP36:%.*]] = fmul float [[VAR_TMP35]], [[VAR_TMP34]] 54; CHECK-NEXT: [[VAR_TMP37:%.*]] = fadd float [[VAR_TMP33]], [[VAR_TMP36]] 55; CHECK-NEXT: store float [[VAR_TMP37]], ptr [[VAR_TMP29]], align 4 56; CHECK-NEXT: ret void 57; 58bb: 59 %tmp = load i32, ptr @global.1, align 4 60 %tmp3 = getelementptr inbounds float, ptr %arg, i64 190 61 %tmp4 = getelementptr inbounds float, ptr %arg1, i64 512 62 %tmp5 = and i32 %tmp, 65535 63 %tmp6 = icmp ugt i32 %arg2, 65536 64 br i1 %tmp6, label %bb7, label %bb9 65 66bb7: ; preds = %bb 67 %tmp8 = load i32, ptr @global, align 4 68 br label %bb27 69 70bb9: ; preds = %bb 71 %tmp10 = udiv i32 65536, %arg2 72 br label %bb11 73 74bb11: ; preds = %bb11, %bb9 75 %tmp12 = phi i32 [ %tmp20, %bb11 ], [ %tmp5, %bb9 ] 76 %tmp13 = phi ptr [ %tmp18, %bb11 ], [ %tmp4, %bb9 ] 77 %tmp14 = phi i32 [ %tmp16, %bb11 ], [ %tmp10, %bb9 ] 78 %tmp15 = phi i32 [ %tmp19, %bb11 ], [ %tmp, %bb9 ] 79 %tmp16 = add nsw i32 %tmp14, -1 80 %tmp17 = sitofp i32 %tmp12 to float 81 store float %tmp17, ptr %tmp13, align 4 82 %tmp18 = getelementptr inbounds float, ptr %tmp13, i64 1 83 %tmp19 = add i32 %tmp15, %arg2 84 %tmp20 = and i32 %tmp19, 65535 85 %tmp21 = icmp eq i32 %tmp16, 0 86 br i1 %tmp21, label %bb22, label %bb11 87 88bb22: ; preds = %bb11 89 %tmp23 = phi ptr [ %tmp18, %bb11 ] 90 %tmp24 = phi i32 [ %tmp19, %bb11 ] 91 %tmp25 = phi i32 [ %tmp20, %bb11 ] 92 %tmp26 = ashr i32 %tmp24, 16 93 store i32 %tmp26, ptr @global, align 4 94 br label %bb27 95 96bb27: ; preds = %bb22, %bb7 97 %tmp28 = phi i32 [ %tmp26, %bb22 ], [ %tmp8, %bb7 ] 98 %tmp29 = phi ptr [ %tmp23, %bb22 ], [ %tmp4, %bb7 ] 99 %tmp30 = phi i32 [ %tmp25, %bb22 ], [ %tmp5, %bb7 ] 100 %tmp31 = sext i32 %tmp28 to i64 101 %tmp32 = getelementptr inbounds float, ptr %tmp3, i64 %tmp31 102 %tmp33 = load float, ptr %tmp32, align 4 103 %tmp34 = sitofp i32 %tmp30 to float 104 %tmp35 = load float, ptr @global.2, align 4 105 %tmp36 = fmul float %tmp35, %tmp34 106 %tmp37 = fadd float %tmp33, %tmp36 107 store float %tmp37, ptr %tmp29, align 4 108 ret void 109} 110