1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 2; RUN: opt -passes=loop-vectorize -force-vector-width=2 -force-vector-interleave=1 -S %s | FileCheck %s 3 4target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128-ni:1" 5 6declare void @init(ptr nocapture nofree) 7 8; Test case where the predicated load in the loop has an access size of 2 but 9; has an alignment of 4. 10define i16 @test_access_size_not_multiple_of_align(i64 %len, ptr %test_base) { 11; CHECK-LABEL: @test_access_size_not_multiple_of_align( 12; CHECK-NEXT: entry: 13; CHECK-NEXT: [[ALLOCA:%.*]] = alloca [163840 x i16], align 4 14; CHECK-NEXT: call void @init(ptr [[ALLOCA]]) 15; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] 16; CHECK: vector.ph: 17; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] 18; CHECK: vector.body: 19; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[PRED_LOAD_CONTINUE2:%.*]] ] 20; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <2 x i16> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP15:%.*]], [[PRED_LOAD_CONTINUE2]] ] 21; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 0 22; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i8, ptr [[TEST_BASE:%.*]], i64 [[TMP0]] 23; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds i8, ptr [[TMP1]], i32 0 24; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <2 x i8>, ptr [[TMP2]], align 1 25; CHECK-NEXT: [[TMP3:%.*]] = icmp sge <2 x i8> [[WIDE_LOAD]], zeroinitializer 26; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i1> [[TMP3]], i32 0 27; CHECK-NEXT: br i1 [[TMP4]], label [[PRED_LOAD_IF:%.*]], label [[PRED_LOAD_CONTINUE:%.*]] 28; CHECK: pred.load.if: 29; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds i16, ptr [[ALLOCA]], i64 [[TMP0]] 30; CHECK-NEXT: [[TMP6:%.*]] = load i16, ptr [[TMP5]], align 4 31; CHECK-NEXT: [[TMP7:%.*]] = insertelement <2 x i16> poison, i16 [[TMP6]], i32 0 32; CHECK-NEXT: br label [[PRED_LOAD_CONTINUE]] 33; CHECK: pred.load.continue: 34; CHECK-NEXT: [[TMP8:%.*]] = phi <2 x i16> [ poison, [[VECTOR_BODY]] ], [ [[TMP7]], [[PRED_LOAD_IF]] ] 35; CHECK-NEXT: [[TMP9:%.*]] = extractelement <2 x i1> [[TMP3]], i32 1 36; CHECK-NEXT: br i1 [[TMP9]], label [[PRED_LOAD_IF1:%.*]], label [[PRED_LOAD_CONTINUE2]] 37; CHECK: pred.load.if1: 38; CHECK-NEXT: [[TMP10:%.*]] = add i64 [[INDEX]], 1 39; CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds i16, ptr [[ALLOCA]], i64 [[TMP10]] 40; CHECK-NEXT: [[TMP12:%.*]] = load i16, ptr [[TMP11]], align 4 41; CHECK-NEXT: [[TMP13:%.*]] = insertelement <2 x i16> [[TMP8]], i16 [[TMP12]], i32 1 42; CHECK-NEXT: br label [[PRED_LOAD_CONTINUE2]] 43; CHECK: pred.load.continue2: 44; CHECK-NEXT: [[TMP14:%.*]] = phi <2 x i16> [ [[TMP8]], [[PRED_LOAD_CONTINUE]] ], [ [[TMP13]], [[PRED_LOAD_IF1]] ] 45; CHECK-NEXT: [[PREDPHI:%.*]] = select <2 x i1> [[TMP3]], <2 x i16> [[TMP14]], <2 x i16> zeroinitializer 46; CHECK-NEXT: [[TMP15]] = add <2 x i16> [[VEC_PHI]], [[PREDPHI]] 47; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2 48; CHECK-NEXT: [[TMP16:%.*]] = icmp eq i64 [[INDEX_NEXT]], 4096 49; CHECK-NEXT: br i1 [[TMP16]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] 50; CHECK: middle.block: 51; CHECK-NEXT: [[TMP17:%.*]] = call i16 @llvm.vector.reduce.add.v2i16(<2 x i16> [[TMP15]]) 52; CHECK-NEXT: br i1 true, label [[LOOP_EXIT:%.*]], label [[SCALAR_PH]] 53; CHECK: scalar.ph: 54; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ 4096, [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ] 55; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i16 [ [[TMP17]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY]] ] 56; CHECK-NEXT: br label [[LOOP:%.*]] 57; CHECK: loop: 58; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LATCH:%.*]] ] 59; CHECK-NEXT: [[ACCUM:%.*]] = phi i16 [ [[BC_MERGE_RDX]], [[SCALAR_PH]] ], [ [[ACCUM_NEXT:%.*]], [[LATCH]] ] 60; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1 61; CHECK-NEXT: [[TEST_ADDR:%.*]] = getelementptr inbounds i8, ptr [[TEST_BASE]], i64 [[IV]] 62; CHECK-NEXT: [[L_T:%.*]] = load i8, ptr [[TEST_ADDR]], align 1 63; CHECK-NEXT: [[CMP:%.*]] = icmp sge i8 [[L_T]], 0 64; CHECK-NEXT: br i1 [[CMP]], label [[PRED:%.*]], label [[LATCH]] 65; CHECK: pred: 66; CHECK-NEXT: [[ADDR:%.*]] = getelementptr inbounds i16, ptr [[ALLOCA]], i64 [[IV]] 67; CHECK-NEXT: [[VAL:%.*]] = load i16, ptr [[ADDR]], align 4 68; CHECK-NEXT: br label [[LATCH]] 69; CHECK: latch: 70; CHECK-NEXT: [[VAL_PHI:%.*]] = phi i16 [ 0, [[LOOP]] ], [ [[VAL]], [[PRED]] ] 71; CHECK-NEXT: [[ACCUM_NEXT]] = add i16 [[ACCUM]], [[VAL_PHI]] 72; CHECK-NEXT: [[EXIT:%.*]] = icmp eq i64 [[IV]], 4095 73; CHECK-NEXT: br i1 [[EXIT]], label [[LOOP_EXIT]], label [[LOOP]], !llvm.loop [[LOOP3:![0-9]+]] 74; CHECK: loop_exit: 75; CHECK-NEXT: [[ACCUM_NEXT_LCSSA:%.*]] = phi i16 [ [[ACCUM_NEXT]], [[LATCH]] ], [ [[TMP17]], [[MIDDLE_BLOCK]] ] 76; CHECK-NEXT: ret i16 [[ACCUM_NEXT_LCSSA]] 77; 78entry: 79 %alloca = alloca [163840 x i16], align 4 80 call void @init(ptr %alloca) 81 br label %loop 82loop: 83 %iv = phi i64 [ 0, %entry ], [ %iv.next, %latch ] 84 %accum = phi i16 [ 0, %entry ], [ %accum.next, %latch ] 85 %iv.next = add i64 %iv, 1 86 %test_addr = getelementptr inbounds i8, ptr %test_base, i64 %iv 87 %l.t = load i8, ptr %test_addr 88 %cmp = icmp sge i8 %l.t, 0 89 br i1 %cmp, label %pred, label %latch 90pred: 91 %addr = getelementptr inbounds i16, ptr %alloca, i64 %iv 92 %val = load i16, ptr %addr, align 4 93 br label %latch 94latch: 95 %val.phi = phi i16 [0, %loop], [%val, %pred] 96 %accum.next = add i16 %accum, %val.phi 97 %exit = icmp eq i64 %iv, 4095 98 br i1 %exit, label %loop_exit, label %loop 99 100loop_exit: 101 ret i16 %accum.next 102} 103 104; Test case where the predicated load in the loop has an access size of 4 and 105; an alignment of 4, but the start pointer is offset by 1. 106define i32 @test_access_size_multiple_of_align_but_offset_by_1(i64 %len, ptr %test_base) { 107; CHECK-LABEL: @test_access_size_multiple_of_align_but_offset_by_1( 108; CHECK-NEXT: entry: 109; CHECK-NEXT: [[ALLOCA:%.*]] = alloca [163840 x i32], align 4 110; CHECK-NEXT: call void @init(ptr [[ALLOCA]]) 111; CHECK-NEXT: [[START:%.*]] = getelementptr i8, ptr [[ALLOCA]], i64 2 112; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] 113; CHECK: vector.ph: 114; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] 115; CHECK: vector.body: 116; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[PRED_LOAD_CONTINUE2:%.*]] ] 117; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <2 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP15:%.*]], [[PRED_LOAD_CONTINUE2]] ] 118; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 0 119; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i8, ptr [[TEST_BASE:%.*]], i64 [[TMP0]] 120; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds i8, ptr [[TMP1]], i32 0 121; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <2 x i8>, ptr [[TMP2]], align 1 122; CHECK-NEXT: [[TMP3:%.*]] = icmp sge <2 x i8> [[WIDE_LOAD]], zeroinitializer 123; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i1> [[TMP3]], i32 0 124; CHECK-NEXT: br i1 [[TMP4]], label [[PRED_LOAD_IF:%.*]], label [[PRED_LOAD_CONTINUE:%.*]] 125; CHECK: pred.load.if: 126; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, ptr [[START]], i64 [[TMP0]] 127; CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 128; CHECK-NEXT: [[TMP7:%.*]] = insertelement <2 x i32> poison, i32 [[TMP6]], i32 0 129; CHECK-NEXT: br label [[PRED_LOAD_CONTINUE]] 130; CHECK: pred.load.continue: 131; CHECK-NEXT: [[TMP8:%.*]] = phi <2 x i32> [ poison, [[VECTOR_BODY]] ], [ [[TMP7]], [[PRED_LOAD_IF]] ] 132; CHECK-NEXT: [[TMP9:%.*]] = extractelement <2 x i1> [[TMP3]], i32 1 133; CHECK-NEXT: br i1 [[TMP9]], label [[PRED_LOAD_IF1:%.*]], label [[PRED_LOAD_CONTINUE2]] 134; CHECK: pred.load.if1: 135; CHECK-NEXT: [[TMP10:%.*]] = add i64 [[INDEX]], 1 136; CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds i32, ptr [[START]], i64 [[TMP10]] 137; CHECK-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP11]], align 4 138; CHECK-NEXT: [[TMP13:%.*]] = insertelement <2 x i32> [[TMP8]], i32 [[TMP12]], i32 1 139; CHECK-NEXT: br label [[PRED_LOAD_CONTINUE2]] 140; CHECK: pred.load.continue2: 141; CHECK-NEXT: [[TMP14:%.*]] = phi <2 x i32> [ [[TMP8]], [[PRED_LOAD_CONTINUE]] ], [ [[TMP13]], [[PRED_LOAD_IF1]] ] 142; CHECK-NEXT: [[PREDPHI:%.*]] = select <2 x i1> [[TMP3]], <2 x i32> [[TMP14]], <2 x i32> zeroinitializer 143; CHECK-NEXT: [[TMP15]] = add <2 x i32> [[VEC_PHI]], [[PREDPHI]] 144; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2 145; CHECK-NEXT: [[TMP16:%.*]] = icmp eq i64 [[INDEX_NEXT]], 4096 146; CHECK-NEXT: br i1 [[TMP16]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]] 147; CHECK: middle.block: 148; CHECK-NEXT: [[TMP17:%.*]] = call i32 @llvm.vector.reduce.add.v2i32(<2 x i32> [[TMP15]]) 149; CHECK-NEXT: br i1 true, label [[LOOP_EXIT:%.*]], label [[SCALAR_PH]] 150; CHECK: scalar.ph: 151; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ 4096, [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ] 152; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP17]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY]] ] 153; CHECK-NEXT: br label [[LOOP:%.*]] 154; CHECK: loop: 155; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LATCH:%.*]] ] 156; CHECK-NEXT: [[ACCUM:%.*]] = phi i32 [ [[BC_MERGE_RDX]], [[SCALAR_PH]] ], [ [[ACCUM_NEXT:%.*]], [[LATCH]] ] 157; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1 158; CHECK-NEXT: [[TEST_ADDR:%.*]] = getelementptr inbounds i8, ptr [[TEST_BASE]], i64 [[IV]] 159; CHECK-NEXT: [[L_T:%.*]] = load i8, ptr [[TEST_ADDR]], align 1 160; CHECK-NEXT: [[CMP:%.*]] = icmp sge i8 [[L_T]], 0 161; CHECK-NEXT: br i1 [[CMP]], label [[PRED:%.*]], label [[LATCH]] 162; CHECK: pred: 163; CHECK-NEXT: [[ADDR:%.*]] = getelementptr inbounds i32, ptr [[START]], i64 [[IV]] 164; CHECK-NEXT: [[VAL:%.*]] = load i32, ptr [[ADDR]], align 4 165; CHECK-NEXT: br label [[LATCH]] 166; CHECK: latch: 167; CHECK-NEXT: [[VAL_PHI:%.*]] = phi i32 [ 0, [[LOOP]] ], [ [[VAL]], [[PRED]] ] 168; CHECK-NEXT: [[ACCUM_NEXT]] = add i32 [[ACCUM]], [[VAL_PHI]] 169; CHECK-NEXT: [[EXIT:%.*]] = icmp eq i64 [[IV]], 4095 170; CHECK-NEXT: br i1 [[EXIT]], label [[LOOP_EXIT]], label [[LOOP]], !llvm.loop [[LOOP5:![0-9]+]] 171; CHECK: loop_exit: 172; CHECK-NEXT: [[ACCUM_NEXT_LCSSA:%.*]] = phi i32 [ [[ACCUM_NEXT]], [[LATCH]] ], [ [[TMP17]], [[MIDDLE_BLOCK]] ] 173; CHECK-NEXT: ret i32 [[ACCUM_NEXT_LCSSA]] 174; 175entry: 176 %alloca = alloca [163840 x i32], align 4 177 call void @init(ptr %alloca) 178 %start = getelementptr i8, ptr %alloca, i64 2 179 br label %loop 180loop: 181 %iv = phi i64 [ 0, %entry ], [ %iv.next, %latch ] 182 %accum = phi i32 [ 0, %entry ], [ %accum.next, %latch ] 183 %iv.next = add i64 %iv, 1 184 %test_addr = getelementptr inbounds i8, ptr %test_base, i64 %iv 185 %l.t = load i8, ptr %test_addr 186 %cmp = icmp sge i8 %l.t, 0 187 br i1 %cmp, label %pred, label %latch 188pred: 189 %addr = getelementptr inbounds i32, ptr %start, i64 %iv 190 %val = load i32, ptr %addr, align 4 191 br label %latch 192latch: 193 %val.phi = phi i32 [0, %loop], [%val, %pred] 194 %accum.next = add i32 %accum, %val.phi 195 %exit = icmp eq i64 %iv, 4095 196 br i1 %exit, label %loop_exit, label %loop 197 198loop_exit: 199 ret i32 %accum.next 200} 201 202 203define i32 @loop_requires_scev_predicate(ptr %dest, i32 %end) { 204; CHECK-LABEL: @loop_requires_scev_predicate( 205; CHECK-NEXT: entry: 206; CHECK-NEXT: [[P1:%.*]] = alloca [1024 x i32], align 4 207; CHECK-NEXT: [[P2:%.*]] = alloca [1024 x i32], align 4 208; CHECK-NEXT: call void @init(ptr [[P1]]) 209; CHECK-NEXT: call void @init(ptr [[P2]]) 210; CHECK-NEXT: [[END_CLAMPED:%.*]] = and i32 [[END:%.*]], 1023 211; CHECK-NEXT: [[TMP0:%.*]] = trunc i32 [[END]] to i10 212; CHECK-NEXT: [[TMP1:%.*]] = zext i10 [[TMP0]] to i64 213; CHECK-NEXT: [[UMAX1:%.*]] = call i64 @llvm.umax.i64(i64 [[TMP1]], i64 1) 214; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[UMAX1]], 2 215; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_SCEVCHECK:%.*]] 216; CHECK: vector.scevcheck: 217; CHECK-NEXT: [[UMAX:%.*]] = call i32 @llvm.umax.i32(i32 [[END_CLAMPED]], i32 1) 218; CHECK-NEXT: [[TMP2:%.*]] = add nsw i32 [[UMAX]], -1 219; CHECK-NEXT: [[TMP3:%.*]] = trunc i32 [[TMP2]] to i8 220; CHECK-NEXT: [[TMP4:%.*]] = add i8 1, [[TMP3]] 221; CHECK-NEXT: [[TMP5:%.*]] = icmp ult i8 [[TMP4]], 1 222; CHECK-NEXT: [[TMP6:%.*]] = icmp ugt i32 [[TMP2]], 255 223; CHECK-NEXT: [[TMP7:%.*]] = or i1 [[TMP5]], [[TMP6]] 224; CHECK-NEXT: br i1 [[TMP7]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]] 225; CHECK: vector.ph: 226; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[UMAX1]], 2 227; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[UMAX1]], [[N_MOD_VF]] 228; CHECK-NEXT: [[IND_END:%.*]] = trunc i64 [[N_VEC]] to i8 229; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] 230; CHECK: vector.body: 231; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[PRED_STORE_CONTINUE4:%.*]] ] 232; CHECK-NEXT: [[TMP8:%.*]] = add i64 [[INDEX]], 0 233; CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds i32, ptr [[P1]], i64 [[TMP8]] 234; CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds i32, ptr [[TMP9]], i32 0 235; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <2 x i32>, ptr [[TMP10]], align 4 236; CHECK-NEXT: [[TMP11:%.*]] = icmp ne <2 x i32> [[WIDE_LOAD]], zeroinitializer 237; CHECK-NEXT: [[TMP12:%.*]] = getelementptr i32, ptr [[P2]], i64 [[TMP8]] 238; CHECK-NEXT: [[TMP13:%.*]] = getelementptr i32, ptr [[TMP12]], i32 0 239; CHECK-NEXT: [[WIDE_LOAD3:%.*]] = load <2 x i32>, ptr [[TMP13]], align 4 240; CHECK-NEXT: [[TMP14:%.*]] = extractelement <2 x i1> [[TMP11]], i32 0 241; CHECK-NEXT: br i1 [[TMP14]], label [[PRED_STORE_IF:%.*]], label [[PRED_STORE_CONTINUE:%.*]] 242; CHECK: pred.store.if: 243; CHECK-NEXT: [[TMP15:%.*]] = getelementptr inbounds i32, ptr [[DEST:%.*]], i64 [[TMP8]] 244; CHECK-NEXT: [[TMP16:%.*]] = extractelement <2 x i32> [[WIDE_LOAD]], i32 0 245; CHECK-NEXT: [[TMP17:%.*]] = extractelement <2 x i32> [[WIDE_LOAD3]], i32 0 246; CHECK-NEXT: [[TMP18:%.*]] = add i32 [[TMP16]], [[TMP17]] 247; CHECK-NEXT: store i32 [[TMP18]], ptr [[TMP15]], align 4 248; CHECK-NEXT: br label [[PRED_STORE_CONTINUE]] 249; CHECK: pred.store.continue: 250; CHECK-NEXT: [[TMP19:%.*]] = extractelement <2 x i1> [[TMP11]], i32 1 251; CHECK-NEXT: br i1 [[TMP19]], label [[PRED_STORE_IF3:%.*]], label [[PRED_STORE_CONTINUE4]] 252; CHECK: pred.store.if3: 253; CHECK-NEXT: [[TMP20:%.*]] = add i64 [[INDEX]], 1 254; CHECK-NEXT: [[TMP21:%.*]] = getelementptr inbounds i32, ptr [[DEST]], i64 [[TMP20]] 255; CHECK-NEXT: [[TMP22:%.*]] = extractelement <2 x i32> [[WIDE_LOAD]], i32 1 256; CHECK-NEXT: [[TMP23:%.*]] = extractelement <2 x i32> [[WIDE_LOAD3]], i32 1 257; CHECK-NEXT: [[TMP24:%.*]] = add i32 [[TMP22]], [[TMP23]] 258; CHECK-NEXT: store i32 [[TMP24]], ptr [[TMP21]], align 4 259; CHECK-NEXT: br label [[PRED_STORE_CONTINUE4]] 260; CHECK: pred.store.continue4: 261; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2 262; CHECK-NEXT: [[TMP25:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] 263; CHECK-NEXT: br i1 [[TMP25]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]] 264; CHECK: middle.block: 265; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[UMAX1]], [[N_VEC]] 266; CHECK-NEXT: br i1 [[CMP_N]], label [[EXIT:%.*]], label [[SCALAR_PH]] 267; CHECK: scalar.ph: 268; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i8 [ [[IND_END]], [[MIDDLE_BLOCK]] ], [ 0, [[VECTOR_SCEVCHECK]] ], [ 0, [[ENTRY:%.*]] ] 269; CHECK-NEXT: [[BC_RESUME_VAL2:%.*]] = phi i64 [ [[N_VEC]], [[MIDDLE_BLOCK]] ], [ 0, [[VECTOR_SCEVCHECK]] ], [ 0, [[ENTRY]] ] 270; CHECK-NEXT: br label [[FOR_BODY:%.*]] 271; CHECK: for.body: 272; CHECK-NEXT: [[IND:%.*]] = phi i8 [ [[IND_NEXT:%.*]], [[FOR_INC:%.*]] ], [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ] 273; CHECK-NEXT: [[GEP_IND:%.*]] = phi i64 [ [[GEP_IND_NEXT:%.*]], [[FOR_INC]] ], [ [[BC_RESUME_VAL2]], [[SCALAR_PH]] ] 274; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[P1]], i64 [[GEP_IND]] 275; CHECK-NEXT: [[TMP26:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 276; CHECK-NEXT: [[DOWORK:%.*]] = icmp ne i32 [[TMP26]], 0 277; CHECK-NEXT: br i1 [[DOWORK]], label [[FOR_DOWORK:%.*]], label [[FOR_INC]] 278; CHECK: for.dowork: 279; CHECK-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds i32, ptr [[P2]], i64 [[GEP_IND]] 280; CHECK-NEXT: [[TMP27:%.*]] = load i32, ptr [[ARRAYIDX3]], align 4 281; CHECK-NEXT: [[ADD:%.*]] = add i32 [[TMP26]], [[TMP27]] 282; CHECK-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i32, ptr [[DEST]], i64 [[GEP_IND]] 283; CHECK-NEXT: store i32 [[ADD]], ptr [[ARRAYIDX5]], align 4 284; CHECK-NEXT: br label [[FOR_INC]] 285; CHECK: for.inc: 286; CHECK-NEXT: [[IND_NEXT]] = add i8 [[IND]], 1 287; CHECK-NEXT: [[CONV:%.*]] = zext i8 [[IND_NEXT]] to i32 288; CHECK-NEXT: [[GEP_IND_NEXT]] = add i64 [[GEP_IND]], 1 289; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[CONV]], [[END_CLAMPED]] 290; CHECK-NEXT: br i1 [[CMP]], label [[FOR_BODY]], label [[EXIT]], !llvm.loop [[LOOP9:![0-9]+]] 291; CHECK: exit: 292; CHECK-NEXT: ret i32 0 293; 294entry: 295 %p1 = alloca [1024 x i32] 296 %p2 = alloca [1024 x i32] 297 call void @init(ptr %p1) 298 call void @init(ptr %p2) 299 %end.clamped = and i32 %end, 1023 300 br label %for.body 301 302for.body: 303 %ind = phi i8 [ %ind.next, %for.inc ], [ 0, %entry ] 304 %gep.ind = phi i64 [ %gep.ind.next, %for.inc ], [ 0, %entry ] 305 %arrayidx = getelementptr inbounds i32, ptr %p1, i64 %gep.ind 306 %0 = load i32, ptr %arrayidx, align 4 307 %dowork = icmp ne i32 %0, 0 308 br i1 %dowork, label %for.dowork, label %for.inc 309 310for.dowork: 311 %arrayidx3 = getelementptr inbounds i32, ptr %p2, i64 %gep.ind 312 %1 = load i32, ptr %arrayidx3, align 4 313 %add = add i32 %0, %1 314 %arrayidx5 = getelementptr inbounds i32, ptr %dest, i64 %gep.ind 315 store i32 %add, ptr %arrayidx5, align 4 316 br label %for.inc 317 318for.inc: 319 %ind.next = add i8 %ind, 1 320 %conv = zext i8 %ind.next to i32 321 %gep.ind.next = add i64 %gep.ind, 1 322 %cmp = icmp ult i32 %conv, %end.clamped 323 br i1 %cmp, label %for.body, label %exit 324 325exit: 326 ret i32 0 327} 328 329 330; Test reverse loops where we should be able to prove loads in predicated blocks 331; are safe to load unconditionally. 332define void @test_rev_loops_deref_loads(ptr nocapture noundef writeonly %dest) { 333; CHECK-LABEL: @test_rev_loops_deref_loads( 334; CHECK-NEXT: entry: 335; CHECK-NEXT: [[LOCAL_DEST:%.*]] = alloca [1024 x i32], align 4 336; CHECK-NEXT: [[LOCAL_SRC:%.*]] = alloca [1024 x i32], align 4 337; CHECK-NEXT: [[LOCAL_CMP:%.*]] = alloca [1024 x i32], align 4 338; CHECK-NEXT: call void @init(ptr [[LOCAL_SRC]]) 339; CHECK-NEXT: call void @init(ptr [[LOCAL_CMP]]) 340; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] 341; CHECK: vector.ph: 342; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] 343; CHECK: vector.body: 344; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[PRED_STORE_CONTINUE4:%.*]] ] 345; CHECK-NEXT: [[OFFSET_IDX:%.*]] = sub i64 1023, [[INDEX]] 346; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[OFFSET_IDX]], 0 347; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1024 x i32], ptr [[LOCAL_CMP]], i64 0, i64 [[TMP0]] 348; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 0 349; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[TMP2]], i32 -1 350; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <2 x i32>, ptr [[TMP3]], align 4 351; CHECK-NEXT: [[REVERSE:%.*]] = shufflevector <2 x i32> [[WIDE_LOAD]], <2 x i32> poison, <2 x i32> <i32 1, i32 0> 352; CHECK-NEXT: [[TMP4:%.*]] = icmp eq <2 x i32> [[REVERSE]], splat (i32 3) 353; CHECK-NEXT: [[TMP5:%.*]] = xor <2 x i1> [[TMP4]], splat (i1 true) 354; CHECK-NEXT: [[TMP6:%.*]] = getelementptr [1024 x i32], ptr [[LOCAL_SRC]], i64 0, i64 [[TMP0]] 355; CHECK-NEXT: [[TMP7:%.*]] = getelementptr i32, ptr [[TMP6]], i32 0 356; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i32, ptr [[TMP7]], i32 -1 357; CHECK-NEXT: [[WIDE_LOAD1:%.*]] = load <2 x i32>, ptr [[TMP8]], align 4 358; CHECK-NEXT: [[REVERSE2:%.*]] = shufflevector <2 x i32> [[WIDE_LOAD1]], <2 x i32> poison, <2 x i32> <i32 1, i32 0> 359; CHECK-NEXT: [[TMP9:%.*]] = extractelement <2 x i1> [[TMP5]], i32 0 360; CHECK-NEXT: br i1 [[TMP9]], label [[PRED_STORE_IF:%.*]], label [[PRED_STORE_CONTINUE:%.*]] 361; CHECK: pred.store.if: 362; CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds [1024 x i32], ptr [[LOCAL_DEST]], i64 0, i64 [[TMP0]] 363; CHECK-NEXT: [[TMP11:%.*]] = extractelement <2 x i32> [[REVERSE2]], i32 0 364; CHECK-NEXT: [[TMP12:%.*]] = shl nsw i32 [[TMP11]], 2 365; CHECK-NEXT: store i32 [[TMP12]], ptr [[TMP10]], align 4 366; CHECK-NEXT: br label [[PRED_STORE_CONTINUE]] 367; CHECK: pred.store.continue: 368; CHECK-NEXT: [[TMP13:%.*]] = extractelement <2 x i1> [[TMP5]], i32 1 369; CHECK-NEXT: br i1 [[TMP13]], label [[PRED_STORE_IF3:%.*]], label [[PRED_STORE_CONTINUE4]] 370; CHECK: pred.store.if3: 371; CHECK-NEXT: [[TMP14:%.*]] = add i64 [[OFFSET_IDX]], -1 372; CHECK-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1024 x i32], ptr [[LOCAL_DEST]], i64 0, i64 [[TMP14]] 373; CHECK-NEXT: [[TMP16:%.*]] = extractelement <2 x i32> [[REVERSE2]], i32 1 374; CHECK-NEXT: [[TMP17:%.*]] = shl nsw i32 [[TMP16]], 2 375; CHECK-NEXT: store i32 [[TMP17]], ptr [[TMP15]], align 4 376; CHECK-NEXT: br label [[PRED_STORE_CONTINUE4]] 377; CHECK: pred.store.continue4: 378; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2 379; CHECK-NEXT: [[TMP18:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1024 380; CHECK-NEXT: br i1 [[TMP18]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP10:![0-9]+]] 381; CHECK: middle.block: 382; CHECK-NEXT: br i1 true, label [[EXIT:%.*]], label [[SCALAR_PH]] 383; CHECK: scalar.ph: 384; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ -1, [[MIDDLE_BLOCK]] ], [ 1023, [[ENTRY:%.*]] ] 385; CHECK-NEXT: br label [[FOR_BODY:%.*]] 386; CHECK: for.body: 387; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[FOR_INC:%.*]] ] 388; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1024 x i32], ptr [[LOCAL_CMP]], i64 0, i64 [[IV]] 389; CHECK-NEXT: [[TMP19:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 390; CHECK-NEXT: [[CMP3_NOT:%.*]] = icmp eq i32 [[TMP19]], 3 391; CHECK-NEXT: br i1 [[CMP3_NOT]], label [[FOR_INC]], label [[IF_THEN:%.*]] 392; CHECK: if.then: 393; CHECK-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [1024 x i32], ptr [[LOCAL_SRC]], i64 0, i64 [[IV]] 394; CHECK-NEXT: [[TMP20:%.*]] = load i32, ptr [[ARRAYIDX5]], align 4 395; CHECK-NEXT: [[MUL:%.*]] = shl nsw i32 [[TMP20]], 2 396; CHECK-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [1024 x i32], ptr [[LOCAL_DEST]], i64 0, i64 [[IV]] 397; CHECK-NEXT: store i32 [[MUL]], ptr [[ARRAYIDX7]], align 4 398; CHECK-NEXT: br label [[FOR_INC]] 399; CHECK: for.inc: 400; CHECK-NEXT: [[IV_NEXT]] = add nsw i64 [[IV]], -1 401; CHECK-NEXT: [[CMP2_NOT:%.*]] = icmp eq i64 [[IV]], 0 402; CHECK-NEXT: br i1 [[CMP2_NOT]], label [[EXIT]], label [[FOR_BODY]], !llvm.loop [[LOOP11:![0-9]+]] 403; CHECK: exit: 404; CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr [[DEST:%.*]], ptr [[LOCAL_DEST]], i64 1024, i1 false) 405; CHECK-NEXT: ret void 406; 407entry: 408 %local_dest = alloca [1024 x i32], align 4 409 %local_src = alloca [1024 x i32], align 4 410 %local_cmp = alloca [1024 x i32], align 4 411 call void @init(ptr %local_src) 412 call void @init(ptr %local_cmp) 413 br label %for.body 414 415for.body: 416 %iv = phi i64 [ 1023, %entry ], [ %iv.next, %for.inc ] 417 %arrayidx = getelementptr inbounds [1024 x i32], ptr %local_cmp, i64 0, i64 %iv 418 %0 = load i32, ptr %arrayidx, align 4 419 %cmp3.not = icmp eq i32 %0, 3 420 br i1 %cmp3.not, label %for.inc, label %if.then 421 422if.then: 423 %arrayidx5 = getelementptr inbounds [1024 x i32], ptr %local_src, i64 0, i64 %iv 424 %1 = load i32, ptr %arrayidx5, align 4 425 %mul = shl nsw i32 %1, 2 426 %arrayidx7 = getelementptr inbounds [1024 x i32], ptr %local_dest, i64 0, i64 %iv 427 store i32 %mul, ptr %arrayidx7, align 4 428 br label %for.inc 429 430for.inc: 431 %iv.next = add nsw i64 %iv, -1 432 %cmp2.not = icmp eq i64 %iv, 0 433 br i1 %cmp2.not, label %exit, label %for.body 434 435exit: 436 call void @llvm.memcpy.p0.p0.i64(ptr %dest, ptr %local_dest, i64 1024, i1 false) 437 ret void 438} 439 440 441; Test reverse loops where we *cannot* prove loads in predicated blocks are safe 442; to load unconditionally. 443define void @test_rev_loops_non_deref_loads(ptr nocapture noundef writeonly %dest) { 444; CHECK-LABEL: @test_rev_loops_non_deref_loads( 445; CHECK-NEXT: entry: 446; CHECK-NEXT: [[LOCAL_DEST:%.*]] = alloca [1024 x i32], align 4 447; CHECK-NEXT: [[LOCAL_SRC:%.*]] = alloca [1024 x i32], align 4 448; CHECK-NEXT: [[LOCAL_CMP:%.*]] = alloca [1024 x i32], align 4 449; CHECK-NEXT: call void @init(ptr [[LOCAL_SRC]]) 450; CHECK-NEXT: call void @init(ptr [[LOCAL_CMP]]) 451; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] 452; CHECK: vector.ph: 453; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] 454; CHECK: vector.body: 455; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[PRED_STORE_CONTINUE2:%.*]] ] 456; CHECK-NEXT: [[VEC_IND:%.*]] = phi <2 x i64> [ <i64 1023, i64 1022>, [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[PRED_STORE_CONTINUE2]] ] 457; CHECK-NEXT: [[TMP0:%.*]] = add <2 x i64> [[VEC_IND]], splat (i64 -1) 458; CHECK-NEXT: [[TMP1:%.*]] = extractelement <2 x i64> [[TMP0]], i32 0 459; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1024 x i32], ptr [[LOCAL_CMP]], i64 0, i64 [[TMP1]] 460; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[TMP2]], i32 0 461; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[TMP3]], i32 -1 462; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <2 x i32>, ptr [[TMP4]], align 4 463; CHECK-NEXT: [[REVERSE:%.*]] = shufflevector <2 x i32> [[WIDE_LOAD]], <2 x i32> poison, <2 x i32> <i32 1, i32 0> 464; CHECK-NEXT: [[TMP5:%.*]] = icmp eq <2 x i32> [[REVERSE]], splat (i32 3) 465; CHECK-NEXT: [[TMP6:%.*]] = xor <2 x i1> [[TMP5]], splat (i1 true) 466; CHECK-NEXT: [[TMP7:%.*]] = extractelement <2 x i1> [[TMP6]], i32 0 467; CHECK-NEXT: br i1 [[TMP7]], label [[PRED_STORE_IF:%.*]], label [[PRED_STORE_CONTINUE:%.*]] 468; CHECK: pred.store.if: 469; CHECK-NEXT: [[TMP8:%.*]] = extractelement <2 x i64> [[TMP0]], i32 0 470; CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1024 x i32], ptr [[LOCAL_SRC]], i64 0, i64 [[TMP8]] 471; CHECK-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4 472; CHECK-NEXT: [[TMP11:%.*]] = extractelement <2 x i64> [[TMP0]], i32 0 473; CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds [1024 x i32], ptr [[LOCAL_DEST]], i64 0, i64 [[TMP11]] 474; CHECK-NEXT: [[TMP13:%.*]] = shl nsw i32 [[TMP10]], 2 475; CHECK-NEXT: store i32 [[TMP13]], ptr [[TMP12]], align 4 476; CHECK-NEXT: br label [[PRED_STORE_CONTINUE]] 477; CHECK: pred.store.continue: 478; CHECK-NEXT: [[TMP14:%.*]] = extractelement <2 x i1> [[TMP6]], i32 1 479; CHECK-NEXT: br i1 [[TMP14]], label [[PRED_STORE_IF1:%.*]], label [[PRED_STORE_CONTINUE2]] 480; CHECK: pred.store.if1: 481; CHECK-NEXT: [[TMP15:%.*]] = extractelement <2 x i64> [[TMP0]], i32 1 482; CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1024 x i32], ptr [[LOCAL_SRC]], i64 0, i64 [[TMP15]] 483; CHECK-NEXT: [[TMP17:%.*]] = load i32, ptr [[TMP16]], align 4 484; CHECK-NEXT: [[TMP18:%.*]] = extractelement <2 x i64> [[TMP0]], i32 1 485; CHECK-NEXT: [[TMP19:%.*]] = getelementptr inbounds [1024 x i32], ptr [[LOCAL_DEST]], i64 0, i64 [[TMP18]] 486; CHECK-NEXT: [[TMP20:%.*]] = shl nsw i32 [[TMP17]], 2 487; CHECK-NEXT: store i32 [[TMP20]], ptr [[TMP19]], align 4 488; CHECK-NEXT: br label [[PRED_STORE_CONTINUE2]] 489; CHECK: pred.store.continue2: 490; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2 491; CHECK-NEXT: [[VEC_IND_NEXT]] = add <2 x i64> [[VEC_IND]], splat (i64 -2) 492; CHECK-NEXT: [[TMP21:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1024 493; CHECK-NEXT: br i1 [[TMP21]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP12:![0-9]+]] 494; CHECK: middle.block: 495; CHECK-NEXT: br i1 true, label [[EXIT:%.*]], label [[SCALAR_PH]] 496; CHECK: scalar.ph: 497; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ -1, [[MIDDLE_BLOCK]] ], [ 1023, [[ENTRY:%.*]] ] 498; CHECK-NEXT: br label [[FOR_BODY:%.*]] 499; CHECK: for.body: 500; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[FOR_INC:%.*]] ] 501; CHECK-NEXT: [[OFF:%.*]] = add i64 [[IV]], -1 502; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1024 x i32], ptr [[LOCAL_CMP]], i64 0, i64 [[OFF]] 503; CHECK-NEXT: [[TMP22:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 504; CHECK-NEXT: [[CMP3_NOT:%.*]] = icmp eq i32 [[TMP22]], 3 505; CHECK-NEXT: br i1 [[CMP3_NOT]], label [[FOR_INC]], label [[IF_THEN:%.*]] 506; CHECK: if.then: 507; CHECK-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [1024 x i32], ptr [[LOCAL_SRC]], i64 0, i64 [[OFF]] 508; CHECK-NEXT: [[TMP23:%.*]] = load i32, ptr [[ARRAYIDX5]], align 4 509; CHECK-NEXT: [[MUL:%.*]] = shl nsw i32 [[TMP23]], 2 510; CHECK-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [1024 x i32], ptr [[LOCAL_DEST]], i64 0, i64 [[OFF]] 511; CHECK-NEXT: store i32 [[MUL]], ptr [[ARRAYIDX7]], align 4 512; CHECK-NEXT: br label [[FOR_INC]] 513; CHECK: for.inc: 514; CHECK-NEXT: [[IV_NEXT]] = add nsw i64 [[IV]], -1 515; CHECK-NEXT: [[CMP2_NOT:%.*]] = icmp eq i64 [[IV]], 0 516; CHECK-NEXT: br i1 [[CMP2_NOT]], label [[EXIT]], label [[FOR_BODY]], !llvm.loop [[LOOP13:![0-9]+]] 517; CHECK: exit: 518; CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr [[DEST:%.*]], ptr [[LOCAL_DEST]], i64 1024, i1 false) 519; CHECK-NEXT: ret void 520; 521entry: 522 %local_dest = alloca [1024 x i32], align 4 523 %local_src = alloca [1024 x i32], align 4 524 %local_cmp = alloca [1024 x i32], align 4 525 call void @init(ptr %local_src) 526 call void @init(ptr %local_cmp) 527 br label %for.body 528 529for.body: 530 %iv = phi i64 [ 1023, %entry ], [ %iv.next, %for.inc ] 531 %off = add i64 %iv, -1 532 %arrayidx = getelementptr inbounds [1024 x i32], ptr %local_cmp, i64 0, i64 %off 533 %0 = load i32, ptr %arrayidx, align 4 534 %cmp3.not = icmp eq i32 %0, 3 535 br i1 %cmp3.not, label %for.inc, label %if.then 536 537if.then: 538 %arrayidx5 = getelementptr inbounds [1024 x i32], ptr %local_src, i64 0, i64 %off 539 %1 = load i32, ptr %arrayidx5, align 4 540 %mul = shl nsw i32 %1, 2 541 %arrayidx7 = getelementptr inbounds [1024 x i32], ptr %local_dest, i64 0, i64 %off 542 store i32 %mul, ptr %arrayidx7, align 4 543 br label %for.inc 544 545for.inc: 546 %iv.next = add nsw i64 %iv, -1 547 %cmp2.not = icmp eq i64 %iv, 0 548 br i1 %cmp2.not, label %exit, label %for.body 549 550exit: 551 call void @llvm.memcpy.p0.p0.i64(ptr %dest, ptr %local_dest, i64 1024, i1 false) 552 ret void 553} 554 555 556; Test a loop with a positive step recurrence that has a strided access 557define i16 @test_strided_access(i64 %len, ptr %test_base) { 558; CHECK-LABEL: @test_strided_access( 559; CHECK-NEXT: entry: 560; CHECK-NEXT: [[ALLOCA:%.*]] = alloca [163840 x i16], align 4 561; CHECK-NEXT: call void @init(ptr [[ALLOCA]]) 562; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] 563; CHECK: vector.ph: 564; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] 565; CHECK: vector.body: 566; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] 567; CHECK-NEXT: [[VEC_IND:%.*]] = phi <2 x i64> [ <i64 0, i64 1>, [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[VECTOR_BODY]] ] 568; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <2 x i16> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP13:%.*]], [[VECTOR_BODY]] ] 569; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 0 570; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i8, ptr [[TEST_BASE:%.*]], i64 [[TMP0]] 571; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds i8, ptr [[TMP1]], i32 0 572; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <2 x i8>, ptr [[TMP2]], align 1 573; CHECK-NEXT: [[TMP3:%.*]] = icmp sge <2 x i8> [[WIDE_LOAD]], zeroinitializer 574; CHECK-NEXT: [[TMP4:%.*]] = mul <2 x i64> [[VEC_IND]], splat (i64 2) 575; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x i64> [[TMP4]], i32 0 576; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds i16, ptr [[ALLOCA]], i64 [[TMP5]] 577; CHECK-NEXT: [[TMP7:%.*]] = extractelement <2 x i64> [[TMP4]], i32 1 578; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds i16, ptr [[ALLOCA]], i64 [[TMP7]] 579; CHECK-NEXT: [[TMP9:%.*]] = load i16, ptr [[TMP6]], align 2 580; CHECK-NEXT: [[TMP10:%.*]] = load i16, ptr [[TMP8]], align 2 581; CHECK-NEXT: [[TMP11:%.*]] = insertelement <2 x i16> poison, i16 [[TMP9]], i32 0 582; CHECK-NEXT: [[TMP12:%.*]] = insertelement <2 x i16> [[TMP11]], i16 [[TMP10]], i32 1 583; CHECK-NEXT: [[PREDPHI:%.*]] = select <2 x i1> [[TMP3]], <2 x i16> [[TMP12]], <2 x i16> zeroinitializer 584; CHECK-NEXT: [[TMP13]] = add <2 x i16> [[VEC_PHI]], [[PREDPHI]] 585; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2 586; CHECK-NEXT: [[VEC_IND_NEXT]] = add <2 x i64> [[VEC_IND]], splat (i64 2) 587; CHECK-NEXT: [[TMP14:%.*]] = icmp eq i64 [[INDEX_NEXT]], 4096 588; CHECK-NEXT: br i1 [[TMP14]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP14:![0-9]+]] 589; CHECK: middle.block: 590; CHECK-NEXT: [[TMP15:%.*]] = call i16 @llvm.vector.reduce.add.v2i16(<2 x i16> [[TMP13]]) 591; CHECK-NEXT: br i1 true, label [[LOOP_EXIT:%.*]], label [[SCALAR_PH]] 592; CHECK: scalar.ph: 593; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ 4096, [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ] 594; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i16 [ [[TMP15]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY]] ] 595; CHECK-NEXT: br label [[LOOP:%.*]] 596; CHECK: loop: 597; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LATCH:%.*]] ] 598; CHECK-NEXT: [[ACCUM:%.*]] = phi i16 [ [[BC_MERGE_RDX]], [[SCALAR_PH]] ], [ [[ACCUM_NEXT:%.*]], [[LATCH]] ] 599; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1 600; CHECK-NEXT: [[TEST_ADDR:%.*]] = getelementptr inbounds i8, ptr [[TEST_BASE]], i64 [[IV]] 601; CHECK-NEXT: [[L_T:%.*]] = load i8, ptr [[TEST_ADDR]], align 1 602; CHECK-NEXT: [[CMP:%.*]] = icmp sge i8 [[L_T]], 0 603; CHECK-NEXT: br i1 [[CMP]], label [[PRED:%.*]], label [[LATCH]] 604; CHECK: pred: 605; CHECK-NEXT: [[IV_STRIDE:%.*]] = mul i64 [[IV]], 2 606; CHECK-NEXT: [[ADDR:%.*]] = getelementptr inbounds i16, ptr [[ALLOCA]], i64 [[IV_STRIDE]] 607; CHECK-NEXT: [[VAL:%.*]] = load i16, ptr [[ADDR]], align 2 608; CHECK-NEXT: br label [[LATCH]] 609; CHECK: latch: 610; CHECK-NEXT: [[VAL_PHI:%.*]] = phi i16 [ 0, [[LOOP]] ], [ [[VAL]], [[PRED]] ] 611; CHECK-NEXT: [[ACCUM_NEXT]] = add i16 [[ACCUM]], [[VAL_PHI]] 612; CHECK-NEXT: [[EXIT:%.*]] = icmp eq i64 [[IV]], 4095 613; CHECK-NEXT: br i1 [[EXIT]], label [[LOOP_EXIT]], label [[LOOP]], !llvm.loop [[LOOP15:![0-9]+]] 614; CHECK: loop_exit: 615; CHECK-NEXT: [[ACCUM_NEXT_LCSSA:%.*]] = phi i16 [ [[ACCUM_NEXT]], [[LATCH]] ], [ [[TMP15]], [[MIDDLE_BLOCK]] ] 616; CHECK-NEXT: ret i16 [[ACCUM_NEXT_LCSSA]] 617; 618entry: 619 %alloca = alloca [163840 x i16], align 4 620 call void @init(ptr %alloca) 621 br label %loop 622loop: 623 %iv = phi i64 [ 0, %entry ], [ %iv.next, %latch ] 624 %accum = phi i16 [ 0, %entry ], [ %accum.next, %latch ] 625 %iv.next = add i64 %iv, 1 626 %test_addr = getelementptr inbounds i8, ptr %test_base, i64 %iv 627 %l.t = load i8, ptr %test_addr 628 %cmp = icmp sge i8 %l.t, 0 629 br i1 %cmp, label %pred, label %latch 630pred: 631 %iv.stride = mul i64 %iv, 2 632 %addr = getelementptr inbounds i16, ptr %alloca, i64 %iv.stride 633 %val = load i16, ptr %addr, align 2 634 br label %latch 635latch: 636 %val.phi = phi i16 [0, %loop], [%val, %pred] 637 %accum.next = add i16 %accum, %val.phi 638 %exit = icmp eq i64 %iv, 4095 639 br i1 %exit, label %loop_exit, label %loop 640 641loop_exit: 642 ret i16 %accum.next 643} 644 645 646; Test a loop with a negative step recurrence that has a strided access 647define void @test_rev_loops_strided_deref_loads(ptr nocapture noundef writeonly %dest) { 648; CHECK-LABEL: @test_rev_loops_strided_deref_loads( 649; CHECK-NEXT: entry: 650; CHECK-NEXT: [[LOCAL_DEST:%.*]] = alloca [1024 x i32], align 4 651; CHECK-NEXT: [[LOCAL_SRC:%.*]] = alloca [1024 x i32], align 4 652; CHECK-NEXT: [[LOCAL_CMP:%.*]] = alloca [1024 x i32], align 4 653; CHECK-NEXT: call void @init(ptr [[LOCAL_SRC]]) 654; CHECK-NEXT: call void @init(ptr [[LOCAL_CMP]]) 655; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] 656; CHECK: vector.ph: 657; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] 658; CHECK: vector.body: 659; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[PRED_STORE_CONTINUE2:%.*]] ] 660; CHECK-NEXT: [[VEC_IND:%.*]] = phi <2 x i64> [ <i64 511, i64 510>, [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[PRED_STORE_CONTINUE2]] ] 661; CHECK-NEXT: [[OFFSET_IDX:%.*]] = sub i64 511, [[INDEX]] 662; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[OFFSET_IDX]], 0 663; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1024 x i32], ptr [[LOCAL_CMP]], i64 0, i64 [[TMP0]] 664; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 0 665; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[TMP2]], i32 -1 666; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <2 x i32>, ptr [[TMP3]], align 4 667; CHECK-NEXT: [[REVERSE:%.*]] = shufflevector <2 x i32> [[WIDE_LOAD]], <2 x i32> poison, <2 x i32> <i32 1, i32 0> 668; CHECK-NEXT: [[TMP4:%.*]] = icmp eq <2 x i32> [[REVERSE]], splat (i32 3) 669; CHECK-NEXT: [[TMP5:%.*]] = xor <2 x i1> [[TMP4]], splat (i1 true) 670; CHECK-NEXT: [[TMP6:%.*]] = mul <2 x i64> [[VEC_IND]], splat (i64 2) 671; CHECK-NEXT: [[TMP7:%.*]] = extractelement <2 x i64> [[TMP6]], i32 0 672; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1024 x i32], ptr [[LOCAL_SRC]], i64 0, i64 [[TMP7]] 673; CHECK-NEXT: [[TMP9:%.*]] = extractelement <2 x i64> [[TMP6]], i32 1 674; CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds [1024 x i32], ptr [[LOCAL_SRC]], i64 0, i64 [[TMP9]] 675; CHECK-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP8]], align 4 676; CHECK-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP10]], align 4 677; CHECK-NEXT: [[TMP13:%.*]] = extractelement <2 x i1> [[TMP5]], i32 0 678; CHECK-NEXT: br i1 [[TMP13]], label [[PRED_STORE_IF:%.*]], label [[PRED_STORE_CONTINUE:%.*]] 679; CHECK: pred.store.if: 680; CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1024 x i32], ptr [[LOCAL_DEST]], i64 0, i64 [[TMP0]] 681; CHECK-NEXT: [[TMP15:%.*]] = shl nsw i32 [[TMP11]], 2 682; CHECK-NEXT: store i32 [[TMP15]], ptr [[TMP14]], align 4 683; CHECK-NEXT: br label [[PRED_STORE_CONTINUE]] 684; CHECK: pred.store.continue: 685; CHECK-NEXT: [[TMP16:%.*]] = extractelement <2 x i1> [[TMP5]], i32 1 686; CHECK-NEXT: br i1 [[TMP16]], label [[PRED_STORE_IF1:%.*]], label [[PRED_STORE_CONTINUE2]] 687; CHECK: pred.store.if1: 688; CHECK-NEXT: [[TMP17:%.*]] = add i64 [[OFFSET_IDX]], -1 689; CHECK-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1024 x i32], ptr [[LOCAL_DEST]], i64 0, i64 [[TMP17]] 690; CHECK-NEXT: [[TMP19:%.*]] = shl nsw i32 [[TMP12]], 2 691; CHECK-NEXT: store i32 [[TMP19]], ptr [[TMP18]], align 4 692; CHECK-NEXT: br label [[PRED_STORE_CONTINUE2]] 693; CHECK: pred.store.continue2: 694; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2 695; CHECK-NEXT: [[VEC_IND_NEXT]] = add <2 x i64> [[VEC_IND]], splat (i64 -2) 696; CHECK-NEXT: [[TMP20:%.*]] = icmp eq i64 [[INDEX_NEXT]], 512 697; CHECK-NEXT: br i1 [[TMP20]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP16:![0-9]+]] 698; CHECK: middle.block: 699; CHECK-NEXT: br i1 true, label [[EXIT:%.*]], label [[SCALAR_PH]] 700; CHECK: scalar.ph: 701; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ -1, [[MIDDLE_BLOCK]] ], [ 511, [[ENTRY:%.*]] ] 702; CHECK-NEXT: br label [[FOR_BODY:%.*]] 703; CHECK: for.body: 704; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[FOR_INC:%.*]] ] 705; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1024 x i32], ptr [[LOCAL_CMP]], i64 0, i64 [[IV]] 706; CHECK-NEXT: [[TMP21:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 707; CHECK-NEXT: [[CMP3_NOT:%.*]] = icmp eq i32 [[TMP21]], 3 708; CHECK-NEXT: br i1 [[CMP3_NOT]], label [[FOR_INC]], label [[IF_THEN:%.*]] 709; CHECK: if.then: 710; CHECK-NEXT: [[IV_STRIDED:%.*]] = mul i64 [[IV]], 2 711; CHECK-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [1024 x i32], ptr [[LOCAL_SRC]], i64 0, i64 [[IV_STRIDED]] 712; CHECK-NEXT: [[TMP22:%.*]] = load i32, ptr [[ARRAYIDX5]], align 4 713; CHECK-NEXT: [[MUL:%.*]] = shl nsw i32 [[TMP22]], 2 714; CHECK-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [1024 x i32], ptr [[LOCAL_DEST]], i64 0, i64 [[IV]] 715; CHECK-NEXT: store i32 [[MUL]], ptr [[ARRAYIDX7]], align 4 716; CHECK-NEXT: br label [[FOR_INC]] 717; CHECK: for.inc: 718; CHECK-NEXT: [[IV_NEXT]] = add nsw i64 [[IV]], -1 719; CHECK-NEXT: [[CMP2_NOT:%.*]] = icmp eq i64 [[IV]], 0 720; CHECK-NEXT: br i1 [[CMP2_NOT]], label [[EXIT]], label [[FOR_BODY]], !llvm.loop [[LOOP17:![0-9]+]] 721; CHECK: exit: 722; CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr [[DEST:%.*]], ptr [[LOCAL_DEST]], i64 1024, i1 false) 723; CHECK-NEXT: ret void 724; 725entry: 726 %local_dest = alloca [1024 x i32], align 4 727 %local_src = alloca [1024 x i32], align 4 728 %local_cmp = alloca [1024 x i32], align 4 729 call void @init(ptr %local_src) 730 call void @init(ptr %local_cmp) 731 br label %for.body 732 733for.body: 734 %iv = phi i64 [ 511, %entry ], [ %iv.next, %for.inc ] 735 %arrayidx = getelementptr inbounds [1024 x i32], ptr %local_cmp, i64 0, i64 %iv 736 %0 = load i32, ptr %arrayidx, align 4 737 %cmp3.not = icmp eq i32 %0, 3 738 br i1 %cmp3.not, label %for.inc, label %if.then 739 740if.then: 741 %iv.strided = mul i64 %iv, 2 742 %arrayidx5 = getelementptr inbounds [1024 x i32], ptr %local_src, i64 0, i64 %iv.strided 743 %1 = load i32, ptr %arrayidx5, align 4 744 %mul = shl nsw i32 %1, 2 745 %arrayidx7 = getelementptr inbounds [1024 x i32], ptr %local_dest, i64 0, i64 %iv 746 store i32 %mul, ptr %arrayidx7, align 4 747 br label %for.inc 748 749for.inc: 750 %iv.next = add nsw i64 %iv, -1 751 %cmp2.not = icmp eq i64 %iv, 0 752 br i1 %cmp2.not, label %exit, label %for.body 753 754exit: 755 call void @llvm.memcpy.p0.p0.i64(ptr %dest, ptr %local_dest, i64 1024, i1 false) 756 ret void 757} 758