1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 2; RUN: opt -S -passes=loop-vectorize -force-vector-width=4 < %s | FileCheck %s 3 4; This is a regression test. Without the fix it crashes on SSAUpdater due to 5; LoopVectroizer created a phi node placeholder without incoming values but 6; SSAUpdater expects that phi node is completely filled. 7 8target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128-ni:1-p2:32:8:8:32-ni:2" 9define void @test(i32 %arg, i32 %L1.limit, i32 %L2.switch, i1 %c, ptr %dst) { 10; CHECK-LABEL: @test( 11; CHECK-NEXT: L1.preheader: 12; CHECK-NEXT: [[TMP0:%.*]] = sub i32 -1, [[ARG:%.*]] 13; CHECK-NEXT: br label [[L1_HEADER:%.*]] 14; CHECK: L1.header: 15; CHECK-NEXT: [[INDUCTION_IV:%.*]] = phi i32 [ [[INDUCTION_IV_NEXT:%.*]], [[L1_BACKEDGE:%.*]] ], [ [[TMP0]], [[L1_PREHEADER:%.*]] ] 16; CHECK-NEXT: [[INDVAR:%.*]] = phi i32 [ [[INDVAR_NEXT:%.*]], [[L1_BACKEDGE]] ], [ 0, [[L1_PREHEADER]] ] 17; CHECK-NEXT: [[L1_SUM:%.*]] = phi i32 [ [[ARG]], [[L1_PREHEADER]] ], [ [[L1_SUM_NEXT:%.*]], [[L1_BACKEDGE]] ] 18; CHECK-NEXT: [[L1_IV:%.*]] = phi i32 [ 1, [[L1_PREHEADER]] ], [ [[L1_IV_NEXT:%.*]], [[L1_BACKEDGE]] ] 19; CHECK-NEXT: [[TMP1:%.*]] = mul nsw i32 [[INDVAR]], -1 20; CHECK-NEXT: [[TMP2:%.*]] = add i32 [[TMP1]], -2 21; CHECK-NEXT: br i1 [[C:%.*]], label [[L1_BACKEDGE]], label [[L1_EARLY_EXIT:%.*]] 22; CHECK: L1.backedge: 23; CHECK-NEXT: [[L1_SUM_NEXT]] = add i32 [[L1_IV]], [[L1_SUM]] 24; CHECK-NEXT: [[L1_IV_NEXT]] = add nuw nsw i32 [[L1_IV]], 1 25; CHECK-NEXT: [[L1_EXIT_COND:%.*]] = icmp ult i32 [[L1_IV_NEXT]], [[L1_LIMIT:%.*]] 26; CHECK-NEXT: [[INDVAR_NEXT]] = add i32 [[INDVAR]], 1 27; CHECK-NEXT: [[INDUCTION_IV_NEXT]] = add i32 [[INDUCTION_IV]], [[TMP2]] 28; CHECK-NEXT: br i1 [[L1_EXIT_COND]], label [[L1_HEADER]], label [[L1_EXIT:%.*]] 29; CHECK: L1.early.exit: 30; CHECK-NEXT: ret void 31; CHECK: L1.exit: 32; CHECK-NEXT: [[INDUCTION_IV_LCSSA1:%.*]] = phi i32 [ [[INDUCTION_IV]], [[L1_BACKEDGE]] ] 33; CHECK-NEXT: [[L1_EXIT_VAL:%.*]] = phi i32 [ [[L1_SUM_NEXT]], [[L1_BACKEDGE]] ] 34; CHECK-NEXT: br label [[L2_HEADER:%.*]] 35; CHECK: L2.header.loopexit: 36; CHECK-NEXT: br label [[L2_HEADER_BACKEDGE:%.*]] 37; CHECK: L2.header: 38; CHECK-NEXT: switch i32 [[L2_SWITCH:%.*]], label [[L2_HEADER_BACKEDGE]] [ 39; CHECK-NEXT: i32 8, label [[L2_EXIT:%.*]] 40; CHECK-NEXT: i32 20, label [[L2_INNER_HEADER_PREHEADER:%.*]] 41; CHECK-NEXT: ] 42; CHECK: L2.header.backedge: 43; CHECK-NEXT: br label [[L2_HEADER]] 44; CHECK: L2.Inner.header.preheader: 45; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] 46; CHECK: vector.ph: 47; CHECK-NEXT: [[TMP3:%.*]] = mul i32 12, [[INDUCTION_IV_LCSSA1]] 48; CHECK-NEXT: [[IND_END:%.*]] = add i32 1, [[TMP3]] 49; CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <4 x i32> poison, i32 [[INDUCTION_IV_LCSSA1]], i64 0 50; CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector <4 x i32> [[DOTSPLATINSERT]], <4 x i32> poison, <4 x i32> zeroinitializer 51; CHECK-NEXT: [[TMP4:%.*]] = mul <4 x i32> <i32 0, i32 1, i32 2, i32 3>, [[DOTSPLAT]] 52; CHECK-NEXT: [[INDUCTION:%.*]] = add <4 x i32> splat (i32 1), [[TMP4]] 53; CHECK-NEXT: [[TMP5:%.*]] = mul i32 [[INDUCTION_IV_LCSSA1]], 4 54; CHECK-NEXT: [[DOTSPLATINSERT3:%.*]] = insertelement <4 x i32> poison, i32 [[TMP5]], i64 0 55; CHECK-NEXT: [[DOTSPLAT4:%.*]] = shufflevector <4 x i32> [[DOTSPLATINSERT3]], <4 x i32> poison, <4 x i32> zeroinitializer 56; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i32> poison, i32 [[L1_EXIT_VAL]], i64 0 57; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i32> [[BROADCAST_SPLATINSERT]], <4 x i32> poison, <4 x i32> zeroinitializer 58; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] 59; CHECK: vector.body: 60; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] 61; CHECK-NEXT: [[VEC_IND:%.*]] = phi <4 x i32> [ [[INDUCTION]], [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[VECTOR_BODY]] ] 62; CHECK-NEXT: [[OFFSET_IDX:%.*]] = add i64 1, [[INDEX]] 63; CHECK-NEXT: [[TMP6:%.*]] = add i64 [[OFFSET_IDX]], 0 64; CHECK-NEXT: [[TMP7:%.*]] = sub <4 x i32> [[VEC_IND]], [[BROADCAST_SPLAT]] 65; CHECK-NEXT: [[TMP8:%.*]] = sext <4 x i32> [[TMP7]] to <4 x i64> 66; CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds i64, ptr [[DST:%.*]], i64 [[TMP6]] 67; CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds i64, ptr [[TMP9]], i32 0 68; CHECK-NEXT: store <4 x i64> [[TMP8]], ptr [[TMP10]], align 8 69; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 70; CHECK-NEXT: [[VEC_IND_NEXT]] = add <4 x i32> [[VEC_IND]], [[DOTSPLAT4]] 71; CHECK-NEXT: [[TMP11:%.*]] = icmp eq i64 [[INDEX_NEXT]], 12 72; CHECK-NEXT: br i1 [[TMP11]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] 73; CHECK: middle.block: 74; CHECK-NEXT: br i1 true, label [[L2_HEADER_LOOPEXIT:%.*]], label [[SCALAR_PH]] 75; CHECK: scalar.ph: 76; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[IND_END]], [[MIDDLE_BLOCK]] ], [ 1, [[L2_INNER_HEADER_PREHEADER]] ] 77; CHECK-NEXT: [[BC_RESUME_VAL2:%.*]] = phi i64 [ 13, [[MIDDLE_BLOCK]] ], [ 1, [[L2_INNER_HEADER_PREHEADER]] ] 78; CHECK-NEXT: br label [[L2_INNER_HEADER:%.*]] 79; CHECK: L2.Inner.header: 80; CHECK-NEXT: [[L2_ACCUM:%.*]] = phi i32 [ [[L2_ACCUM_NEXT:%.*]], [[L2_INNER_HEADER]] ], [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ] 81; CHECK-NEXT: [[L2_IV:%.*]] = phi i64 [ [[L2_IV_NEXT:%.*]], [[L2_INNER_HEADER]] ], [ [[BC_RESUME_VAL2]], [[SCALAR_PH]] ] 82; CHECK-NEXT: [[L2_ACCUM_NEXT]] = sub i32 [[L2_ACCUM]], [[L1_EXIT_VAL]] 83; CHECK-NEXT: [[L2_DUMMY_BUT_NEED_IT:%.*]] = sext i32 [[L2_ACCUM_NEXT]] to i64 84; CHECK-NEXT: [[GEP:%.*]] = getelementptr inbounds i64, ptr [[DST]], i64 [[L2_IV]] 85; CHECK-NEXT: store i64 [[L2_DUMMY_BUT_NEED_IT]], ptr [[GEP]], align 8 86; CHECK-NEXT: [[L2_IV_NEXT]] = add nuw nsw i64 [[L2_IV]], 1 87; CHECK-NEXT: [[L2_EXIT_COND:%.*]] = icmp ugt i64 [[L2_IV]], 11 88; CHECK-NEXT: br i1 [[L2_EXIT_COND]], label [[L2_HEADER_LOOPEXIT]], label [[L2_INNER_HEADER]], !llvm.loop [[LOOP3:![0-9]+]] 89; CHECK: L2.exit: 90; CHECK-NEXT: ret void 91; 92L1.preheader: 93 br label %L1.header 94 95L1.header: ; preds = %L1.preheader, %L1.backedge 96 %L1.sum = phi i32 [ %arg, %L1.preheader ], [ %L1.sum.next, %L1.backedge ] 97 %L1.iv = phi i32 [ 1, %L1.preheader ], [ %L1.iv.next, %L1.backedge ] 98 br i1 %c, label %L1.backedge, label %L1.early.exit 99 100L1.backedge: ; preds = %L1.header 101 %L1.sum.next = add i32 %L1.iv, %L1.sum 102 %L1.iv.next = add nuw nsw i32 %L1.iv, 1 103 %L1.exit.cond = icmp ult i32 %L1.iv.next, %L1.limit 104 br i1 %L1.exit.cond, label %L1.header, label %L1.exit 105 106L1.early.exit: ; preds = %L1.header 107 ret void 108 109L1.exit: ; preds = %L1.backedge 110 %L1.exit.val = phi i32 [ %L1.sum.next, %L1.backedge ] 111 br label %L2.header 112 113L2.header: ; preds = %L2.Inner.header, %L1.exit, %L2.header 114 switch i32 %L2.switch, label %L2.header [ 115 i32 8, label %L2.exit 116 i32 20, label %L2.Inner.header 117 ] 118 119L2.Inner.header: ; preds = %L2.Inner.header, %L2.header 120 %L2.accum = phi i32 [ %L2.accum.next, %L2.Inner.header ], [ 1, %L2.header ] 121 %L2.iv = phi i64 [ %L2.iv.next, %L2.Inner.header ], [ 1, %L2.header ] 122 %L2.accum.next = sub i32 %L2.accum, %L1.exit.val 123 %L2.dummy.but.need.it = sext i32 %L2.accum.next to i64 124 %gep = getelementptr inbounds i64 , ptr %dst, i64 %L2.iv 125 store i64 %L2.dummy.but.need.it, ptr %gep 126 %L2.iv.next = add nuw nsw i64 %L2.iv, 1 127 %L2.exit_cond = icmp ugt i64 %L2.iv, 11 128 br i1 %L2.exit_cond, label %L2.header, label %L2.Inner.header 129 130L2.exit: ; preds = %L2.header 131 ret void 132} 133 134