1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 2; RUN: opt < %s -passes=loop-vectorize,dce,instcombine -force-vector-interleave=1 -force-vector-width=4 -loop-vectorize-with-block-frequency -S | FileCheck %s 3 4target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" 5target triple = "x86_64-apple-macosx10.8.0" 6 7@b = common global [2048 x i32] zeroinitializer, align 16 8@c = common global [2048 x i32] zeroinitializer, align 16 9@a = common global [2048 x i32] zeroinitializer, align 16 10@G = common global [32 x [1024 x i32]] zeroinitializer, align 16 11@ub = common global [1024 x i32] zeroinitializer, align 16 12@uc = common global [1024 x i32] zeroinitializer, align 16 13@d = common global [2048 x i32] zeroinitializer, align 16 14@fa = common global [1024 x float] zeroinitializer, align 16 15@fb = common global [1024 x float] zeroinitializer, align 16 16@ic = common global [1024 x i32] zeroinitializer, align 16 17@da = common global [1024 x float] zeroinitializer, align 16 18@db = common global [1024 x float] zeroinitializer, align 16 19@dc = common global [1024 x float] zeroinitializer, align 16 20@dd = common global [1024 x float] zeroinitializer, align 16 21@dj = common global [1024 x i32] zeroinitializer, align 16 22 23; We can optimize this test without a tail. 24define void @example1() optsize { 25; CHECK-LABEL: @example1( 26; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] 27; CHECK: vector.ph: 28; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] 29; CHECK: vector.body: 30; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] 31; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds [2048 x i32], ptr @b, i64 0, i64 [[INDEX]] 32; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP1]], align 4 33; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds [2048 x i32], ptr @c, i64 0, i64 [[INDEX]] 34; CHECK-NEXT: [[WIDE_LOAD1:%.*]] = load <4 x i32>, ptr [[TMP2]], align 4 35; CHECK-NEXT: [[TMP3:%.*]] = add nsw <4 x i32> [[WIDE_LOAD1]], [[WIDE_LOAD]] 36; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2048 x i32], ptr @a, i64 0, i64 [[INDEX]] 37; CHECK-NEXT: store <4 x i32> [[TMP3]], ptr [[TMP4]], align 4 38; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 39; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT]], 256 40; CHECK-NEXT: br i1 [[TMP5]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] 41; CHECK: middle.block: 42; CHECK-NEXT: br i1 true, label [[TMP7:%.*]], label [[SCALAR_PH]] 43; CHECK: scalar.ph: 44; CHECK-NEXT: br label [[TMP6:%.*]] 45; CHECK: 6: 46; CHECK-NEXT: br i1 poison, label [[TMP7]], label [[TMP6]], !llvm.loop [[LOOP3:![0-9]+]] 47; CHECK: 7: 48; CHECK-NEXT: ret void 49; 50 br label %1 51 52; <label>:1 ; preds = %1, %0 53 %indvars.iv = phi i64 [ 0, %0 ], [ %indvars.iv.next, %1 ] 54 %2 = getelementptr inbounds [2048 x i32], ptr @b, i64 0, i64 %indvars.iv 55 %3 = load i32, ptr %2, align 4 56 %4 = getelementptr inbounds [2048 x i32], ptr @c, i64 0, i64 %indvars.iv 57 %5 = load i32, ptr %4, align 4 58 %6 = add nsw i32 %5, %3 59 %7 = getelementptr inbounds [2048 x i32], ptr @a, i64 0, i64 %indvars.iv 60 store i32 %6, ptr %7, align 4 61 %indvars.iv.next = add i64 %indvars.iv, 1 62 %lftr.wideiv = trunc i64 %indvars.iv.next to i32 63 %exitcond = icmp eq i32 %lftr.wideiv, 256 64 br i1 %exitcond, label %8, label %1 65 66; <label>:8 ; preds = %1 67 ret void 68} 69 70; Can vectorize in 'optsize' mode by masking the needed tail. 71define void @example2(i32 %n, i32 %x) optsize { 72; CHECK-LABEL: @example2( 73; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt i32 [[N:%.*]], 0 74; CHECK-NEXT: br i1 [[TMP1]], label [[DOTLR_PH5_PREHEADER:%.*]], label [[DOTPREHEADER:%.*]] 75; CHECK: .lr.ph5.preheader: 76; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] 77; CHECK: vector.ph: 78; CHECK-NEXT: [[TMP2:%.*]] = zext nneg i32 [[N]] to i64 79; CHECK-NEXT: [[N_RND_UP:%.*]] = add nuw nsw i64 [[TMP2]], 3 80; CHECK-NEXT: [[N_VEC:%.*]] = and i64 [[N_RND_UP]], 4294967292 81; CHECK-NEXT: [[TRIP_COUNT_MINUS_1:%.*]] = add nsw i64 [[TMP2]], -1 82; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i64> poison, i64 [[TRIP_COUNT_MINUS_1]], i64 0 83; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i64> [[BROADCAST_SPLATINSERT]], <4 x i64> poison, <4 x i32> zeroinitializer 84; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] 85; CHECK: vector.body: 86; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[PRED_STORE_CONTINUE6:%.*]] ] 87; CHECK-NEXT: [[VEC_IND:%.*]] = phi <4 x i64> [ <i64 0, i64 1, i64 2, i64 3>, [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[PRED_STORE_CONTINUE6]] ] 88; CHECK-NEXT: [[TMP3:%.*]] = icmp ule <4 x i64> [[VEC_IND]], [[BROADCAST_SPLAT]] 89; CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x i1> [[TMP3]], i64 0 90; CHECK-NEXT: br i1 [[TMP4]], label [[PRED_STORE_IF:%.*]], label [[PRED_STORE_CONTINUE:%.*]] 91; CHECK: pred.store.if: 92; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds [2048 x i32], ptr @b, i64 0, i64 [[INDEX]] 93; CHECK-NEXT: store i32 [[X:%.*]], ptr [[TMP5]], align 4 94; CHECK-NEXT: br label [[PRED_STORE_CONTINUE]] 95; CHECK: pred.store.continue: 96; CHECK-NEXT: [[TMP6:%.*]] = extractelement <4 x i1> [[TMP3]], i64 1 97; CHECK-NEXT: br i1 [[TMP6]], label [[PRED_STORE_IF1:%.*]], label [[PRED_STORE_CONTINUE2:%.*]] 98; CHECK: pred.store.if1: 99; CHECK-NEXT: [[TMP7:%.*]] = or disjoint i64 [[INDEX]], 1 100; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2048 x i32], ptr @b, i64 0, i64 [[TMP7]] 101; CHECK-NEXT: store i32 [[X]], ptr [[TMP8]], align 4 102; CHECK-NEXT: br label [[PRED_STORE_CONTINUE2]] 103; CHECK: pred.store.continue2: 104; CHECK-NEXT: [[TMP9:%.*]] = extractelement <4 x i1> [[TMP3]], i64 2 105; CHECK-NEXT: br i1 [[TMP9]], label [[PRED_STORE_IF3:%.*]], label [[PRED_STORE_CONTINUE4:%.*]] 106; CHECK: pred.store.if3: 107; CHECK-NEXT: [[TMP10:%.*]] = or disjoint i64 [[INDEX]], 2 108; CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds [2048 x i32], ptr @b, i64 0, i64 [[TMP10]] 109; CHECK-NEXT: store i32 [[X]], ptr [[TMP11]], align 4 110; CHECK-NEXT: br label [[PRED_STORE_CONTINUE4]] 111; CHECK: pred.store.continue4: 112; CHECK-NEXT: [[TMP12:%.*]] = extractelement <4 x i1> [[TMP3]], i64 3 113; CHECK-NEXT: br i1 [[TMP12]], label [[PRED_STORE_IF5:%.*]], label [[PRED_STORE_CONTINUE6]] 114; CHECK: pred.store.if5: 115; CHECK-NEXT: [[TMP13:%.*]] = or disjoint i64 [[INDEX]], 3 116; CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds [2048 x i32], ptr @b, i64 0, i64 [[TMP13]] 117; CHECK-NEXT: store i32 [[X]], ptr [[TMP14]], align 4 118; CHECK-NEXT: br label [[PRED_STORE_CONTINUE6]] 119; CHECK: pred.store.continue6: 120; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 121; CHECK-NEXT: [[VEC_IND_NEXT]] = add <4 x i64> [[VEC_IND]], splat (i64 4) 122; CHECK-NEXT: [[TMP15:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] 123; CHECK-NEXT: br i1 [[TMP15]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]] 124; CHECK: middle.block: 125; CHECK-NEXT: br i1 true, label [[DOT_PREHEADER_CRIT_EDGE:%.*]], label [[SCALAR_PH]] 126; CHECK: scalar.ph: 127; CHECK-NEXT: br label [[DOTLR_PH5:%.*]] 128; CHECK: ..preheader_crit_edge: 129; CHECK-NEXT: [[PHITMP:%.*]] = zext nneg i32 [[N]] to i64 130; CHECK-NEXT: br label [[DOTPREHEADER]] 131; CHECK: .preheader: 132; CHECK-NEXT: [[I_0_LCSSA:%.*]] = phi i64 [ [[PHITMP]], [[DOT_PREHEADER_CRIT_EDGE]] ], [ 0, [[TMP0:%.*]] ] 133; CHECK-NEXT: [[TMP16:%.*]] = icmp eq i32 [[N]], 0 134; CHECK-NEXT: br i1 [[TMP16]], label [[DOT_CRIT_EDGE:%.*]], label [[DOTLR_PH_PREHEADER:%.*]] 135; CHECK: .lr.ph.preheader: 136; CHECK-NEXT: br i1 false, label [[SCALAR_PH8:%.*]], label [[VECTOR_PH9:%.*]] 137; CHECK: vector.ph9: 138; CHECK-NEXT: [[TMP17:%.*]] = zext i32 [[N]] to i64 139; CHECK-NEXT: [[N_RND_UP10:%.*]] = add nuw nsw i64 [[TMP17]], 3 140; CHECK-NEXT: [[N_VEC12:%.*]] = and i64 [[N_RND_UP10]], 8589934588 141; CHECK-NEXT: [[TRIP_COUNT_MINUS_114:%.*]] = add nsw i64 [[TMP17]], -1 142; CHECK-NEXT: [[BROADCAST_SPLATINSERT19:%.*]] = insertelement <4 x i64> poison, i64 [[TRIP_COUNT_MINUS_114]], i64 0 143; CHECK-NEXT: [[BROADCAST_SPLAT20:%.*]] = shufflevector <4 x i64> [[BROADCAST_SPLATINSERT19]], <4 x i64> poison, <4 x i32> zeroinitializer 144; CHECK-NEXT: br label [[VECTOR_BODY15:%.*]] 145; CHECK: vector.body14: 146; CHECK-NEXT: [[INDEX16:%.*]] = phi i64 [ 0, [[VECTOR_PH9]] ], [ [[INDEX_NEXT29:%.*]], [[PRED_STORE_CONTINUE78:%.*]] ] 147; CHECK-NEXT: [[OFFSET_IDX:%.*]] = add i64 [[I_0_LCSSA]], [[INDEX16]] 148; CHECK-NEXT: [[BROADCAST_SPLATINSERT17:%.*]] = insertelement <4 x i64> poison, i64 [[INDEX16]], i64 0 149; CHECK-NEXT: [[BROADCAST_SPLAT18:%.*]] = shufflevector <4 x i64> [[BROADCAST_SPLATINSERT17]], <4 x i64> poison, <4 x i32> zeroinitializer 150; CHECK-NEXT: [[VEC_IV:%.*]] = or disjoint <4 x i64> [[BROADCAST_SPLAT18]], <i64 0, i64 1, i64 2, i64 3> 151; CHECK-NEXT: [[TMP18:%.*]] = icmp ule <4 x i64> [[VEC_IV]], [[BROADCAST_SPLAT20]] 152; CHECK-NEXT: [[TMP19:%.*]] = extractelement <4 x i1> [[TMP18]], i64 0 153; CHECK-NEXT: br i1 [[TMP19]], label [[PRED_STORE_IF21:%.*]], label [[PRED_STORE_CONTINUE22:%.*]] 154; CHECK: pred.store.if20: 155; CHECK-NEXT: [[TMP20:%.*]] = getelementptr inbounds [2048 x i32], ptr @b, i64 0, i64 [[OFFSET_IDX]] 156; CHECK-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4 157; CHECK-NEXT: [[TMP22:%.*]] = getelementptr inbounds [2048 x i32], ptr @c, i64 0, i64 [[OFFSET_IDX]] 158; CHECK-NEXT: [[TMP23:%.*]] = load i32, ptr [[TMP22]], align 4 159; CHECK-NEXT: [[TMP24:%.*]] = getelementptr inbounds [2048 x i32], ptr @a, i64 0, i64 [[OFFSET_IDX]] 160; CHECK-NEXT: [[TMP25:%.*]] = and i32 [[TMP23]], [[TMP21]] 161; CHECK-NEXT: store i32 [[TMP25]], ptr [[TMP24]], align 4 162; CHECK-NEXT: br label [[PRED_STORE_CONTINUE22]] 163; CHECK: pred.store.continue21: 164; CHECK-NEXT: [[TMP26:%.*]] = extractelement <4 x i1> [[TMP18]], i64 1 165; CHECK-NEXT: br i1 [[TMP26]], label [[PRED_STORE_IF23:%.*]], label [[PRED_STORE_CONTINUE24:%.*]] 166; CHECK: pred.store.if22: 167; CHECK-NEXT: [[TMP27:%.*]] = add i64 [[OFFSET_IDX]], 1 168; CHECK-NEXT: [[TMP28:%.*]] = getelementptr inbounds [2048 x i32], ptr @b, i64 0, i64 [[TMP27]] 169; CHECK-NEXT: [[TMP29:%.*]] = load i32, ptr [[TMP28]], align 4 170; CHECK-NEXT: [[TMP30:%.*]] = getelementptr inbounds [2048 x i32], ptr @c, i64 0, i64 [[TMP27]] 171; CHECK-NEXT: [[TMP31:%.*]] = load i32, ptr [[TMP30]], align 4 172; CHECK-NEXT: [[TMP32:%.*]] = getelementptr inbounds [2048 x i32], ptr @a, i64 0, i64 [[TMP27]] 173; CHECK-NEXT: [[TMP33:%.*]] = and i32 [[TMP31]], [[TMP29]] 174; CHECK-NEXT: store i32 [[TMP33]], ptr [[TMP32]], align 4 175; CHECK-NEXT: br label [[PRED_STORE_CONTINUE24]] 176; CHECK: pred.store.continue23: 177; CHECK-NEXT: [[TMP34:%.*]] = extractelement <4 x i1> [[TMP18]], i64 2 178; CHECK-NEXT: br i1 [[TMP34]], label [[PRED_STORE_IF25:%.*]], label [[PRED_STORE_CONTINUE26:%.*]] 179; CHECK: pred.store.if24: 180; CHECK-NEXT: [[TMP35:%.*]] = add i64 [[OFFSET_IDX]], 2 181; CHECK-NEXT: [[TMP36:%.*]] = getelementptr inbounds [2048 x i32], ptr @b, i64 0, i64 [[TMP35]] 182; CHECK-NEXT: [[TMP37:%.*]] = load i32, ptr [[TMP36]], align 4 183; CHECK-NEXT: [[TMP38:%.*]] = getelementptr inbounds [2048 x i32], ptr @c, i64 0, i64 [[TMP35]] 184; CHECK-NEXT: [[TMP39:%.*]] = load i32, ptr [[TMP38]], align 4 185; CHECK-NEXT: [[TMP40:%.*]] = getelementptr inbounds [2048 x i32], ptr @a, i64 0, i64 [[TMP35]] 186; CHECK-NEXT: [[TMP41:%.*]] = and i32 [[TMP39]], [[TMP37]] 187; CHECK-NEXT: store i32 [[TMP41]], ptr [[TMP40]], align 4 188; CHECK-NEXT: br label [[PRED_STORE_CONTINUE26]] 189; CHECK: pred.store.continue25: 190; CHECK-NEXT: [[TMP42:%.*]] = extractelement <4 x i1> [[TMP18]], i64 3 191; CHECK-NEXT: br i1 [[TMP42]], label [[PRED_STORE_IF26:%.*]], label [[PRED_STORE_CONTINUE78]] 192; CHECK: pred.store.if26: 193; CHECK-NEXT: [[TMP43:%.*]] = add i64 [[OFFSET_IDX]], 3 194; CHECK-NEXT: [[TMP44:%.*]] = getelementptr inbounds [2048 x i32], ptr @b, i64 0, i64 [[TMP43]] 195; CHECK-NEXT: [[TMP45:%.*]] = load i32, ptr [[TMP44]], align 4 196; CHECK-NEXT: [[TMP46:%.*]] = getelementptr inbounds [2048 x i32], ptr @c, i64 0, i64 [[TMP43]] 197; CHECK-NEXT: [[TMP47:%.*]] = load i32, ptr [[TMP46]], align 4 198; CHECK-NEXT: [[TMP48:%.*]] = getelementptr inbounds [2048 x i32], ptr @a, i64 0, i64 [[TMP43]] 199; CHECK-NEXT: [[TMP49:%.*]] = and i32 [[TMP47]], [[TMP45]] 200; CHECK-NEXT: store i32 [[TMP49]], ptr [[TMP48]], align 4 201; CHECK-NEXT: br label [[PRED_STORE_CONTINUE78]] 202; CHECK: pred.store.continue27: 203; CHECK-NEXT: [[INDEX_NEXT29]] = add nuw i64 [[INDEX16]], 4 204; CHECK-NEXT: [[TMP50:%.*]] = icmp eq i64 [[INDEX_NEXT29]], [[N_VEC12]] 205; CHECK-NEXT: br i1 [[TMP50]], label [[MIDDLE_BLOCK7:%.*]], label [[VECTOR_BODY15]], !llvm.loop [[LOOP5:![0-9]+]] 206; CHECK: middle.block7: 207; CHECK-NEXT: br i1 true, label [[DOT_CRIT_EDGE_LOOPEXIT:%.*]], label [[SCALAR_PH8]] 208; CHECK: scalar.ph8: 209; CHECK-NEXT: br label [[DOTLR_PH:%.*]] 210; CHECK: .lr.ph5: 211; CHECK-NEXT: br i1 poison, label [[DOT_PREHEADER_CRIT_EDGE]], label [[DOTLR_PH5]], !llvm.loop [[LOOP6:![0-9]+]] 212; CHECK: .lr.ph: 213; CHECK-NEXT: br i1 poison, label [[DOT_CRIT_EDGE_LOOPEXIT]], label [[DOTLR_PH]], !llvm.loop [[LOOP7:![0-9]+]] 214; CHECK: ._crit_edge.loopexit: 215; CHECK-NEXT: br label [[DOT_CRIT_EDGE]] 216; CHECK: ._crit_edge: 217; CHECK-NEXT: ret void 218; 219 %1 = icmp sgt i32 %n, 0 220 br i1 %1, label %.lr.ph5, label %.preheader 221 222..preheader_crit_edge: ; preds = %.lr.ph5 223 %phitmp = sext i32 %n to i64 224 br label %.preheader 225 226.preheader: ; preds = %..preheader_crit_edge, %0 227 %i.0.lcssa = phi i64 [ %phitmp, %..preheader_crit_edge ], [ 0, %0 ] 228 %2 = icmp eq i32 %n, 0 229 br i1 %2, label %._crit_edge, label %.lr.ph 230 231.lr.ph5: ; preds = %0, %.lr.ph5 232 %indvars.iv6 = phi i64 [ %indvars.iv.next7, %.lr.ph5 ], [ 0, %0 ] 233 %3 = getelementptr inbounds [2048 x i32], ptr @b, i64 0, i64 %indvars.iv6 234 store i32 %x, ptr %3, align 4 235 %indvars.iv.next7 = add i64 %indvars.iv6, 1 236 %lftr.wideiv = trunc i64 %indvars.iv.next7 to i32 237 %exitcond = icmp eq i32 %lftr.wideiv, %n 238 br i1 %exitcond, label %..preheader_crit_edge, label %.lr.ph5 239 240.lr.ph: ; preds = %.preheader, %.lr.ph 241 %indvars.iv = phi i64 [ %indvars.iv.next, %.lr.ph ], [ %i.0.lcssa, %.preheader ] 242 %.02 = phi i32 [ %4, %.lr.ph ], [ %n, %.preheader ] 243 %4 = add nsw i32 %.02, -1 244 %5 = getelementptr inbounds [2048 x i32], ptr @b, i64 0, i64 %indvars.iv 245 %6 = load i32, ptr %5, align 4 246 %7 = getelementptr inbounds [2048 x i32], ptr @c, i64 0, i64 %indvars.iv 247 %8 = load i32, ptr %7, align 4 248 %9 = and i32 %8, %6 249 %10 = getelementptr inbounds [2048 x i32], ptr @a, i64 0, i64 %indvars.iv 250 store i32 %9, ptr %10, align 4 251 %indvars.iv.next = add i64 %indvars.iv, 1 252 %11 = icmp eq i32 %4, 0 253 br i1 %11, label %._crit_edge, label %.lr.ph 254 255._crit_edge: ; preds = %.lr.ph, %.preheader 256 ret void 257} 258 259; Loop has no primary induction as its integer IV has step -1 starting at 260; unknown N, but can still be vectorized. 261define void @example3(i32 %n, ptr noalias nocapture %p, ptr noalias nocapture %q) optsize { 262; CHECK-LABEL: @example3( 263; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i32 [[N:%.*]], 0 264; CHECK-NEXT: br i1 [[TMP1]], label [[DOT_CRIT_EDGE:%.*]], label [[DOTLR_PH_PREHEADER:%.*]] 265; CHECK: .lr.ph.preheader: 266; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] 267; CHECK: vector.ph: 268; CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[N]] to i64 269; CHECK-NEXT: [[N_RND_UP:%.*]] = add nuw nsw i64 [[TMP2]], 3 270; CHECK-NEXT: [[N_VEC:%.*]] = and i64 [[N_RND_UP]], 8589934588 271; CHECK-NEXT: [[TRIP_COUNT_MINUS_1:%.*]] = add nsw i64 [[TMP2]], -1 272; CHECK-NEXT: [[BROADCAST_SPLATINSERT11:%.*]] = insertelement <4 x i64> poison, i64 [[TRIP_COUNT_MINUS_1]], i64 0 273; CHECK-NEXT: [[BROADCAST_SPLAT12:%.*]] = shufflevector <4 x i64> [[BROADCAST_SPLATINSERT11]], <4 x i64> poison, <4 x i32> zeroinitializer 274; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] 275; CHECK: vector.body: 276; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[PRED_STORE_CONTINUE16:%.*]] ] 277; CHECK-NEXT: [[OFFSET_IDX:%.*]] = shl i64 [[INDEX]], 2 278; CHECK-NEXT: [[OFFSET_IDX6:%.*]] = shl i64 [[INDEX]], 2 279; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i64> poison, i64 [[INDEX]], i64 0 280; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i64> [[BROADCAST_SPLATINSERT]], <4 x i64> poison, <4 x i32> zeroinitializer 281; CHECK-NEXT: [[VEC_IV:%.*]] = or disjoint <4 x i64> [[BROADCAST_SPLAT]], <i64 0, i64 1, i64 2, i64 3> 282; CHECK-NEXT: [[TMP3:%.*]] = icmp ule <4 x i64> [[VEC_IV]], [[BROADCAST_SPLAT12]] 283; CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x i1> [[TMP3]], i64 0 284; CHECK-NEXT: br i1 [[TMP4]], label [[PRED_STORE_IF:%.*]], label [[PRED_STORE_CONTINUE:%.*]] 285; CHECK: pred.store.if: 286; CHECK-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, ptr [[P:%.*]], i64 [[OFFSET_IDX]] 287; CHECK-NEXT: [[NEXT_GEP7:%.*]] = getelementptr i8, ptr [[Q:%.*]], i64 [[OFFSET_IDX6]] 288; CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[NEXT_GEP7]], align 16 289; CHECK-NEXT: store i32 [[TMP5]], ptr [[NEXT_GEP]], align 16 290; CHECK-NEXT: br label [[PRED_STORE_CONTINUE]] 291; CHECK: pred.store.continue: 292; CHECK-NEXT: [[TMP6:%.*]] = extractelement <4 x i1> [[TMP3]], i64 1 293; CHECK-NEXT: br i1 [[TMP6]], label [[PRED_STORE_IF11:%.*]], label [[PRED_STORE_CONTINUE12:%.*]] 294; CHECK: pred.store.if11: 295; CHECK-NEXT: [[TMP7:%.*]] = or disjoint i64 [[OFFSET_IDX]], 4 296; CHECK-NEXT: [[NEXT_GEP3:%.*]] = getelementptr i8, ptr [[P]], i64 [[TMP7]] 297; CHECK-NEXT: [[TMP8:%.*]] = or disjoint i64 [[OFFSET_IDX6]], 4 298; CHECK-NEXT: [[NEXT_GEP8:%.*]] = getelementptr i8, ptr [[Q]], i64 [[TMP8]] 299; CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr [[NEXT_GEP8]], align 16 300; CHECK-NEXT: store i32 [[TMP9]], ptr [[NEXT_GEP3]], align 16 301; CHECK-NEXT: br label [[PRED_STORE_CONTINUE12]] 302; CHECK: pred.store.continue12: 303; CHECK-NEXT: [[TMP10:%.*]] = extractelement <4 x i1> [[TMP3]], i64 2 304; CHECK-NEXT: br i1 [[TMP10]], label [[PRED_STORE_IF13:%.*]], label [[PRED_STORE_CONTINUE14:%.*]] 305; CHECK: pred.store.if13: 306; CHECK-NEXT: [[TMP11:%.*]] = or disjoint i64 [[OFFSET_IDX]], 8 307; CHECK-NEXT: [[NEXT_GEP4:%.*]] = getelementptr i8, ptr [[P]], i64 [[TMP11]] 308; CHECK-NEXT: [[TMP12:%.*]] = or disjoint i64 [[OFFSET_IDX6]], 8 309; CHECK-NEXT: [[NEXT_GEP9:%.*]] = getelementptr i8, ptr [[Q]], i64 [[TMP12]] 310; CHECK-NEXT: [[TMP13:%.*]] = load i32, ptr [[NEXT_GEP9]], align 16 311; CHECK-NEXT: store i32 [[TMP13]], ptr [[NEXT_GEP4]], align 16 312; CHECK-NEXT: br label [[PRED_STORE_CONTINUE14]] 313; CHECK: pred.store.continue14: 314; CHECK-NEXT: [[TMP14:%.*]] = extractelement <4 x i1> [[TMP3]], i64 3 315; CHECK-NEXT: br i1 [[TMP14]], label [[PRED_STORE_IF15:%.*]], label [[PRED_STORE_CONTINUE16]] 316; CHECK: pred.store.if15: 317; CHECK-NEXT: [[TMP15:%.*]] = or disjoint i64 [[OFFSET_IDX]], 12 318; CHECK-NEXT: [[NEXT_GEP5:%.*]] = getelementptr i8, ptr [[P]], i64 [[TMP15]] 319; CHECK-NEXT: [[TMP16:%.*]] = or disjoint i64 [[OFFSET_IDX6]], 12 320; CHECK-NEXT: [[NEXT_GEP10:%.*]] = getelementptr i8, ptr [[Q]], i64 [[TMP16]] 321; CHECK-NEXT: [[TMP17:%.*]] = load i32, ptr [[NEXT_GEP10]], align 16 322; CHECK-NEXT: store i32 [[TMP17]], ptr [[NEXT_GEP5]], align 16 323; CHECK-NEXT: br label [[PRED_STORE_CONTINUE16]] 324; CHECK: pred.store.continue16: 325; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 326; CHECK-NEXT: [[TMP18:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] 327; CHECK-NEXT: br i1 [[TMP18]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]] 328; CHECK: middle.block: 329; CHECK-NEXT: br i1 true, label [[DOT_CRIT_EDGE_LOOPEXIT:%.*]], label [[SCALAR_PH]] 330; CHECK: scalar.ph: 331; CHECK-NEXT: br label [[DOTLR_PH:%.*]] 332; CHECK: .lr.ph: 333; CHECK-NEXT: br i1 poison, label [[DOT_CRIT_EDGE_LOOPEXIT]], label [[DOTLR_PH]], !llvm.loop [[LOOP9:![0-9]+]] 334; CHECK: ._crit_edge.loopexit: 335; CHECK-NEXT: br label [[DOT_CRIT_EDGE]] 336; CHECK: ._crit_edge: 337; CHECK-NEXT: ret void 338; 339 %1 = icmp eq i32 %n, 0 340 br i1 %1, label %._crit_edge, label %.lr.ph 341 342.lr.ph: ; preds = %0, %.lr.ph 343 %.05 = phi i32 [ %2, %.lr.ph ], [ %n, %0 ] 344 %.014 = phi ptr [ %5, %.lr.ph ], [ %p, %0 ] 345 %.023 = phi ptr [ %3, %.lr.ph ], [ %q, %0 ] 346 %2 = add nsw i32 %.05, -1 347 %3 = getelementptr inbounds i32, ptr %.023, i64 1 348 %4 = load i32, ptr %.023, align 16 349 %5 = getelementptr inbounds i32, ptr %.014, i64 1 350 store i32 %4, ptr %.014, align 16 351 %6 = icmp eq i32 %2, 0 352 br i1 %6, label %._crit_edge, label %.lr.ph 353 354._crit_edge: ; preds = %.lr.ph, %0 355 ret void 356} 357 358; We can't vectorize this one because we need a runtime ptr check. 359define void @example23(ptr nocapture %src, ptr nocapture %dst) optsize { 360; CHECK-LABEL: @example23( 361; CHECK-NEXT: br label [[TMP1:%.*]] 362; CHECK: 1: 363; CHECK-NEXT: [[DOT04:%.*]] = phi ptr [ [[SRC:%.*]], [[TMP0:%.*]] ], [ [[TMP2:%.*]], [[TMP1]] ] 364; CHECK-NEXT: [[DOT013:%.*]] = phi ptr [ [[DST:%.*]], [[TMP0]] ], [ [[TMP6:%.*]], [[TMP1]] ] 365; CHECK-NEXT: [[I_02:%.*]] = phi i32 [ 0, [[TMP0]] ], [ [[TMP7:%.*]], [[TMP1]] ] 366; CHECK-NEXT: [[TMP2]] = getelementptr inbounds nuw i8, ptr [[DOT04]], i64 2 367; CHECK-NEXT: [[TMP3:%.*]] = load i16, ptr [[DOT04]], align 2 368; CHECK-NEXT: [[TMP4:%.*]] = zext i16 [[TMP3]] to i32 369; CHECK-NEXT: [[TMP5:%.*]] = shl nuw nsw i32 [[TMP4]], 7 370; CHECK-NEXT: [[TMP6]] = getelementptr inbounds nuw i8, ptr [[DOT013]], i64 4 371; CHECK-NEXT: store i32 [[TMP5]], ptr [[DOT013]], align 4 372; CHECK-NEXT: [[TMP7]] = add nuw nsw i32 [[I_02]], 1 373; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i32 [[TMP7]], 256 374; CHECK-NEXT: br i1 [[EXITCOND]], label [[TMP8:%.*]], label [[TMP1]] 375; CHECK: 8: 376; CHECK-NEXT: ret void 377; 378 br label %1 379 380; <label>:1 ; preds = %1, %0 381 %.04 = phi ptr [ %src, %0 ], [ %2, %1 ] 382 %.013 = phi ptr [ %dst, %0 ], [ %6, %1 ] 383 %i.02 = phi i32 [ 0, %0 ], [ %7, %1 ] 384 %2 = getelementptr inbounds i16, ptr %.04, i64 1 385 %3 = load i16, ptr %.04, align 2 386 %4 = zext i16 %3 to i32 387 %5 = shl nuw nsw i32 %4, 7 388 %6 = getelementptr inbounds i32, ptr %.013, i64 1 389 store i32 %5, ptr %.013, align 4 390 %7 = add nsw i32 %i.02, 1 391 %exitcond = icmp eq i32 %7, 256 392 br i1 %exitcond, label %8, label %1 393 394; <label>:8 ; preds = %1 395 ret void 396} 397 398 399; We CAN vectorize this example because the pointers are marked as noalias. 400define void @example23b(ptr noalias nocapture %src, ptr noalias nocapture %dst) optsize { 401; CHECK-LABEL: @example23b( 402; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] 403; CHECK: vector.ph: 404; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] 405; CHECK: vector.body: 406; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] 407; CHECK-NEXT: [[OFFSET_IDX:%.*]] = shl i64 [[INDEX]], 1 408; CHECK-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, ptr [[SRC:%.*]], i64 [[OFFSET_IDX]] 409; CHECK-NEXT: [[OFFSET_IDX2:%.*]] = shl i64 [[INDEX]], 2 410; CHECK-NEXT: [[NEXT_GEP3:%.*]] = getelementptr i8, ptr [[DST:%.*]], i64 [[OFFSET_IDX2]] 411; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i16>, ptr [[NEXT_GEP]], align 2 412; CHECK-NEXT: [[TMP1:%.*]] = zext <4 x i16> [[WIDE_LOAD]] to <4 x i32> 413; CHECK-NEXT: [[TMP2:%.*]] = shl nuw nsw <4 x i32> [[TMP1]], splat (i32 7) 414; CHECK-NEXT: store <4 x i32> [[TMP2]], ptr [[NEXT_GEP3]], align 4 415; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 416; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i64 [[INDEX_NEXT]], 256 417; CHECK-NEXT: br i1 [[TMP3]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP10:![0-9]+]] 418; CHECK: middle.block: 419; CHECK-NEXT: br i1 true, label [[TMP5:%.*]], label [[SCALAR_PH]] 420; CHECK: scalar.ph: 421; CHECK-NEXT: br label [[TMP4:%.*]] 422; CHECK: 4: 423; CHECK-NEXT: br i1 poison, label [[TMP5]], label [[TMP4]], !llvm.loop [[LOOP11:![0-9]+]] 424; CHECK: 5: 425; CHECK-NEXT: ret void 426; 427 br label %1 428 429; <label>:1 ; preds = %1, %0 430 %.04 = phi ptr [ %src, %0 ], [ %2, %1 ] 431 %.013 = phi ptr [ %dst, %0 ], [ %6, %1 ] 432 %i.02 = phi i32 [ 0, %0 ], [ %7, %1 ] 433 %2 = getelementptr inbounds i16, ptr %.04, i64 1 434 %3 = load i16, ptr %.04, align 2 435 %4 = zext i16 %3 to i32 436 %5 = shl nuw nsw i32 %4, 7 437 %6 = getelementptr inbounds i32, ptr %.013, i64 1 438 store i32 %5, ptr %.013, align 4 439 %7 = add nsw i32 %i.02, 1 440 %exitcond = icmp eq i32 %7, 256 441 br i1 %exitcond, label %8, label %1 442 443; <label>:8 ; preds = %1 444 ret void 445} 446 447; We CAN vectorize this example by folding the tail it entails. 448define void @example23c(ptr noalias nocapture %src, ptr noalias nocapture %dst) optsize { 449; CHECK-LABEL: @example23c( 450; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] 451; CHECK: vector.ph: 452; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] 453; CHECK: vector.body: 454; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[PRED_STORE_CONTINUE15:%.*]] ] 455; CHECK-NEXT: [[OFFSET_IDX:%.*]] = shl i64 [[INDEX]], 1 456; CHECK-NEXT: [[OFFSET_IDX5:%.*]] = shl i64 [[INDEX]], 2 457; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i64> poison, i64 [[INDEX]], i64 0 458; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i64> [[BROADCAST_SPLATINSERT]], <4 x i64> poison, <4 x i32> zeroinitializer 459; CHECK-NEXT: [[VEC_IV:%.*]] = or disjoint <4 x i64> [[BROADCAST_SPLAT]], <i64 0, i64 1, i64 2, i64 3> 460; CHECK-NEXT: [[TMP1:%.*]] = icmp ult <4 x i64> [[VEC_IV]], splat (i64 257) 461; CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x i1> [[TMP1]], i64 0 462; CHECK-NEXT: br i1 [[TMP2]], label [[PRED_STORE_IF:%.*]], label [[PRED_STORE_CONTINUE:%.*]] 463; CHECK: pred.store.if: 464; CHECK-NEXT: [[NEXT_GEP6:%.*]] = getelementptr i8, ptr [[DST:%.*]], i64 [[OFFSET_IDX5]] 465; CHECK-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, ptr [[SRC:%.*]], i64 [[OFFSET_IDX]] 466; CHECK-NEXT: [[TMP3:%.*]] = load i16, ptr [[NEXT_GEP]], align 2 467; CHECK-NEXT: [[TMP4:%.*]] = zext i16 [[TMP3]] to i32 468; CHECK-NEXT: [[TMP5:%.*]] = shl nuw nsw i32 [[TMP4]], 7 469; CHECK-NEXT: store i32 [[TMP5]], ptr [[NEXT_GEP6]], align 4 470; CHECK-NEXT: br label [[PRED_STORE_CONTINUE]] 471; CHECK: pred.store.continue: 472; CHECK-NEXT: [[TMP6:%.*]] = extractelement <4 x i1> [[TMP1]], i64 1 473; CHECK-NEXT: br i1 [[TMP6]], label [[PRED_STORE_IF9:%.*]], label [[PRED_STORE_CONTINUE10:%.*]] 474; CHECK: pred.store.if9: 475; CHECK-NEXT: [[TMP7:%.*]] = or disjoint i64 [[OFFSET_IDX5]], 4 476; CHECK-NEXT: [[NEXT_GEP7:%.*]] = getelementptr i8, ptr [[DST]], i64 [[TMP7]] 477; CHECK-NEXT: [[TMP8:%.*]] = or disjoint i64 [[OFFSET_IDX]], 2 478; CHECK-NEXT: [[NEXT_GEP2:%.*]] = getelementptr i8, ptr [[SRC]], i64 [[TMP8]] 479; CHECK-NEXT: [[TMP9:%.*]] = load i16, ptr [[NEXT_GEP2]], align 2 480; CHECK-NEXT: [[TMP10:%.*]] = zext i16 [[TMP9]] to i32 481; CHECK-NEXT: [[TMP11:%.*]] = shl nuw nsw i32 [[TMP10]], 7 482; CHECK-NEXT: store i32 [[TMP11]], ptr [[NEXT_GEP7]], align 4 483; CHECK-NEXT: br label [[PRED_STORE_CONTINUE10]] 484; CHECK: pred.store.continue10: 485; CHECK-NEXT: [[TMP12:%.*]] = extractelement <4 x i1> [[TMP1]], i64 2 486; CHECK-NEXT: br i1 [[TMP12]], label [[PRED_STORE_IF12:%.*]], label [[PRED_STORE_CONTINUE12:%.*]] 487; CHECK: pred.store.if11: 488; CHECK-NEXT: [[TMP13:%.*]] = or disjoint i64 [[OFFSET_IDX5]], 8 489; CHECK-NEXT: [[NEXT_GEP8:%.*]] = getelementptr i8, ptr [[DST]], i64 [[TMP13]] 490; CHECK-NEXT: [[TMP14:%.*]] = or disjoint i64 [[OFFSET_IDX]], 4 491; CHECK-NEXT: [[NEXT_GEP3:%.*]] = getelementptr i8, ptr [[SRC]], i64 [[TMP14]] 492; CHECK-NEXT: [[TMP15:%.*]] = load i16, ptr [[NEXT_GEP3]], align 2 493; CHECK-NEXT: [[TMP16:%.*]] = zext i16 [[TMP15]] to i32 494; CHECK-NEXT: [[TMP17:%.*]] = shl nuw nsw i32 [[TMP16]], 7 495; CHECK-NEXT: store i32 [[TMP17]], ptr [[NEXT_GEP8]], align 4 496; CHECK-NEXT: br label [[PRED_STORE_CONTINUE12]] 497; CHECK: pred.store.continue12: 498; CHECK-NEXT: [[TMP18:%.*]] = extractelement <4 x i1> [[TMP1]], i64 3 499; CHECK-NEXT: br i1 [[TMP18]], label [[PRED_STORE_IF13:%.*]], label [[PRED_STORE_CONTINUE15]] 500; CHECK: pred.store.if13: 501; CHECK-NEXT: [[TMP19:%.*]] = or disjoint i64 [[OFFSET_IDX5]], 12 502; CHECK-NEXT: [[NEXT_GEP9:%.*]] = getelementptr i8, ptr [[DST]], i64 [[TMP19]] 503; CHECK-NEXT: [[TMP20:%.*]] = or disjoint i64 [[OFFSET_IDX]], 6 504; CHECK-NEXT: [[NEXT_GEP4:%.*]] = getelementptr i8, ptr [[SRC]], i64 [[TMP20]] 505; CHECK-NEXT: [[TMP21:%.*]] = load i16, ptr [[NEXT_GEP4]], align 2 506; CHECK-NEXT: [[TMP22:%.*]] = zext i16 [[TMP21]] to i32 507; CHECK-NEXT: [[TMP23:%.*]] = shl nuw nsw i32 [[TMP22]], 7 508; CHECK-NEXT: store i32 [[TMP23]], ptr [[NEXT_GEP9]], align 4 509; CHECK-NEXT: br label [[PRED_STORE_CONTINUE15]] 510; CHECK: pred.store.continue14: 511; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 512; CHECK-NEXT: [[TMP24:%.*]] = icmp eq i64 [[INDEX_NEXT]], 260 513; CHECK-NEXT: br i1 [[TMP24]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP12:![0-9]+]] 514; CHECK: middle.block: 515; CHECK-NEXT: br i1 true, label [[TMP26:%.*]], label [[SCALAR_PH]] 516; CHECK: scalar.ph: 517; CHECK-NEXT: br label [[TMP25:%.*]] 518; CHECK: 25: 519; CHECK-NEXT: br i1 poison, label [[TMP26]], label [[TMP25]], !llvm.loop [[LOOP13:![0-9]+]] 520; CHECK: 26: 521; CHECK-NEXT: ret void 522; 523 br label %1 524 525; <label>:1 ; preds = %1, %0 526 %.04 = phi ptr [ %src, %0 ], [ %2, %1 ] 527 %.013 = phi ptr [ %dst, %0 ], [ %6, %1 ] 528 %i.02 = phi i64 [ 0, %0 ], [ %7, %1 ] 529 %2 = getelementptr inbounds i16, ptr %.04, i64 1 530 %3 = load i16, ptr %.04, align 2 531 %4 = zext i16 %3 to i32 532 %5 = shl nuw nsw i32 %4, 7 533 %6 = getelementptr inbounds i32, ptr %.013, i64 1 534 store i32 %5, ptr %.013, align 4 535 %7 = add nsw i64 %i.02, 1 536 %exitcond = icmp eq i64 %7, 257 537 br i1 %exitcond, label %8, label %1 538 539; <label>:8 ; preds = %1 540 ret void 541} 542 543; We CAN'T vectorize this example because it would entail a tail and an 544; induction is used outside the loop. 545define i64 @example23d(ptr noalias nocapture %src, ptr noalias nocapture %dst) optsize { 546; CHECK-LABEL: @example23d( 547; CHECK-NEXT: br label [[TMP1:%.*]] 548; CHECK: 1: 549; CHECK-NEXT: [[DOT04:%.*]] = phi ptr [ [[SRC:%.*]], [[TMP0:%.*]] ], [ [[TMP2:%.*]], [[TMP1]] ] 550; CHECK-NEXT: [[DOT013:%.*]] = phi ptr [ [[DST:%.*]], [[TMP0]] ], [ [[TMP6:%.*]], [[TMP1]] ] 551; CHECK-NEXT: [[I_02:%.*]] = phi i64 [ 0, [[TMP0]] ], [ [[TMP7:%.*]], [[TMP1]] ] 552; CHECK-NEXT: [[TMP2]] = getelementptr inbounds nuw i8, ptr [[DOT04]], i64 2 553; CHECK-NEXT: [[TMP3:%.*]] = load i16, ptr [[DOT04]], align 2 554; CHECK-NEXT: [[TMP4:%.*]] = zext i16 [[TMP3]] to i32 555; CHECK-NEXT: [[TMP5:%.*]] = shl nuw nsw i32 [[TMP4]], 7 556; CHECK-NEXT: [[TMP6]] = getelementptr inbounds nuw i8, ptr [[DOT013]], i64 4 557; CHECK-NEXT: store i32 [[TMP5]], ptr [[DOT013]], align 4 558; CHECK-NEXT: [[TMP7]] = add nuw nsw i64 [[I_02]], 1 559; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i64 [[TMP7]], 257 560; CHECK-NEXT: br i1 [[EXITCOND]], label [[TMP8:%.*]], label [[TMP1]] 561; CHECK: 8: 562; CHECK-NEXT: ret i64 [[TMP7]] 563; 564 br label %1 565 566; <label>:1 ; preds = %1, %0 567 %.04 = phi ptr [ %src, %0 ], [ %2, %1 ] 568 %.013 = phi ptr [ %dst, %0 ], [ %6, %1 ] 569 %i.02 = phi i64 [ 0, %0 ], [ %7, %1 ] 570 %2 = getelementptr inbounds i16, ptr %.04, i64 1 571 %3 = load i16, ptr %.04, align 2 572 %4 = zext i16 %3 to i32 573 %5 = shl nuw nsw i32 %4, 7 574 %6 = getelementptr inbounds i32, ptr %.013, i64 1 575 store i32 %5, ptr %.013, align 4 576 %7 = add nsw i64 %i.02, 1 577 %exitcond = icmp eq i64 %7, 257 578 br i1 %exitcond, label %8, label %1 579 580; <label>:8 ; preds = %1 581 ret i64 %7 582} 583