1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 2; RUN: opt -S -force-vector-width=4 -passes=loop-vectorize -mcpu=haswell < %s | FileCheck %s 3 4target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128-ni:1" 5target triple = "x86_64-unknown-linux-gnu" 6 7;; This file includes tests for avoiding the need for a masked.load 8;; We don't need a masked.load for this due to deref facts, and can instead 9;; use a plain vector load. 10 11declare void @init(ptr nocapture nofree) 12 13;; For ease of explanation, this one demonstrates 14;; with a range check, but there are better lowering options specifically for 15;; this test (i.e. reducing the iteration space of the vector copy), so 16;; following tests are written more generically. 17define i32 @test_explicit_pred(i64 %len) { 18; CHECK-LABEL: @test_explicit_pred( 19; CHECK-NEXT: entry: 20; CHECK-NEXT: [[ALLOCA:%.*]] = alloca [4096 x i32], align 4 21; CHECK-NEXT: call void @init(ptr [[ALLOCA]]) 22; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] 23; CHECK: vector.ph: 24; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i64> poison, i64 [[LEN:%.*]], i64 0 25; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i64> [[BROADCAST_SPLATINSERT]], <4 x i64> poison, <4 x i32> zeroinitializer 26; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] 27; CHECK: vector.body: 28; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] 29; CHECK-NEXT: [[VEC_IND:%.*]] = phi <4 x i64> [ <i64 0, i64 1, i64 2, i64 3>, [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[VECTOR_BODY]] ] 30; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP16:%.*]], [[VECTOR_BODY]] ] 31; CHECK-NEXT: [[VEC_PHI4:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP17:%.*]], [[VECTOR_BODY]] ] 32; CHECK-NEXT: [[VEC_PHI5:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP18:%.*]], [[VECTOR_BODY]] ] 33; CHECK-NEXT: [[VEC_PHI6:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP19:%.*]], [[VECTOR_BODY]] ] 34; CHECK-NEXT: [[STEP_ADD:%.*]] = add <4 x i64> [[VEC_IND]], splat (i64 4) 35; CHECK-NEXT: [[STEP_ADD1:%.*]] = add <4 x i64> [[STEP_ADD]], splat (i64 4) 36; CHECK-NEXT: [[STEP_ADD2:%.*]] = add <4 x i64> [[STEP_ADD1]], splat (i64 4) 37; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 0 38; CHECK-NEXT: [[TMP4:%.*]] = icmp slt <4 x i64> [[VEC_IND]], [[BROADCAST_SPLAT]] 39; CHECK-NEXT: [[TMP5:%.*]] = icmp slt <4 x i64> [[STEP_ADD]], [[BROADCAST_SPLAT]] 40; CHECK-NEXT: [[TMP6:%.*]] = icmp slt <4 x i64> [[STEP_ADD1]], [[BROADCAST_SPLAT]] 41; CHECK-NEXT: [[TMP7:%.*]] = icmp slt <4 x i64> [[STEP_ADD2]], [[BROADCAST_SPLAT]] 42; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i32, ptr [[ALLOCA]], i64 [[TMP0]] 43; CHECK-NEXT: [[TMP12:%.*]] = getelementptr i32, ptr [[TMP8]], i32 0 44; CHECK-NEXT: [[TMP13:%.*]] = getelementptr i32, ptr [[TMP8]], i32 4 45; CHECK-NEXT: [[TMP14:%.*]] = getelementptr i32, ptr [[TMP8]], i32 8 46; CHECK-NEXT: [[TMP15:%.*]] = getelementptr i32, ptr [[TMP8]], i32 12 47; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP12]], align 4 48; CHECK-NEXT: [[WIDE_LOAD7:%.*]] = load <4 x i32>, ptr [[TMP13]], align 4 49; CHECK-NEXT: [[WIDE_LOAD8:%.*]] = load <4 x i32>, ptr [[TMP14]], align 4 50; CHECK-NEXT: [[WIDE_LOAD9:%.*]] = load <4 x i32>, ptr [[TMP15]], align 4 51; CHECK-NEXT: [[PREDPHI:%.*]] = select <4 x i1> [[TMP4]], <4 x i32> [[WIDE_LOAD]], <4 x i32> zeroinitializer 52; CHECK-NEXT: [[PREDPHI10:%.*]] = select <4 x i1> [[TMP5]], <4 x i32> [[WIDE_LOAD7]], <4 x i32> zeroinitializer 53; CHECK-NEXT: [[PREDPHI11:%.*]] = select <4 x i1> [[TMP6]], <4 x i32> [[WIDE_LOAD8]], <4 x i32> zeroinitializer 54; CHECK-NEXT: [[PREDPHI12:%.*]] = select <4 x i1> [[TMP7]], <4 x i32> [[WIDE_LOAD9]], <4 x i32> zeroinitializer 55; CHECK-NEXT: [[TMP16]] = add <4 x i32> [[VEC_PHI]], [[PREDPHI]] 56; CHECK-NEXT: [[TMP17]] = add <4 x i32> [[VEC_PHI4]], [[PREDPHI10]] 57; CHECK-NEXT: [[TMP18]] = add <4 x i32> [[VEC_PHI5]], [[PREDPHI11]] 58; CHECK-NEXT: [[TMP19]] = add <4 x i32> [[VEC_PHI6]], [[PREDPHI12]] 59; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16 60; CHECK-NEXT: [[VEC_IND_NEXT]] = add <4 x i64> [[STEP_ADD2]], splat (i64 4) 61; CHECK-NEXT: [[TMP20:%.*]] = icmp eq i64 [[INDEX_NEXT]], 4096 62; CHECK-NEXT: br i1 [[TMP20]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] 63; CHECK: middle.block: 64; CHECK-NEXT: [[BIN_RDX:%.*]] = add <4 x i32> [[TMP17]], [[TMP16]] 65; CHECK-NEXT: [[BIN_RDX13:%.*]] = add <4 x i32> [[TMP18]], [[BIN_RDX]] 66; CHECK-NEXT: [[BIN_RDX14:%.*]] = add <4 x i32> [[TMP19]], [[BIN_RDX13]] 67; CHECK-NEXT: [[TMP21:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[BIN_RDX14]]) 68; CHECK-NEXT: br i1 true, label [[LOOP_EXIT:%.*]], label [[SCALAR_PH]] 69; CHECK: scalar.ph: 70; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ 4096, [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ] 71; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP21]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY]] ] 72; CHECK-NEXT: br label [[LOOP:%.*]] 73; CHECK: loop: 74; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LATCH:%.*]] ] 75; CHECK-NEXT: [[ACCUM:%.*]] = phi i32 [ [[BC_MERGE_RDX]], [[SCALAR_PH]] ], [ [[ACCUM_NEXT:%.*]], [[LATCH]] ] 76; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1 77; CHECK-NEXT: [[EARLYCND:%.*]] = icmp slt i64 [[IV]], [[LEN]] 78; CHECK-NEXT: br i1 [[EARLYCND]], label [[PRED:%.*]], label [[LATCH]] 79; CHECK: pred: 80; CHECK-NEXT: [[ADDR:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[IV]] 81; CHECK-NEXT: [[VAL:%.*]] = load i32, ptr [[ADDR]], align 4 82; CHECK-NEXT: br label [[LATCH]] 83; CHECK: latch: 84; CHECK-NEXT: [[VAL_PHI:%.*]] = phi i32 [ 0, [[LOOP]] ], [ [[VAL]], [[PRED]] ] 85; CHECK-NEXT: [[ACCUM_NEXT]] = add i32 [[ACCUM]], [[VAL_PHI]] 86; CHECK-NEXT: [[EXIT:%.*]] = icmp ugt i64 [[IV]], 4094 87; CHECK-NEXT: br i1 [[EXIT]], label [[LOOP_EXIT]], label [[LOOP]], !llvm.loop [[LOOP3:![0-9]+]] 88; CHECK: loop_exit: 89; CHECK-NEXT: [[ACCUM_NEXT_LCSSA:%.*]] = phi i32 [ [[ACCUM_NEXT]], [[LATCH]] ], [ [[TMP21]], [[MIDDLE_BLOCK]] ] 90; CHECK-NEXT: ret i32 [[ACCUM_NEXT_LCSSA]] 91; 92entry: 93 %alloca = alloca [4096 x i32] 94 call void @init(ptr %alloca) 95 br label %loop 96loop: 97 %iv = phi i64 [ 0, %entry ], [ %iv.next, %latch ] 98 %accum = phi i32 [ 0, %entry ], [ %accum.next, %latch ] 99 %iv.next = add i64 %iv, 1 100 %earlycnd = icmp slt i64 %iv, %len 101 br i1 %earlycnd, label %pred, label %latch 102pred: 103 %addr = getelementptr inbounds i32, ptr %alloca, i64 %iv 104 %val = load i32, ptr %addr 105 br label %latch 106latch: 107 %val.phi = phi i32 [0, %loop], [%val, %pred] 108 %accum.next = add i32 %accum, %val.phi 109 %exit = icmp ugt i64 %iv, 4094 110 br i1 %exit, label %loop_exit, label %loop 111 112loop_exit: 113 ret i32 %accum.next 114} 115 116;; Similiar to the above, but without an analyzeable condition. 117define i32 @test_explicit_pred_generic(i64 %len, ptr %test_base) { 118; CHECK-LABEL: @test_explicit_pred_generic( 119; CHECK-NEXT: entry: 120; CHECK-NEXT: [[ALLOCA:%.*]] = alloca [4096 x i32], align 4 121; CHECK-NEXT: call void @init(ptr [[ALLOCA]]) 122; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] 123; CHECK: vector.ph: 124; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] 125; CHECK: vector.body: 126; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] 127; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP72:%.*]], [[VECTOR_BODY]] ] 128; CHECK-NEXT: [[VEC_PHI1:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP73:%.*]], [[VECTOR_BODY]] ] 129; CHECK-NEXT: [[VEC_PHI2:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP74:%.*]], [[VECTOR_BODY]] ] 130; CHECK-NEXT: [[VEC_PHI3:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP75:%.*]], [[VECTOR_BODY]] ] 131; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 0 132; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[INDEX]], 1 133; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[INDEX]], 2 134; CHECK-NEXT: [[TMP3:%.*]] = add i64 [[INDEX]], 3 135; CHECK-NEXT: [[TMP4:%.*]] = add i64 [[INDEX]], 4 136; CHECK-NEXT: [[TMP5:%.*]] = add i64 [[INDEX]], 5 137; CHECK-NEXT: [[TMP6:%.*]] = add i64 [[INDEX]], 6 138; CHECK-NEXT: [[TMP7:%.*]] = add i64 [[INDEX]], 7 139; CHECK-NEXT: [[TMP8:%.*]] = add i64 [[INDEX]], 8 140; CHECK-NEXT: [[TMP9:%.*]] = add i64 [[INDEX]], 9 141; CHECK-NEXT: [[TMP10:%.*]] = add i64 [[INDEX]], 10 142; CHECK-NEXT: [[TMP11:%.*]] = add i64 [[INDEX]], 11 143; CHECK-NEXT: [[TMP12:%.*]] = add i64 [[INDEX]], 12 144; CHECK-NEXT: [[TMP13:%.*]] = add i64 [[INDEX]], 13 145; CHECK-NEXT: [[TMP14:%.*]] = add i64 [[INDEX]], 14 146; CHECK-NEXT: [[TMP15:%.*]] = add i64 [[INDEX]], 15 147; CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE:%.*]], i64 [[TMP0]] 148; CHECK-NEXT: [[TMP17:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP1]] 149; CHECK-NEXT: [[TMP18:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP2]] 150; CHECK-NEXT: [[TMP19:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP3]] 151; CHECK-NEXT: [[TMP20:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP4]] 152; CHECK-NEXT: [[TMP21:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP5]] 153; CHECK-NEXT: [[TMP22:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP6]] 154; CHECK-NEXT: [[TMP23:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP7]] 155; CHECK-NEXT: [[TMP24:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP8]] 156; CHECK-NEXT: [[TMP25:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP9]] 157; CHECK-NEXT: [[TMP26:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP10]] 158; CHECK-NEXT: [[TMP27:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP11]] 159; CHECK-NEXT: [[TMP28:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP12]] 160; CHECK-NEXT: [[TMP29:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP13]] 161; CHECK-NEXT: [[TMP30:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP14]] 162; CHECK-NEXT: [[TMP31:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP15]] 163; CHECK-NEXT: [[TMP32:%.*]] = load i1, ptr [[TMP16]], align 1 164; CHECK-NEXT: [[TMP33:%.*]] = load i1, ptr [[TMP17]], align 1 165; CHECK-NEXT: [[TMP34:%.*]] = load i1, ptr [[TMP18]], align 1 166; CHECK-NEXT: [[TMP35:%.*]] = load i1, ptr [[TMP19]], align 1 167; CHECK-NEXT: [[TMP36:%.*]] = insertelement <4 x i1> poison, i1 [[TMP32]], i32 0 168; CHECK-NEXT: [[TMP37:%.*]] = insertelement <4 x i1> [[TMP36]], i1 [[TMP33]], i32 1 169; CHECK-NEXT: [[TMP38:%.*]] = insertelement <4 x i1> [[TMP37]], i1 [[TMP34]], i32 2 170; CHECK-NEXT: [[TMP39:%.*]] = insertelement <4 x i1> [[TMP38]], i1 [[TMP35]], i32 3 171; CHECK-NEXT: [[TMP40:%.*]] = load i1, ptr [[TMP20]], align 1 172; CHECK-NEXT: [[TMP41:%.*]] = load i1, ptr [[TMP21]], align 1 173; CHECK-NEXT: [[TMP42:%.*]] = load i1, ptr [[TMP22]], align 1 174; CHECK-NEXT: [[TMP43:%.*]] = load i1, ptr [[TMP23]], align 1 175; CHECK-NEXT: [[TMP44:%.*]] = insertelement <4 x i1> poison, i1 [[TMP40]], i32 0 176; CHECK-NEXT: [[TMP45:%.*]] = insertelement <4 x i1> [[TMP44]], i1 [[TMP41]], i32 1 177; CHECK-NEXT: [[TMP46:%.*]] = insertelement <4 x i1> [[TMP45]], i1 [[TMP42]], i32 2 178; CHECK-NEXT: [[TMP47:%.*]] = insertelement <4 x i1> [[TMP46]], i1 [[TMP43]], i32 3 179; CHECK-NEXT: [[TMP48:%.*]] = load i1, ptr [[TMP24]], align 1 180; CHECK-NEXT: [[TMP49:%.*]] = load i1, ptr [[TMP25]], align 1 181; CHECK-NEXT: [[TMP50:%.*]] = load i1, ptr [[TMP26]], align 1 182; CHECK-NEXT: [[TMP51:%.*]] = load i1, ptr [[TMP27]], align 1 183; CHECK-NEXT: [[TMP52:%.*]] = insertelement <4 x i1> poison, i1 [[TMP48]], i32 0 184; CHECK-NEXT: [[TMP53:%.*]] = insertelement <4 x i1> [[TMP52]], i1 [[TMP49]], i32 1 185; CHECK-NEXT: [[TMP54:%.*]] = insertelement <4 x i1> [[TMP53]], i1 [[TMP50]], i32 2 186; CHECK-NEXT: [[TMP55:%.*]] = insertelement <4 x i1> [[TMP54]], i1 [[TMP51]], i32 3 187; CHECK-NEXT: [[TMP56:%.*]] = load i1, ptr [[TMP28]], align 1 188; CHECK-NEXT: [[TMP57:%.*]] = load i1, ptr [[TMP29]], align 1 189; CHECK-NEXT: [[TMP58:%.*]] = load i1, ptr [[TMP30]], align 1 190; CHECK-NEXT: [[TMP59:%.*]] = load i1, ptr [[TMP31]], align 1 191; CHECK-NEXT: [[TMP60:%.*]] = insertelement <4 x i1> poison, i1 [[TMP56]], i32 0 192; CHECK-NEXT: [[TMP61:%.*]] = insertelement <4 x i1> [[TMP60]], i1 [[TMP57]], i32 1 193; CHECK-NEXT: [[TMP62:%.*]] = insertelement <4 x i1> [[TMP61]], i1 [[TMP58]], i32 2 194; CHECK-NEXT: [[TMP63:%.*]] = insertelement <4 x i1> [[TMP62]], i1 [[TMP59]], i32 3 195; CHECK-NEXT: [[TMP64:%.*]] = getelementptr i32, ptr [[ALLOCA]], i64 [[TMP0]] 196; CHECK-NEXT: [[TMP68:%.*]] = getelementptr i32, ptr [[TMP64]], i32 0 197; CHECK-NEXT: [[TMP69:%.*]] = getelementptr i32, ptr [[TMP64]], i32 4 198; CHECK-NEXT: [[TMP70:%.*]] = getelementptr i32, ptr [[TMP64]], i32 8 199; CHECK-NEXT: [[TMP71:%.*]] = getelementptr i32, ptr [[TMP64]], i32 12 200; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP68]], align 4 201; CHECK-NEXT: [[WIDE_LOAD4:%.*]] = load <4 x i32>, ptr [[TMP69]], align 4 202; CHECK-NEXT: [[WIDE_LOAD5:%.*]] = load <4 x i32>, ptr [[TMP70]], align 4 203; CHECK-NEXT: [[WIDE_LOAD6:%.*]] = load <4 x i32>, ptr [[TMP71]], align 4 204; CHECK-NEXT: [[PREDPHI:%.*]] = select <4 x i1> [[TMP39]], <4 x i32> [[WIDE_LOAD]], <4 x i32> zeroinitializer 205; CHECK-NEXT: [[PREDPHI7:%.*]] = select <4 x i1> [[TMP47]], <4 x i32> [[WIDE_LOAD4]], <4 x i32> zeroinitializer 206; CHECK-NEXT: [[PREDPHI8:%.*]] = select <4 x i1> [[TMP55]], <4 x i32> [[WIDE_LOAD5]], <4 x i32> zeroinitializer 207; CHECK-NEXT: [[PREDPHI9:%.*]] = select <4 x i1> [[TMP63]], <4 x i32> [[WIDE_LOAD6]], <4 x i32> zeroinitializer 208; CHECK-NEXT: [[TMP72]] = add <4 x i32> [[VEC_PHI]], [[PREDPHI]] 209; CHECK-NEXT: [[TMP73]] = add <4 x i32> [[VEC_PHI1]], [[PREDPHI7]] 210; CHECK-NEXT: [[TMP74]] = add <4 x i32> [[VEC_PHI2]], [[PREDPHI8]] 211; CHECK-NEXT: [[TMP75]] = add <4 x i32> [[VEC_PHI3]], [[PREDPHI9]] 212; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16 213; CHECK-NEXT: [[TMP76:%.*]] = icmp eq i64 [[INDEX_NEXT]], 4096 214; CHECK-NEXT: br i1 [[TMP76]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]] 215; CHECK: middle.block: 216; CHECK-NEXT: [[BIN_RDX:%.*]] = add <4 x i32> [[TMP73]], [[TMP72]] 217; CHECK-NEXT: [[BIN_RDX10:%.*]] = add <4 x i32> [[TMP74]], [[BIN_RDX]] 218; CHECK-NEXT: [[BIN_RDX11:%.*]] = add <4 x i32> [[TMP75]], [[BIN_RDX10]] 219; CHECK-NEXT: [[TMP77:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[BIN_RDX11]]) 220; CHECK-NEXT: br i1 true, label [[LOOP_EXIT:%.*]], label [[SCALAR_PH]] 221; CHECK: scalar.ph: 222; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ 4096, [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ] 223; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP77]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY]] ] 224; CHECK-NEXT: br label [[LOOP:%.*]] 225; CHECK: loop: 226; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LATCH:%.*]] ] 227; CHECK-NEXT: [[ACCUM:%.*]] = phi i32 [ [[BC_MERGE_RDX]], [[SCALAR_PH]] ], [ [[ACCUM_NEXT:%.*]], [[LATCH]] ] 228; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1 229; CHECK-NEXT: [[TEST_ADDR:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[IV]] 230; CHECK-NEXT: [[EARLYCND:%.*]] = load i1, ptr [[TEST_ADDR]], align 1 231; CHECK-NEXT: br i1 [[EARLYCND]], label [[PRED:%.*]], label [[LATCH]] 232; CHECK: pred: 233; CHECK-NEXT: [[ADDR:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[IV]] 234; CHECK-NEXT: [[VAL:%.*]] = load i32, ptr [[ADDR]], align 4 235; CHECK-NEXT: br label [[LATCH]] 236; CHECK: latch: 237; CHECK-NEXT: [[VAL_PHI:%.*]] = phi i32 [ 0, [[LOOP]] ], [ [[VAL]], [[PRED]] ] 238; CHECK-NEXT: [[ACCUM_NEXT]] = add i32 [[ACCUM]], [[VAL_PHI]] 239; CHECK-NEXT: [[EXIT:%.*]] = icmp ugt i64 [[IV]], 4094 240; CHECK-NEXT: br i1 [[EXIT]], label [[LOOP_EXIT]], label [[LOOP]], !llvm.loop [[LOOP5:![0-9]+]] 241; CHECK: loop_exit: 242; CHECK-NEXT: [[ACCUM_NEXT_LCSSA:%.*]] = phi i32 [ [[ACCUM_NEXT]], [[LATCH]] ], [ [[TMP77]], [[MIDDLE_BLOCK]] ] 243; CHECK-NEXT: ret i32 [[ACCUM_NEXT_LCSSA]] 244; 245entry: 246 %alloca = alloca [4096 x i32] 247 call void @init(ptr %alloca) 248 br label %loop 249loop: 250 %iv = phi i64 [ 0, %entry ], [ %iv.next, %latch ] 251 %accum = phi i32 [ 0, %entry ], [ %accum.next, %latch ] 252 %iv.next = add i64 %iv, 1 253 %test_addr = getelementptr inbounds i1, ptr %test_base, i64 %iv 254 %earlycnd = load i1, ptr %test_addr 255 br i1 %earlycnd, label %pred, label %latch 256pred: 257 %addr = getelementptr inbounds i32, ptr %alloca, i64 %iv 258 %val = load i32, ptr %addr 259 br label %latch 260latch: 261 %val.phi = phi i32 [0, %loop], [%val, %pred] 262 %accum.next = add i32 %accum, %val.phi 263 %exit = icmp ugt i64 %iv, 4094 264 br i1 %exit, label %loop_exit, label %loop 265 266loop_exit: 267 ret i32 %accum.next 268} 269 270; Trivial case where the address loaded from it loop invariant (and yes, 271; there are better lowerings, this is a test of robustness of vectorization, 272; nothing more.) 273; TODO: currently shows predication which can be removed 274define i32 @test_invariant_address(i64 %len, ptr %test_base) { 275; CHECK-LABEL: @test_invariant_address( 276; CHECK-NEXT: entry: 277; CHECK-NEXT: [[ALLOCA:%.*]] = alloca [4096 x i32], align 4 278; CHECK-NEXT: call void @init(ptr [[ALLOCA]]) 279; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] 280; CHECK: vector.ph: 281; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] 282; CHECK: vector.body: 283; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] 284; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP96:%.*]], [[VECTOR_BODY]] ] 285; CHECK-NEXT: [[VEC_PHI1:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP97:%.*]], [[VECTOR_BODY]] ] 286; CHECK-NEXT: [[VEC_PHI2:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP98:%.*]], [[VECTOR_BODY]] ] 287; CHECK-NEXT: [[VEC_PHI3:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP99:%.*]], [[VECTOR_BODY]] ] 288; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 0 289; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[INDEX]], 1 290; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[INDEX]], 2 291; CHECK-NEXT: [[TMP3:%.*]] = add i64 [[INDEX]], 3 292; CHECK-NEXT: [[TMP4:%.*]] = add i64 [[INDEX]], 4 293; CHECK-NEXT: [[TMP5:%.*]] = add i64 [[INDEX]], 5 294; CHECK-NEXT: [[TMP6:%.*]] = add i64 [[INDEX]], 6 295; CHECK-NEXT: [[TMP7:%.*]] = add i64 [[INDEX]], 7 296; CHECK-NEXT: [[TMP8:%.*]] = add i64 [[INDEX]], 8 297; CHECK-NEXT: [[TMP9:%.*]] = add i64 [[INDEX]], 9 298; CHECK-NEXT: [[TMP10:%.*]] = add i64 [[INDEX]], 10 299; CHECK-NEXT: [[TMP11:%.*]] = add i64 [[INDEX]], 11 300; CHECK-NEXT: [[TMP12:%.*]] = add i64 [[INDEX]], 12 301; CHECK-NEXT: [[TMP13:%.*]] = add i64 [[INDEX]], 13 302; CHECK-NEXT: [[TMP14:%.*]] = add i64 [[INDEX]], 14 303; CHECK-NEXT: [[TMP15:%.*]] = add i64 [[INDEX]], 15 304; CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE:%.*]], i64 [[TMP0]] 305; CHECK-NEXT: [[TMP17:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP1]] 306; CHECK-NEXT: [[TMP18:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP2]] 307; CHECK-NEXT: [[TMP19:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP3]] 308; CHECK-NEXT: [[TMP20:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP4]] 309; CHECK-NEXT: [[TMP21:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP5]] 310; CHECK-NEXT: [[TMP22:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP6]] 311; CHECK-NEXT: [[TMP23:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP7]] 312; CHECK-NEXT: [[TMP24:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP8]] 313; CHECK-NEXT: [[TMP25:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP9]] 314; CHECK-NEXT: [[TMP26:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP10]] 315; CHECK-NEXT: [[TMP27:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP11]] 316; CHECK-NEXT: [[TMP28:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP12]] 317; CHECK-NEXT: [[TMP29:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP13]] 318; CHECK-NEXT: [[TMP30:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP14]] 319; CHECK-NEXT: [[TMP31:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP15]] 320; CHECK-NEXT: [[TMP32:%.*]] = load i1, ptr [[TMP16]], align 1 321; CHECK-NEXT: [[TMP33:%.*]] = load i1, ptr [[TMP17]], align 1 322; CHECK-NEXT: [[TMP34:%.*]] = load i1, ptr [[TMP18]], align 1 323; CHECK-NEXT: [[TMP35:%.*]] = load i1, ptr [[TMP19]], align 1 324; CHECK-NEXT: [[TMP36:%.*]] = insertelement <4 x i1> poison, i1 [[TMP32]], i32 0 325; CHECK-NEXT: [[TMP37:%.*]] = insertelement <4 x i1> [[TMP36]], i1 [[TMP33]], i32 1 326; CHECK-NEXT: [[TMP38:%.*]] = insertelement <4 x i1> [[TMP37]], i1 [[TMP34]], i32 2 327; CHECK-NEXT: [[TMP39:%.*]] = insertelement <4 x i1> [[TMP38]], i1 [[TMP35]], i32 3 328; CHECK-NEXT: [[TMP40:%.*]] = load i1, ptr [[TMP20]], align 1 329; CHECK-NEXT: [[TMP41:%.*]] = load i1, ptr [[TMP21]], align 1 330; CHECK-NEXT: [[TMP42:%.*]] = load i1, ptr [[TMP22]], align 1 331; CHECK-NEXT: [[TMP43:%.*]] = load i1, ptr [[TMP23]], align 1 332; CHECK-NEXT: [[TMP44:%.*]] = insertelement <4 x i1> poison, i1 [[TMP40]], i32 0 333; CHECK-NEXT: [[TMP45:%.*]] = insertelement <4 x i1> [[TMP44]], i1 [[TMP41]], i32 1 334; CHECK-NEXT: [[TMP46:%.*]] = insertelement <4 x i1> [[TMP45]], i1 [[TMP42]], i32 2 335; CHECK-NEXT: [[TMP47:%.*]] = insertelement <4 x i1> [[TMP46]], i1 [[TMP43]], i32 3 336; CHECK-NEXT: [[TMP48:%.*]] = load i1, ptr [[TMP24]], align 1 337; CHECK-NEXT: [[TMP49:%.*]] = load i1, ptr [[TMP25]], align 1 338; CHECK-NEXT: [[TMP50:%.*]] = load i1, ptr [[TMP26]], align 1 339; CHECK-NEXT: [[TMP51:%.*]] = load i1, ptr [[TMP27]], align 1 340; CHECK-NEXT: [[TMP52:%.*]] = insertelement <4 x i1> poison, i1 [[TMP48]], i32 0 341; CHECK-NEXT: [[TMP53:%.*]] = insertelement <4 x i1> [[TMP52]], i1 [[TMP49]], i32 1 342; CHECK-NEXT: [[TMP54:%.*]] = insertelement <4 x i1> [[TMP53]], i1 [[TMP50]], i32 2 343; CHECK-NEXT: [[TMP55:%.*]] = insertelement <4 x i1> [[TMP54]], i1 [[TMP51]], i32 3 344; CHECK-NEXT: [[TMP56:%.*]] = load i1, ptr [[TMP28]], align 1 345; CHECK-NEXT: [[TMP57:%.*]] = load i1, ptr [[TMP29]], align 1 346; CHECK-NEXT: [[TMP58:%.*]] = load i1, ptr [[TMP30]], align 1 347; CHECK-NEXT: [[TMP59:%.*]] = load i1, ptr [[TMP31]], align 1 348; CHECK-NEXT: [[TMP60:%.*]] = insertelement <4 x i1> poison, i1 [[TMP56]], i32 0 349; CHECK-NEXT: [[TMP61:%.*]] = insertelement <4 x i1> [[TMP60]], i1 [[TMP57]], i32 1 350; CHECK-NEXT: [[TMP62:%.*]] = insertelement <4 x i1> [[TMP61]], i1 [[TMP58]], i32 2 351; CHECK-NEXT: [[TMP63:%.*]] = insertelement <4 x i1> [[TMP62]], i1 [[TMP59]], i32 3 352; CHECK-NEXT: [[TMP64:%.*]] = load i32, ptr [[ALLOCA]], align 4 353; CHECK-NEXT: [[TMP65:%.*]] = load i32, ptr [[ALLOCA]], align 4 354; CHECK-NEXT: [[TMP66:%.*]] = load i32, ptr [[ALLOCA]], align 4 355; CHECK-NEXT: [[TMP67:%.*]] = load i32, ptr [[ALLOCA]], align 4 356; CHECK-NEXT: [[TMP68:%.*]] = insertelement <4 x i32> poison, i32 [[TMP64]], i32 0 357; CHECK-NEXT: [[TMP69:%.*]] = insertelement <4 x i32> [[TMP68]], i32 [[TMP65]], i32 1 358; CHECK-NEXT: [[TMP70:%.*]] = insertelement <4 x i32> [[TMP69]], i32 [[TMP66]], i32 2 359; CHECK-NEXT: [[TMP71:%.*]] = insertelement <4 x i32> [[TMP70]], i32 [[TMP67]], i32 3 360; CHECK-NEXT: [[TMP72:%.*]] = load i32, ptr [[ALLOCA]], align 4 361; CHECK-NEXT: [[TMP73:%.*]] = load i32, ptr [[ALLOCA]], align 4 362; CHECK-NEXT: [[TMP74:%.*]] = load i32, ptr [[ALLOCA]], align 4 363; CHECK-NEXT: [[TMP75:%.*]] = load i32, ptr [[ALLOCA]], align 4 364; CHECK-NEXT: [[TMP76:%.*]] = insertelement <4 x i32> poison, i32 [[TMP72]], i32 0 365; CHECK-NEXT: [[TMP77:%.*]] = insertelement <4 x i32> [[TMP76]], i32 [[TMP73]], i32 1 366; CHECK-NEXT: [[TMP78:%.*]] = insertelement <4 x i32> [[TMP77]], i32 [[TMP74]], i32 2 367; CHECK-NEXT: [[TMP79:%.*]] = insertelement <4 x i32> [[TMP78]], i32 [[TMP75]], i32 3 368; CHECK-NEXT: [[TMP80:%.*]] = load i32, ptr [[ALLOCA]], align 4 369; CHECK-NEXT: [[TMP81:%.*]] = load i32, ptr [[ALLOCA]], align 4 370; CHECK-NEXT: [[TMP82:%.*]] = load i32, ptr [[ALLOCA]], align 4 371; CHECK-NEXT: [[TMP83:%.*]] = load i32, ptr [[ALLOCA]], align 4 372; CHECK-NEXT: [[TMP84:%.*]] = insertelement <4 x i32> poison, i32 [[TMP80]], i32 0 373; CHECK-NEXT: [[TMP85:%.*]] = insertelement <4 x i32> [[TMP84]], i32 [[TMP81]], i32 1 374; CHECK-NEXT: [[TMP86:%.*]] = insertelement <4 x i32> [[TMP85]], i32 [[TMP82]], i32 2 375; CHECK-NEXT: [[TMP87:%.*]] = insertelement <4 x i32> [[TMP86]], i32 [[TMP83]], i32 3 376; CHECK-NEXT: [[TMP88:%.*]] = load i32, ptr [[ALLOCA]], align 4 377; CHECK-NEXT: [[TMP89:%.*]] = load i32, ptr [[ALLOCA]], align 4 378; CHECK-NEXT: [[TMP90:%.*]] = load i32, ptr [[ALLOCA]], align 4 379; CHECK-NEXT: [[TMP91:%.*]] = load i32, ptr [[ALLOCA]], align 4 380; CHECK-NEXT: [[TMP92:%.*]] = insertelement <4 x i32> poison, i32 [[TMP88]], i32 0 381; CHECK-NEXT: [[TMP93:%.*]] = insertelement <4 x i32> [[TMP92]], i32 [[TMP89]], i32 1 382; CHECK-NEXT: [[TMP94:%.*]] = insertelement <4 x i32> [[TMP93]], i32 [[TMP90]], i32 2 383; CHECK-NEXT: [[TMP95:%.*]] = insertelement <4 x i32> [[TMP94]], i32 [[TMP91]], i32 3 384; CHECK-NEXT: [[PREDPHI:%.*]] = select <4 x i1> [[TMP39]], <4 x i32> [[TMP71]], <4 x i32> zeroinitializer 385; CHECK-NEXT: [[PREDPHI4:%.*]] = select <4 x i1> [[TMP47]], <4 x i32> [[TMP79]], <4 x i32> zeroinitializer 386; CHECK-NEXT: [[PREDPHI5:%.*]] = select <4 x i1> [[TMP55]], <4 x i32> [[TMP87]], <4 x i32> zeroinitializer 387; CHECK-NEXT: [[PREDPHI6:%.*]] = select <4 x i1> [[TMP63]], <4 x i32> [[TMP95]], <4 x i32> zeroinitializer 388; CHECK-NEXT: [[TMP96]] = add <4 x i32> [[VEC_PHI]], [[PREDPHI]] 389; CHECK-NEXT: [[TMP97]] = add <4 x i32> [[VEC_PHI1]], [[PREDPHI4]] 390; CHECK-NEXT: [[TMP98]] = add <4 x i32> [[VEC_PHI2]], [[PREDPHI5]] 391; CHECK-NEXT: [[TMP99]] = add <4 x i32> [[VEC_PHI3]], [[PREDPHI6]] 392; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16 393; CHECK-NEXT: [[TMP100:%.*]] = icmp eq i64 [[INDEX_NEXT]], 4096 394; CHECK-NEXT: br i1 [[TMP100]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]] 395; CHECK: middle.block: 396; CHECK-NEXT: [[BIN_RDX:%.*]] = add <4 x i32> [[TMP97]], [[TMP96]] 397; CHECK-NEXT: [[BIN_RDX7:%.*]] = add <4 x i32> [[TMP98]], [[BIN_RDX]] 398; CHECK-NEXT: [[BIN_RDX8:%.*]] = add <4 x i32> [[TMP99]], [[BIN_RDX7]] 399; CHECK-NEXT: [[TMP101:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[BIN_RDX8]]) 400; CHECK-NEXT: br i1 true, label [[LOOP_EXIT:%.*]], label [[SCALAR_PH]] 401; CHECK: scalar.ph: 402; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ 4096, [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ] 403; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP101]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY]] ] 404; CHECK-NEXT: br label [[LOOP:%.*]] 405; CHECK: loop: 406; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LATCH:%.*]] ] 407; CHECK-NEXT: [[ACCUM:%.*]] = phi i32 [ [[BC_MERGE_RDX]], [[SCALAR_PH]] ], [ [[ACCUM_NEXT:%.*]], [[LATCH]] ] 408; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1 409; CHECK-NEXT: [[TEST_ADDR:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[IV]] 410; CHECK-NEXT: [[EARLYCND:%.*]] = load i1, ptr [[TEST_ADDR]], align 1 411; CHECK-NEXT: br i1 [[EARLYCND]], label [[PRED:%.*]], label [[LATCH]] 412; CHECK: pred: 413; CHECK-NEXT: [[VAL:%.*]] = load i32, ptr [[ALLOCA]], align 4 414; CHECK-NEXT: br label [[LATCH]] 415; CHECK: latch: 416; CHECK-NEXT: [[VAL_PHI:%.*]] = phi i32 [ 0, [[LOOP]] ], [ [[VAL]], [[PRED]] ] 417; CHECK-NEXT: [[ACCUM_NEXT]] = add i32 [[ACCUM]], [[VAL_PHI]] 418; CHECK-NEXT: [[EXIT:%.*]] = icmp ugt i64 [[IV]], 4094 419; CHECK-NEXT: br i1 [[EXIT]], label [[LOOP_EXIT]], label [[LOOP]], !llvm.loop [[LOOP7:![0-9]+]] 420; CHECK: loop_exit: 421; CHECK-NEXT: [[ACCUM_NEXT_LCSSA:%.*]] = phi i32 [ [[ACCUM_NEXT]], [[LATCH]] ], [ [[TMP101]], [[MIDDLE_BLOCK]] ] 422; CHECK-NEXT: ret i32 [[ACCUM_NEXT_LCSSA]] 423; 424entry: 425 %alloca = alloca [4096 x i32] 426 call void @init(ptr %alloca) 427 br label %loop 428loop: 429 %iv = phi i64 [ 0, %entry ], [ %iv.next, %latch ] 430 %accum = phi i32 [ 0, %entry ], [ %accum.next, %latch ] 431 %iv.next = add i64 %iv, 1 432 %test_addr = getelementptr inbounds i1, ptr %test_base, i64 %iv 433 %earlycnd = load i1, ptr %test_addr 434 br i1 %earlycnd, label %pred, label %latch 435pred: 436 %val = load i32, ptr %alloca 437 br label %latch 438latch: 439 %val.phi = phi i32 [0, %loop], [%val, %pred] 440 %accum.next = add i32 %accum, %val.phi 441 %exit = icmp ugt i64 %iv, 4094 442 br i1 %exit, label %loop_exit, label %loop 443 444loop_exit: 445 ret i32 %accum.next 446} 447 448; Overlapping loads - Fails alignment checking, not dereferenceability 449define i32 @test_step_narrower_than_access(i64 %len, ptr %test_base) { 450; CHECK-LABEL: @test_step_narrower_than_access( 451; CHECK-NEXT: entry: 452; CHECK-NEXT: [[ALLOCA:%.*]] = alloca [4096 x i32], align 4 453; CHECK-NEXT: call void @init(ptr [[ALLOCA]]) 454; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] 455; CHECK: vector.ph: 456; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] 457; CHECK: vector.body: 458; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[PRED_LOAD_CONTINUE33:%.*]] ] 459; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP144:%.*]], [[PRED_LOAD_CONTINUE33]] ] 460; CHECK-NEXT: [[VEC_PHI1:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP145:%.*]], [[PRED_LOAD_CONTINUE33]] ] 461; CHECK-NEXT: [[VEC_PHI2:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP146:%.*]], [[PRED_LOAD_CONTINUE33]] ] 462; CHECK-NEXT: [[VEC_PHI3:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP147:%.*]], [[PRED_LOAD_CONTINUE33]] ] 463; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 0 464; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[INDEX]], 1 465; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[INDEX]], 2 466; CHECK-NEXT: [[TMP3:%.*]] = add i64 [[INDEX]], 3 467; CHECK-NEXT: [[TMP4:%.*]] = add i64 [[INDEX]], 4 468; CHECK-NEXT: [[TMP5:%.*]] = add i64 [[INDEX]], 5 469; CHECK-NEXT: [[TMP6:%.*]] = add i64 [[INDEX]], 6 470; CHECK-NEXT: [[TMP7:%.*]] = add i64 [[INDEX]], 7 471; CHECK-NEXT: [[TMP8:%.*]] = add i64 [[INDEX]], 8 472; CHECK-NEXT: [[TMP9:%.*]] = add i64 [[INDEX]], 9 473; CHECK-NEXT: [[TMP10:%.*]] = add i64 [[INDEX]], 10 474; CHECK-NEXT: [[TMP11:%.*]] = add i64 [[INDEX]], 11 475; CHECK-NEXT: [[TMP12:%.*]] = add i64 [[INDEX]], 12 476; CHECK-NEXT: [[TMP13:%.*]] = add i64 [[INDEX]], 13 477; CHECK-NEXT: [[TMP14:%.*]] = add i64 [[INDEX]], 14 478; CHECK-NEXT: [[TMP15:%.*]] = add i64 [[INDEX]], 15 479; CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE:%.*]], i64 [[TMP0]] 480; CHECK-NEXT: [[TMP17:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP1]] 481; CHECK-NEXT: [[TMP18:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP2]] 482; CHECK-NEXT: [[TMP19:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP3]] 483; CHECK-NEXT: [[TMP20:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP4]] 484; CHECK-NEXT: [[TMP21:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP5]] 485; CHECK-NEXT: [[TMP22:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP6]] 486; CHECK-NEXT: [[TMP23:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP7]] 487; CHECK-NEXT: [[TMP24:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP8]] 488; CHECK-NEXT: [[TMP25:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP9]] 489; CHECK-NEXT: [[TMP26:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP10]] 490; CHECK-NEXT: [[TMP27:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP11]] 491; CHECK-NEXT: [[TMP28:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP12]] 492; CHECK-NEXT: [[TMP29:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP13]] 493; CHECK-NEXT: [[TMP30:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP14]] 494; CHECK-NEXT: [[TMP31:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP15]] 495; CHECK-NEXT: [[TMP32:%.*]] = load i1, ptr [[TMP16]], align 1 496; CHECK-NEXT: [[TMP33:%.*]] = load i1, ptr [[TMP17]], align 1 497; CHECK-NEXT: [[TMP34:%.*]] = load i1, ptr [[TMP18]], align 1 498; CHECK-NEXT: [[TMP35:%.*]] = load i1, ptr [[TMP19]], align 1 499; CHECK-NEXT: [[TMP36:%.*]] = insertelement <4 x i1> poison, i1 [[TMP32]], i32 0 500; CHECK-NEXT: [[TMP37:%.*]] = insertelement <4 x i1> [[TMP36]], i1 [[TMP33]], i32 1 501; CHECK-NEXT: [[TMP38:%.*]] = insertelement <4 x i1> [[TMP37]], i1 [[TMP34]], i32 2 502; CHECK-NEXT: [[TMP39:%.*]] = insertelement <4 x i1> [[TMP38]], i1 [[TMP35]], i32 3 503; CHECK-NEXT: [[TMP40:%.*]] = load i1, ptr [[TMP20]], align 1 504; CHECK-NEXT: [[TMP41:%.*]] = load i1, ptr [[TMP21]], align 1 505; CHECK-NEXT: [[TMP42:%.*]] = load i1, ptr [[TMP22]], align 1 506; CHECK-NEXT: [[TMP43:%.*]] = load i1, ptr [[TMP23]], align 1 507; CHECK-NEXT: [[TMP44:%.*]] = insertelement <4 x i1> poison, i1 [[TMP40]], i32 0 508; CHECK-NEXT: [[TMP45:%.*]] = insertelement <4 x i1> [[TMP44]], i1 [[TMP41]], i32 1 509; CHECK-NEXT: [[TMP46:%.*]] = insertelement <4 x i1> [[TMP45]], i1 [[TMP42]], i32 2 510; CHECK-NEXT: [[TMP47:%.*]] = insertelement <4 x i1> [[TMP46]], i1 [[TMP43]], i32 3 511; CHECK-NEXT: [[TMP48:%.*]] = load i1, ptr [[TMP24]], align 1 512; CHECK-NEXT: [[TMP49:%.*]] = load i1, ptr [[TMP25]], align 1 513; CHECK-NEXT: [[TMP50:%.*]] = load i1, ptr [[TMP26]], align 1 514; CHECK-NEXT: [[TMP51:%.*]] = load i1, ptr [[TMP27]], align 1 515; CHECK-NEXT: [[TMP52:%.*]] = insertelement <4 x i1> poison, i1 [[TMP48]], i32 0 516; CHECK-NEXT: [[TMP53:%.*]] = insertelement <4 x i1> [[TMP52]], i1 [[TMP49]], i32 1 517; CHECK-NEXT: [[TMP54:%.*]] = insertelement <4 x i1> [[TMP53]], i1 [[TMP50]], i32 2 518; CHECK-NEXT: [[TMP55:%.*]] = insertelement <4 x i1> [[TMP54]], i1 [[TMP51]], i32 3 519; CHECK-NEXT: [[TMP56:%.*]] = load i1, ptr [[TMP28]], align 1 520; CHECK-NEXT: [[TMP57:%.*]] = load i1, ptr [[TMP29]], align 1 521; CHECK-NEXT: [[TMP58:%.*]] = load i1, ptr [[TMP30]], align 1 522; CHECK-NEXT: [[TMP59:%.*]] = load i1, ptr [[TMP31]], align 1 523; CHECK-NEXT: [[TMP60:%.*]] = insertelement <4 x i1> poison, i1 [[TMP56]], i32 0 524; CHECK-NEXT: [[TMP61:%.*]] = insertelement <4 x i1> [[TMP60]], i1 [[TMP57]], i32 1 525; CHECK-NEXT: [[TMP62:%.*]] = insertelement <4 x i1> [[TMP61]], i1 [[TMP58]], i32 2 526; CHECK-NEXT: [[TMP63:%.*]] = insertelement <4 x i1> [[TMP62]], i1 [[TMP59]], i32 3 527; CHECK-NEXT: br i1 [[TMP32]], label [[PRED_LOAD_IF:%.*]], label [[PRED_LOAD_CONTINUE:%.*]] 528; CHECK: pred.load.if: 529; CHECK-NEXT: [[TMP65:%.*]] = getelementptr inbounds i16, ptr [[ALLOCA]], i64 [[TMP0]] 530; CHECK-NEXT: [[TMP66:%.*]] = load i32, ptr [[TMP65]], align 4 531; CHECK-NEXT: [[TMP67:%.*]] = insertelement <4 x i32> poison, i32 [[TMP66]], i32 0 532; CHECK-NEXT: br label [[PRED_LOAD_CONTINUE]] 533; CHECK: pred.load.continue: 534; CHECK-NEXT: [[TMP68:%.*]] = phi <4 x i32> [ poison, [[VECTOR_BODY]] ], [ [[TMP67]], [[PRED_LOAD_IF]] ] 535; CHECK-NEXT: br i1 [[TMP33]], label [[PRED_LOAD_IF4:%.*]], label [[PRED_LOAD_CONTINUE5:%.*]] 536; CHECK: pred.load.if4: 537; CHECK-NEXT: [[TMP70:%.*]] = getelementptr inbounds i16, ptr [[ALLOCA]], i64 [[TMP1]] 538; CHECK-NEXT: [[TMP71:%.*]] = load i32, ptr [[TMP70]], align 4 539; CHECK-NEXT: [[TMP72:%.*]] = insertelement <4 x i32> [[TMP68]], i32 [[TMP71]], i32 1 540; CHECK-NEXT: br label [[PRED_LOAD_CONTINUE5]] 541; CHECK: pred.load.continue5: 542; CHECK-NEXT: [[TMP73:%.*]] = phi <4 x i32> [ [[TMP68]], [[PRED_LOAD_CONTINUE]] ], [ [[TMP72]], [[PRED_LOAD_IF4]] ] 543; CHECK-NEXT: br i1 [[TMP34]], label [[PRED_LOAD_IF6:%.*]], label [[PRED_LOAD_CONTINUE7:%.*]] 544; CHECK: pred.load.if6: 545; CHECK-NEXT: [[TMP75:%.*]] = getelementptr inbounds i16, ptr [[ALLOCA]], i64 [[TMP2]] 546; CHECK-NEXT: [[TMP76:%.*]] = load i32, ptr [[TMP75]], align 4 547; CHECK-NEXT: [[TMP77:%.*]] = insertelement <4 x i32> [[TMP73]], i32 [[TMP76]], i32 2 548; CHECK-NEXT: br label [[PRED_LOAD_CONTINUE7]] 549; CHECK: pred.load.continue7: 550; CHECK-NEXT: [[TMP78:%.*]] = phi <4 x i32> [ [[TMP73]], [[PRED_LOAD_CONTINUE5]] ], [ [[TMP77]], [[PRED_LOAD_IF6]] ] 551; CHECK-NEXT: br i1 [[TMP35]], label [[PRED_LOAD_IF8:%.*]], label [[PRED_LOAD_CONTINUE9:%.*]] 552; CHECK: pred.load.if8: 553; CHECK-NEXT: [[TMP80:%.*]] = getelementptr inbounds i16, ptr [[ALLOCA]], i64 [[TMP3]] 554; CHECK-NEXT: [[TMP81:%.*]] = load i32, ptr [[TMP80]], align 4 555; CHECK-NEXT: [[TMP82:%.*]] = insertelement <4 x i32> [[TMP78]], i32 [[TMP81]], i32 3 556; CHECK-NEXT: br label [[PRED_LOAD_CONTINUE9]] 557; CHECK: pred.load.continue9: 558; CHECK-NEXT: [[TMP83:%.*]] = phi <4 x i32> [ [[TMP78]], [[PRED_LOAD_CONTINUE7]] ], [ [[TMP82]], [[PRED_LOAD_IF8]] ] 559; CHECK-NEXT: br i1 [[TMP40]], label [[PRED_LOAD_IF10:%.*]], label [[PRED_LOAD_CONTINUE11:%.*]] 560; CHECK: pred.load.if10: 561; CHECK-NEXT: [[TMP85:%.*]] = getelementptr inbounds i16, ptr [[ALLOCA]], i64 [[TMP4]] 562; CHECK-NEXT: [[TMP86:%.*]] = load i32, ptr [[TMP85]], align 4 563; CHECK-NEXT: [[TMP87:%.*]] = insertelement <4 x i32> poison, i32 [[TMP86]], i32 0 564; CHECK-NEXT: br label [[PRED_LOAD_CONTINUE11]] 565; CHECK: pred.load.continue11: 566; CHECK-NEXT: [[TMP88:%.*]] = phi <4 x i32> [ poison, [[PRED_LOAD_CONTINUE9]] ], [ [[TMP87]], [[PRED_LOAD_IF10]] ] 567; CHECK-NEXT: br i1 [[TMP41]], label [[PRED_LOAD_IF12:%.*]], label [[PRED_LOAD_CONTINUE13:%.*]] 568; CHECK: pred.load.if12: 569; CHECK-NEXT: [[TMP90:%.*]] = getelementptr inbounds i16, ptr [[ALLOCA]], i64 [[TMP5]] 570; CHECK-NEXT: [[TMP91:%.*]] = load i32, ptr [[TMP90]], align 4 571; CHECK-NEXT: [[TMP92:%.*]] = insertelement <4 x i32> [[TMP88]], i32 [[TMP91]], i32 1 572; CHECK-NEXT: br label [[PRED_LOAD_CONTINUE13]] 573; CHECK: pred.load.continue13: 574; CHECK-NEXT: [[TMP93:%.*]] = phi <4 x i32> [ [[TMP88]], [[PRED_LOAD_CONTINUE11]] ], [ [[TMP92]], [[PRED_LOAD_IF12]] ] 575; CHECK-NEXT: br i1 [[TMP42]], label [[PRED_LOAD_IF14:%.*]], label [[PRED_LOAD_CONTINUE15:%.*]] 576; CHECK: pred.load.if14: 577; CHECK-NEXT: [[TMP95:%.*]] = getelementptr inbounds i16, ptr [[ALLOCA]], i64 [[TMP6]] 578; CHECK-NEXT: [[TMP96:%.*]] = load i32, ptr [[TMP95]], align 4 579; CHECK-NEXT: [[TMP97:%.*]] = insertelement <4 x i32> [[TMP93]], i32 [[TMP96]], i32 2 580; CHECK-NEXT: br label [[PRED_LOAD_CONTINUE15]] 581; CHECK: pred.load.continue15: 582; CHECK-NEXT: [[TMP98:%.*]] = phi <4 x i32> [ [[TMP93]], [[PRED_LOAD_CONTINUE13]] ], [ [[TMP97]], [[PRED_LOAD_IF14]] ] 583; CHECK-NEXT: br i1 [[TMP43]], label [[PRED_LOAD_IF16:%.*]], label [[PRED_LOAD_CONTINUE17:%.*]] 584; CHECK: pred.load.if16: 585; CHECK-NEXT: [[TMP100:%.*]] = getelementptr inbounds i16, ptr [[ALLOCA]], i64 [[TMP7]] 586; CHECK-NEXT: [[TMP101:%.*]] = load i32, ptr [[TMP100]], align 4 587; CHECK-NEXT: [[TMP102:%.*]] = insertelement <4 x i32> [[TMP98]], i32 [[TMP101]], i32 3 588; CHECK-NEXT: br label [[PRED_LOAD_CONTINUE17]] 589; CHECK: pred.load.continue17: 590; CHECK-NEXT: [[TMP103:%.*]] = phi <4 x i32> [ [[TMP98]], [[PRED_LOAD_CONTINUE15]] ], [ [[TMP102]], [[PRED_LOAD_IF16]] ] 591; CHECK-NEXT: br i1 [[TMP48]], label [[PRED_LOAD_IF18:%.*]], label [[PRED_LOAD_CONTINUE19:%.*]] 592; CHECK: pred.load.if18: 593; CHECK-NEXT: [[TMP105:%.*]] = getelementptr inbounds i16, ptr [[ALLOCA]], i64 [[TMP8]] 594; CHECK-NEXT: [[TMP106:%.*]] = load i32, ptr [[TMP105]], align 4 595; CHECK-NEXT: [[TMP107:%.*]] = insertelement <4 x i32> poison, i32 [[TMP106]], i32 0 596; CHECK-NEXT: br label [[PRED_LOAD_CONTINUE19]] 597; CHECK: pred.load.continue19: 598; CHECK-NEXT: [[TMP108:%.*]] = phi <4 x i32> [ poison, [[PRED_LOAD_CONTINUE17]] ], [ [[TMP107]], [[PRED_LOAD_IF18]] ] 599; CHECK-NEXT: br i1 [[TMP49]], label [[PRED_LOAD_IF20:%.*]], label [[PRED_LOAD_CONTINUE21:%.*]] 600; CHECK: pred.load.if20: 601; CHECK-NEXT: [[TMP110:%.*]] = getelementptr inbounds i16, ptr [[ALLOCA]], i64 [[TMP9]] 602; CHECK-NEXT: [[TMP111:%.*]] = load i32, ptr [[TMP110]], align 4 603; CHECK-NEXT: [[TMP112:%.*]] = insertelement <4 x i32> [[TMP108]], i32 [[TMP111]], i32 1 604; CHECK-NEXT: br label [[PRED_LOAD_CONTINUE21]] 605; CHECK: pred.load.continue21: 606; CHECK-NEXT: [[TMP113:%.*]] = phi <4 x i32> [ [[TMP108]], [[PRED_LOAD_CONTINUE19]] ], [ [[TMP112]], [[PRED_LOAD_IF20]] ] 607; CHECK-NEXT: br i1 [[TMP50]], label [[PRED_LOAD_IF22:%.*]], label [[PRED_LOAD_CONTINUE23:%.*]] 608; CHECK: pred.load.if22: 609; CHECK-NEXT: [[TMP115:%.*]] = getelementptr inbounds i16, ptr [[ALLOCA]], i64 [[TMP10]] 610; CHECK-NEXT: [[TMP116:%.*]] = load i32, ptr [[TMP115]], align 4 611; CHECK-NEXT: [[TMP117:%.*]] = insertelement <4 x i32> [[TMP113]], i32 [[TMP116]], i32 2 612; CHECK-NEXT: br label [[PRED_LOAD_CONTINUE23]] 613; CHECK: pred.load.continue23: 614; CHECK-NEXT: [[TMP118:%.*]] = phi <4 x i32> [ [[TMP113]], [[PRED_LOAD_CONTINUE21]] ], [ [[TMP117]], [[PRED_LOAD_IF22]] ] 615; CHECK-NEXT: br i1 [[TMP51]], label [[PRED_LOAD_IF24:%.*]], label [[PRED_LOAD_CONTINUE25:%.*]] 616; CHECK: pred.load.if24: 617; CHECK-NEXT: [[TMP120:%.*]] = getelementptr inbounds i16, ptr [[ALLOCA]], i64 [[TMP11]] 618; CHECK-NEXT: [[TMP121:%.*]] = load i32, ptr [[TMP120]], align 4 619; CHECK-NEXT: [[TMP122:%.*]] = insertelement <4 x i32> [[TMP118]], i32 [[TMP121]], i32 3 620; CHECK-NEXT: br label [[PRED_LOAD_CONTINUE25]] 621; CHECK: pred.load.continue25: 622; CHECK-NEXT: [[TMP123:%.*]] = phi <4 x i32> [ [[TMP118]], [[PRED_LOAD_CONTINUE23]] ], [ [[TMP122]], [[PRED_LOAD_IF24]] ] 623; CHECK-NEXT: br i1 [[TMP56]], label [[PRED_LOAD_IF26:%.*]], label [[PRED_LOAD_CONTINUE27:%.*]] 624; CHECK: pred.load.if26: 625; CHECK-NEXT: [[TMP125:%.*]] = getelementptr inbounds i16, ptr [[ALLOCA]], i64 [[TMP12]] 626; CHECK-NEXT: [[TMP126:%.*]] = load i32, ptr [[TMP125]], align 4 627; CHECK-NEXT: [[TMP127:%.*]] = insertelement <4 x i32> poison, i32 [[TMP126]], i32 0 628; CHECK-NEXT: br label [[PRED_LOAD_CONTINUE27]] 629; CHECK: pred.load.continue27: 630; CHECK-NEXT: [[TMP128:%.*]] = phi <4 x i32> [ poison, [[PRED_LOAD_CONTINUE25]] ], [ [[TMP127]], [[PRED_LOAD_IF26]] ] 631; CHECK-NEXT: br i1 [[TMP57]], label [[PRED_LOAD_IF28:%.*]], label [[PRED_LOAD_CONTINUE29:%.*]] 632; CHECK: pred.load.if28: 633; CHECK-NEXT: [[TMP130:%.*]] = getelementptr inbounds i16, ptr [[ALLOCA]], i64 [[TMP13]] 634; CHECK-NEXT: [[TMP131:%.*]] = load i32, ptr [[TMP130]], align 4 635; CHECK-NEXT: [[TMP132:%.*]] = insertelement <4 x i32> [[TMP128]], i32 [[TMP131]], i32 1 636; CHECK-NEXT: br label [[PRED_LOAD_CONTINUE29]] 637; CHECK: pred.load.continue29: 638; CHECK-NEXT: [[TMP133:%.*]] = phi <4 x i32> [ [[TMP128]], [[PRED_LOAD_CONTINUE27]] ], [ [[TMP132]], [[PRED_LOAD_IF28]] ] 639; CHECK-NEXT: br i1 [[TMP58]], label [[PRED_LOAD_IF30:%.*]], label [[PRED_LOAD_CONTINUE31:%.*]] 640; CHECK: pred.load.if30: 641; CHECK-NEXT: [[TMP135:%.*]] = getelementptr inbounds i16, ptr [[ALLOCA]], i64 [[TMP14]] 642; CHECK-NEXT: [[TMP136:%.*]] = load i32, ptr [[TMP135]], align 4 643; CHECK-NEXT: [[TMP137:%.*]] = insertelement <4 x i32> [[TMP133]], i32 [[TMP136]], i32 2 644; CHECK-NEXT: br label [[PRED_LOAD_CONTINUE31]] 645; CHECK: pred.load.continue31: 646; CHECK-NEXT: [[TMP138:%.*]] = phi <4 x i32> [ [[TMP133]], [[PRED_LOAD_CONTINUE29]] ], [ [[TMP137]], [[PRED_LOAD_IF30]] ] 647; CHECK-NEXT: br i1 [[TMP59]], label [[PRED_LOAD_IF32:%.*]], label [[PRED_LOAD_CONTINUE33]] 648; CHECK: pred.load.if32: 649; CHECK-NEXT: [[TMP140:%.*]] = getelementptr inbounds i16, ptr [[ALLOCA]], i64 [[TMP15]] 650; CHECK-NEXT: [[TMP141:%.*]] = load i32, ptr [[TMP140]], align 4 651; CHECK-NEXT: [[TMP142:%.*]] = insertelement <4 x i32> [[TMP138]], i32 [[TMP141]], i32 3 652; CHECK-NEXT: br label [[PRED_LOAD_CONTINUE33]] 653; CHECK: pred.load.continue33: 654; CHECK-NEXT: [[TMP143:%.*]] = phi <4 x i32> [ [[TMP138]], [[PRED_LOAD_CONTINUE31]] ], [ [[TMP142]], [[PRED_LOAD_IF32]] ] 655; CHECK-NEXT: [[PREDPHI:%.*]] = select <4 x i1> [[TMP39]], <4 x i32> [[TMP83]], <4 x i32> zeroinitializer 656; CHECK-NEXT: [[PREDPHI34:%.*]] = select <4 x i1> [[TMP47]], <4 x i32> [[TMP103]], <4 x i32> zeroinitializer 657; CHECK-NEXT: [[PREDPHI35:%.*]] = select <4 x i1> [[TMP55]], <4 x i32> [[TMP123]], <4 x i32> zeroinitializer 658; CHECK-NEXT: [[PREDPHI36:%.*]] = select <4 x i1> [[TMP63]], <4 x i32> [[TMP143]], <4 x i32> zeroinitializer 659; CHECK-NEXT: [[TMP144]] = add <4 x i32> [[VEC_PHI]], [[PREDPHI]] 660; CHECK-NEXT: [[TMP145]] = add <4 x i32> [[VEC_PHI1]], [[PREDPHI34]] 661; CHECK-NEXT: [[TMP146]] = add <4 x i32> [[VEC_PHI2]], [[PREDPHI35]] 662; CHECK-NEXT: [[TMP147]] = add <4 x i32> [[VEC_PHI3]], [[PREDPHI36]] 663; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16 664; CHECK-NEXT: [[TMP148:%.*]] = icmp eq i64 [[INDEX_NEXT]], 4096 665; CHECK-NEXT: br i1 [[TMP148]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]] 666; CHECK: middle.block: 667; CHECK-NEXT: [[BIN_RDX:%.*]] = add <4 x i32> [[TMP145]], [[TMP144]] 668; CHECK-NEXT: [[BIN_RDX37:%.*]] = add <4 x i32> [[TMP146]], [[BIN_RDX]] 669; CHECK-NEXT: [[BIN_RDX38:%.*]] = add <4 x i32> [[TMP147]], [[BIN_RDX37]] 670; CHECK-NEXT: [[TMP149:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[BIN_RDX38]]) 671; CHECK-NEXT: br i1 true, label [[LOOP_EXIT:%.*]], label [[SCALAR_PH]] 672; CHECK: scalar.ph: 673; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ 4096, [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ] 674; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP149]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY]] ] 675; CHECK-NEXT: br label [[LOOP:%.*]] 676; CHECK: loop: 677; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LATCH:%.*]] ] 678; CHECK-NEXT: [[ACCUM:%.*]] = phi i32 [ [[BC_MERGE_RDX]], [[SCALAR_PH]] ], [ [[ACCUM_NEXT:%.*]], [[LATCH]] ] 679; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1 680; CHECK-NEXT: [[TEST_ADDR:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[IV]] 681; CHECK-NEXT: [[EARLYCND:%.*]] = load i1, ptr [[TEST_ADDR]], align 1 682; CHECK-NEXT: br i1 [[EARLYCND]], label [[PRED:%.*]], label [[LATCH]] 683; CHECK: pred: 684; CHECK-NEXT: [[ADDR_I16P:%.*]] = getelementptr inbounds i16, ptr [[ALLOCA]], i64 [[IV]] 685; CHECK-NEXT: [[VAL:%.*]] = load i32, ptr [[ADDR_I16P]], align 4 686; CHECK-NEXT: br label [[LATCH]] 687; CHECK: latch: 688; CHECK-NEXT: [[VAL_PHI:%.*]] = phi i32 [ 0, [[LOOP]] ], [ [[VAL]], [[PRED]] ] 689; CHECK-NEXT: [[ACCUM_NEXT]] = add i32 [[ACCUM]], [[VAL_PHI]] 690; CHECK-NEXT: [[EXIT:%.*]] = icmp ugt i64 [[IV]], 4094 691; CHECK-NEXT: br i1 [[EXIT]], label [[LOOP_EXIT]], label [[LOOP]], !llvm.loop [[LOOP9:![0-9]+]] 692; CHECK: loop_exit: 693; CHECK-NEXT: [[ACCUM_NEXT_LCSSA:%.*]] = phi i32 [ [[ACCUM_NEXT]], [[LATCH]] ], [ [[TMP149]], [[MIDDLE_BLOCK]] ] 694; CHECK-NEXT: ret i32 [[ACCUM_NEXT_LCSSA]] 695; 696entry: 697 %alloca = alloca [4096 x i32] 698 call void @init(ptr %alloca) 699 br label %loop 700loop: 701 %iv = phi i64 [ 0, %entry ], [ %iv.next, %latch ] 702 %accum = phi i32 [ 0, %entry ], [ %accum.next, %latch ] 703 %iv.next = add i64 %iv, 1 704 %test_addr = getelementptr inbounds i1, ptr %test_base, i64 %iv 705 %earlycnd = load i1, ptr %test_addr 706 br i1 %earlycnd, label %pred, label %latch 707pred: 708 %addr.i16p = getelementptr inbounds i16, ptr %alloca, i64 %iv 709 %val = load i32, ptr %addr.i16p 710 br label %latch 711latch: 712 %val.phi = phi i32 [0, %loop], [%val, %pred] 713 %accum.next = add i32 %accum, %val.phi 714 %exit = icmp ugt i64 %iv, 4094 715 br i1 %exit, label %loop_exit, label %loop 716 717loop_exit: 718 ret i32 %accum.next 719} 720 721define i32 @test_max_trip_count(i64 %len, ptr %test_base, i64 %n) { 722; CHECK-LABEL: @test_max_trip_count( 723; CHECK-NEXT: entry: 724; CHECK-NEXT: [[ALLOCA:%.*]] = alloca [4096 x i32], align 4 725; CHECK-NEXT: call void @init(ptr [[ALLOCA]]) 726; CHECK-NEXT: [[MIN_CMP:%.*]] = icmp ult i64 4096, [[N:%.*]] 727; CHECK-NEXT: [[MIN_N:%.*]] = select i1 [[MIN_CMP]], i64 4096, i64 [[N]] 728; CHECK-NEXT: [[TMP0:%.*]] = add nuw nsw i64 [[MIN_N]], 2 729; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP0]], 16 730; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] 731; CHECK: vector.ph: 732; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP0]], 16 733; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP0]], [[N_MOD_VF]] 734; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] 735; CHECK: vector.body: 736; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] 737; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP73:%.*]], [[VECTOR_BODY]] ] 738; CHECK-NEXT: [[VEC_PHI1:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP74:%.*]], [[VECTOR_BODY]] ] 739; CHECK-NEXT: [[VEC_PHI2:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP75:%.*]], [[VECTOR_BODY]] ] 740; CHECK-NEXT: [[VEC_PHI3:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP76:%.*]], [[VECTOR_BODY]] ] 741; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[INDEX]], 0 742; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[INDEX]], 1 743; CHECK-NEXT: [[TMP3:%.*]] = add i64 [[INDEX]], 2 744; CHECK-NEXT: [[TMP4:%.*]] = add i64 [[INDEX]], 3 745; CHECK-NEXT: [[TMP5:%.*]] = add i64 [[INDEX]], 4 746; CHECK-NEXT: [[TMP6:%.*]] = add i64 [[INDEX]], 5 747; CHECK-NEXT: [[TMP7:%.*]] = add i64 [[INDEX]], 6 748; CHECK-NEXT: [[TMP8:%.*]] = add i64 [[INDEX]], 7 749; CHECK-NEXT: [[TMP9:%.*]] = add i64 [[INDEX]], 8 750; CHECK-NEXT: [[TMP10:%.*]] = add i64 [[INDEX]], 9 751; CHECK-NEXT: [[TMP11:%.*]] = add i64 [[INDEX]], 10 752; CHECK-NEXT: [[TMP12:%.*]] = add i64 [[INDEX]], 11 753; CHECK-NEXT: [[TMP13:%.*]] = add i64 [[INDEX]], 12 754; CHECK-NEXT: [[TMP14:%.*]] = add i64 [[INDEX]], 13 755; CHECK-NEXT: [[TMP15:%.*]] = add i64 [[INDEX]], 14 756; CHECK-NEXT: [[TMP16:%.*]] = add i64 [[INDEX]], 15 757; CHECK-NEXT: [[TMP17:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE:%.*]], i64 [[TMP1]] 758; CHECK-NEXT: [[TMP18:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP2]] 759; CHECK-NEXT: [[TMP19:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP3]] 760; CHECK-NEXT: [[TMP20:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP4]] 761; CHECK-NEXT: [[TMP21:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP5]] 762; CHECK-NEXT: [[TMP22:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP6]] 763; CHECK-NEXT: [[TMP23:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP7]] 764; CHECK-NEXT: [[TMP24:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP8]] 765; CHECK-NEXT: [[TMP25:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP9]] 766; CHECK-NEXT: [[TMP26:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP10]] 767; CHECK-NEXT: [[TMP27:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP11]] 768; CHECK-NEXT: [[TMP28:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP12]] 769; CHECK-NEXT: [[TMP29:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP13]] 770; CHECK-NEXT: [[TMP30:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP14]] 771; CHECK-NEXT: [[TMP31:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP15]] 772; CHECK-NEXT: [[TMP32:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP16]] 773; CHECK-NEXT: [[TMP33:%.*]] = load i1, ptr [[TMP17]], align 1 774; CHECK-NEXT: [[TMP34:%.*]] = load i1, ptr [[TMP18]], align 1 775; CHECK-NEXT: [[TMP35:%.*]] = load i1, ptr [[TMP19]], align 1 776; CHECK-NEXT: [[TMP36:%.*]] = load i1, ptr [[TMP20]], align 1 777; CHECK-NEXT: [[TMP37:%.*]] = insertelement <4 x i1> poison, i1 [[TMP33]], i32 0 778; CHECK-NEXT: [[TMP38:%.*]] = insertelement <4 x i1> [[TMP37]], i1 [[TMP34]], i32 1 779; CHECK-NEXT: [[TMP39:%.*]] = insertelement <4 x i1> [[TMP38]], i1 [[TMP35]], i32 2 780; CHECK-NEXT: [[TMP40:%.*]] = insertelement <4 x i1> [[TMP39]], i1 [[TMP36]], i32 3 781; CHECK-NEXT: [[TMP41:%.*]] = load i1, ptr [[TMP21]], align 1 782; CHECK-NEXT: [[TMP42:%.*]] = load i1, ptr [[TMP22]], align 1 783; CHECK-NEXT: [[TMP43:%.*]] = load i1, ptr [[TMP23]], align 1 784; CHECK-NEXT: [[TMP44:%.*]] = load i1, ptr [[TMP24]], align 1 785; CHECK-NEXT: [[TMP45:%.*]] = insertelement <4 x i1> poison, i1 [[TMP41]], i32 0 786; CHECK-NEXT: [[TMP46:%.*]] = insertelement <4 x i1> [[TMP45]], i1 [[TMP42]], i32 1 787; CHECK-NEXT: [[TMP47:%.*]] = insertelement <4 x i1> [[TMP46]], i1 [[TMP43]], i32 2 788; CHECK-NEXT: [[TMP48:%.*]] = insertelement <4 x i1> [[TMP47]], i1 [[TMP44]], i32 3 789; CHECK-NEXT: [[TMP49:%.*]] = load i1, ptr [[TMP25]], align 1 790; CHECK-NEXT: [[TMP50:%.*]] = load i1, ptr [[TMP26]], align 1 791; CHECK-NEXT: [[TMP51:%.*]] = load i1, ptr [[TMP27]], align 1 792; CHECK-NEXT: [[TMP52:%.*]] = load i1, ptr [[TMP28]], align 1 793; CHECK-NEXT: [[TMP53:%.*]] = insertelement <4 x i1> poison, i1 [[TMP49]], i32 0 794; CHECK-NEXT: [[TMP54:%.*]] = insertelement <4 x i1> [[TMP53]], i1 [[TMP50]], i32 1 795; CHECK-NEXT: [[TMP55:%.*]] = insertelement <4 x i1> [[TMP54]], i1 [[TMP51]], i32 2 796; CHECK-NEXT: [[TMP56:%.*]] = insertelement <4 x i1> [[TMP55]], i1 [[TMP52]], i32 3 797; CHECK-NEXT: [[TMP57:%.*]] = load i1, ptr [[TMP29]], align 1 798; CHECK-NEXT: [[TMP58:%.*]] = load i1, ptr [[TMP30]], align 1 799; CHECK-NEXT: [[TMP59:%.*]] = load i1, ptr [[TMP31]], align 1 800; CHECK-NEXT: [[TMP60:%.*]] = load i1, ptr [[TMP32]], align 1 801; CHECK-NEXT: [[TMP61:%.*]] = insertelement <4 x i1> poison, i1 [[TMP57]], i32 0 802; CHECK-NEXT: [[TMP62:%.*]] = insertelement <4 x i1> [[TMP61]], i1 [[TMP58]], i32 1 803; CHECK-NEXT: [[TMP63:%.*]] = insertelement <4 x i1> [[TMP62]], i1 [[TMP59]], i32 2 804; CHECK-NEXT: [[TMP64:%.*]] = insertelement <4 x i1> [[TMP63]], i1 [[TMP60]], i32 3 805; CHECK-NEXT: [[TMP65:%.*]] = getelementptr i32, ptr [[ALLOCA]], i64 [[TMP1]] 806; CHECK-NEXT: [[TMP69:%.*]] = getelementptr i32, ptr [[TMP65]], i32 0 807; CHECK-NEXT: [[TMP70:%.*]] = getelementptr i32, ptr [[TMP65]], i32 4 808; CHECK-NEXT: [[TMP71:%.*]] = getelementptr i32, ptr [[TMP65]], i32 8 809; CHECK-NEXT: [[TMP72:%.*]] = getelementptr i32, ptr [[TMP65]], i32 12 810; CHECK-NEXT: [[WIDE_MASKED_LOAD:%.*]] = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr [[TMP69]], i32 4, <4 x i1> [[TMP40]], <4 x i32> poison) 811; CHECK-NEXT: [[WIDE_MASKED_LOAD4:%.*]] = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr [[TMP70]], i32 4, <4 x i1> [[TMP48]], <4 x i32> poison) 812; CHECK-NEXT: [[WIDE_MASKED_LOAD5:%.*]] = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr [[TMP71]], i32 4, <4 x i1> [[TMP56]], <4 x i32> poison) 813; CHECK-NEXT: [[WIDE_MASKED_LOAD6:%.*]] = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr [[TMP72]], i32 4, <4 x i1> [[TMP64]], <4 x i32> poison) 814; CHECK-NEXT: [[PREDPHI:%.*]] = select <4 x i1> [[TMP40]], <4 x i32> [[WIDE_MASKED_LOAD]], <4 x i32> zeroinitializer 815; CHECK-NEXT: [[PREDPHI7:%.*]] = select <4 x i1> [[TMP48]], <4 x i32> [[WIDE_MASKED_LOAD4]], <4 x i32> zeroinitializer 816; CHECK-NEXT: [[PREDPHI8:%.*]] = select <4 x i1> [[TMP56]], <4 x i32> [[WIDE_MASKED_LOAD5]], <4 x i32> zeroinitializer 817; CHECK-NEXT: [[PREDPHI9:%.*]] = select <4 x i1> [[TMP64]], <4 x i32> [[WIDE_MASKED_LOAD6]], <4 x i32> zeroinitializer 818; CHECK-NEXT: [[TMP73]] = add <4 x i32> [[VEC_PHI]], [[PREDPHI]] 819; CHECK-NEXT: [[TMP74]] = add <4 x i32> [[VEC_PHI1]], [[PREDPHI7]] 820; CHECK-NEXT: [[TMP75]] = add <4 x i32> [[VEC_PHI2]], [[PREDPHI8]] 821; CHECK-NEXT: [[TMP76]] = add <4 x i32> [[VEC_PHI3]], [[PREDPHI9]] 822; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16 823; CHECK-NEXT: [[TMP77:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] 824; CHECK-NEXT: br i1 [[TMP77]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP10:![0-9]+]] 825; CHECK: middle.block: 826; CHECK-NEXT: [[BIN_RDX:%.*]] = add <4 x i32> [[TMP74]], [[TMP73]] 827; CHECK-NEXT: [[BIN_RDX10:%.*]] = add <4 x i32> [[TMP75]], [[BIN_RDX]] 828; CHECK-NEXT: [[BIN_RDX11:%.*]] = add <4 x i32> [[TMP76]], [[BIN_RDX10]] 829; CHECK-NEXT: [[TMP78:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[BIN_RDX11]]) 830; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP0]], [[N_VEC]] 831; CHECK-NEXT: br i1 [[CMP_N]], label [[LOOP_EXIT:%.*]], label [[SCALAR_PH]] 832; CHECK: scalar.ph: 833; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ] 834; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP78]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY]] ] 835; CHECK-NEXT: br label [[LOOP:%.*]] 836; CHECK: loop: 837; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LATCH:%.*]] ] 838; CHECK-NEXT: [[ACCUM:%.*]] = phi i32 [ [[BC_MERGE_RDX]], [[SCALAR_PH]] ], [ [[ACCUM_NEXT:%.*]], [[LATCH]] ] 839; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1 840; CHECK-NEXT: [[TEST_ADDR:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[IV]] 841; CHECK-NEXT: [[EARLYCND:%.*]] = load i1, ptr [[TEST_ADDR]], align 1 842; CHECK-NEXT: br i1 [[EARLYCND]], label [[PRED:%.*]], label [[LATCH]] 843; CHECK: pred: 844; CHECK-NEXT: [[ADDR:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[IV]] 845; CHECK-NEXT: [[VAL:%.*]] = load i32, ptr [[ADDR]], align 4 846; CHECK-NEXT: br label [[LATCH]] 847; CHECK: latch: 848; CHECK-NEXT: [[VAL_PHI:%.*]] = phi i32 [ 0, [[LOOP]] ], [ [[VAL]], [[PRED]] ] 849; CHECK-NEXT: [[ACCUM_NEXT]] = add i32 [[ACCUM]], [[VAL_PHI]] 850; CHECK-NEXT: [[EXIT:%.*]] = icmp ugt i64 [[IV]], [[MIN_N]] 851; CHECK-NEXT: br i1 [[EXIT]], label [[LOOP_EXIT]], label [[LOOP]], !llvm.loop [[LOOP11:![0-9]+]] 852; CHECK: loop_exit: 853; CHECK-NEXT: [[ACCUM_NEXT_LCSSA:%.*]] = phi i32 [ [[ACCUM_NEXT]], [[LATCH]] ], [ [[TMP78]], [[MIDDLE_BLOCK]] ] 854; CHECK-NEXT: ret i32 [[ACCUM_NEXT_LCSSA]] 855; 856entry: 857 %alloca = alloca [4096 x i32] 858 call void @init(ptr %alloca) 859 %min.cmp = icmp ult i64 4096, %n 860 %min.n = select i1 %min.cmp, i64 4096, i64 %n 861 br label %loop 862loop: 863 %iv = phi i64 [ 0, %entry ], [ %iv.next, %latch ] 864 %accum = phi i32 [ 0, %entry ], [ %accum.next, %latch ] 865 %iv.next = add i64 %iv, 1 866 %test_addr = getelementptr inbounds i1, ptr %test_base, i64 %iv 867 %earlycnd = load i1, ptr %test_addr 868 br i1 %earlycnd, label %pred, label %latch 869pred: 870 %addr = getelementptr inbounds i32, ptr %alloca, i64 %iv 871 %val = load i32, ptr %addr 872 br label %latch 873latch: 874 %val.phi = phi i32 [0, %loop], [%val, %pred] 875 %accum.next = add i32 %accum, %val.phi 876 %exit = icmp ugt i64 %iv, %min.n 877 br i1 %exit, label %loop_exit, label %loop 878 879loop_exit: 880 ret i32 %accum.next 881} 882 883 884 885 886define i32 @test_non_zero_start(i64 %len, ptr %test_base) { 887; CHECK-LABEL: @test_non_zero_start( 888; CHECK-NEXT: entry: 889; CHECK-NEXT: [[ALLOCA:%.*]] = alloca [4096 x i32], align 4 890; CHECK-NEXT: call void @init(ptr [[ALLOCA]]) 891; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] 892; CHECK: vector.ph: 893; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] 894; CHECK: vector.body: 895; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] 896; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP72:%.*]], [[VECTOR_BODY]] ] 897; CHECK-NEXT: [[VEC_PHI1:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP73:%.*]], [[VECTOR_BODY]] ] 898; CHECK-NEXT: [[VEC_PHI2:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP74:%.*]], [[VECTOR_BODY]] ] 899; CHECK-NEXT: [[VEC_PHI3:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP75:%.*]], [[VECTOR_BODY]] ] 900; CHECK-NEXT: [[OFFSET_IDX:%.*]] = add i64 1024, [[INDEX]] 901; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[OFFSET_IDX]], 0 902; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[OFFSET_IDX]], 1 903; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[OFFSET_IDX]], 2 904; CHECK-NEXT: [[TMP3:%.*]] = add i64 [[OFFSET_IDX]], 3 905; CHECK-NEXT: [[TMP4:%.*]] = add i64 [[OFFSET_IDX]], 4 906; CHECK-NEXT: [[TMP5:%.*]] = add i64 [[OFFSET_IDX]], 5 907; CHECK-NEXT: [[TMP6:%.*]] = add i64 [[OFFSET_IDX]], 6 908; CHECK-NEXT: [[TMP7:%.*]] = add i64 [[OFFSET_IDX]], 7 909; CHECK-NEXT: [[TMP8:%.*]] = add i64 [[OFFSET_IDX]], 8 910; CHECK-NEXT: [[TMP9:%.*]] = add i64 [[OFFSET_IDX]], 9 911; CHECK-NEXT: [[TMP10:%.*]] = add i64 [[OFFSET_IDX]], 10 912; CHECK-NEXT: [[TMP11:%.*]] = add i64 [[OFFSET_IDX]], 11 913; CHECK-NEXT: [[TMP12:%.*]] = add i64 [[OFFSET_IDX]], 12 914; CHECK-NEXT: [[TMP13:%.*]] = add i64 [[OFFSET_IDX]], 13 915; CHECK-NEXT: [[TMP14:%.*]] = add i64 [[OFFSET_IDX]], 14 916; CHECK-NEXT: [[TMP15:%.*]] = add i64 [[OFFSET_IDX]], 15 917; CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE:%.*]], i64 [[TMP0]] 918; CHECK-NEXT: [[TMP17:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP1]] 919; CHECK-NEXT: [[TMP18:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP2]] 920; CHECK-NEXT: [[TMP19:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP3]] 921; CHECK-NEXT: [[TMP20:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP4]] 922; CHECK-NEXT: [[TMP21:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP5]] 923; CHECK-NEXT: [[TMP22:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP6]] 924; CHECK-NEXT: [[TMP23:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP7]] 925; CHECK-NEXT: [[TMP24:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP8]] 926; CHECK-NEXT: [[TMP25:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP9]] 927; CHECK-NEXT: [[TMP26:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP10]] 928; CHECK-NEXT: [[TMP27:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP11]] 929; CHECK-NEXT: [[TMP28:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP12]] 930; CHECK-NEXT: [[TMP29:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP13]] 931; CHECK-NEXT: [[TMP30:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP14]] 932; CHECK-NEXT: [[TMP31:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP15]] 933; CHECK-NEXT: [[TMP32:%.*]] = load i1, ptr [[TMP16]], align 1 934; CHECK-NEXT: [[TMP33:%.*]] = load i1, ptr [[TMP17]], align 1 935; CHECK-NEXT: [[TMP34:%.*]] = load i1, ptr [[TMP18]], align 1 936; CHECK-NEXT: [[TMP35:%.*]] = load i1, ptr [[TMP19]], align 1 937; CHECK-NEXT: [[TMP36:%.*]] = insertelement <4 x i1> poison, i1 [[TMP32]], i32 0 938; CHECK-NEXT: [[TMP37:%.*]] = insertelement <4 x i1> [[TMP36]], i1 [[TMP33]], i32 1 939; CHECK-NEXT: [[TMP38:%.*]] = insertelement <4 x i1> [[TMP37]], i1 [[TMP34]], i32 2 940; CHECK-NEXT: [[TMP39:%.*]] = insertelement <4 x i1> [[TMP38]], i1 [[TMP35]], i32 3 941; CHECK-NEXT: [[TMP40:%.*]] = load i1, ptr [[TMP20]], align 1 942; CHECK-NEXT: [[TMP41:%.*]] = load i1, ptr [[TMP21]], align 1 943; CHECK-NEXT: [[TMP42:%.*]] = load i1, ptr [[TMP22]], align 1 944; CHECK-NEXT: [[TMP43:%.*]] = load i1, ptr [[TMP23]], align 1 945; CHECK-NEXT: [[TMP44:%.*]] = insertelement <4 x i1> poison, i1 [[TMP40]], i32 0 946; CHECK-NEXT: [[TMP45:%.*]] = insertelement <4 x i1> [[TMP44]], i1 [[TMP41]], i32 1 947; CHECK-NEXT: [[TMP46:%.*]] = insertelement <4 x i1> [[TMP45]], i1 [[TMP42]], i32 2 948; CHECK-NEXT: [[TMP47:%.*]] = insertelement <4 x i1> [[TMP46]], i1 [[TMP43]], i32 3 949; CHECK-NEXT: [[TMP48:%.*]] = load i1, ptr [[TMP24]], align 1 950; CHECK-NEXT: [[TMP49:%.*]] = load i1, ptr [[TMP25]], align 1 951; CHECK-NEXT: [[TMP50:%.*]] = load i1, ptr [[TMP26]], align 1 952; CHECK-NEXT: [[TMP51:%.*]] = load i1, ptr [[TMP27]], align 1 953; CHECK-NEXT: [[TMP52:%.*]] = insertelement <4 x i1> poison, i1 [[TMP48]], i32 0 954; CHECK-NEXT: [[TMP53:%.*]] = insertelement <4 x i1> [[TMP52]], i1 [[TMP49]], i32 1 955; CHECK-NEXT: [[TMP54:%.*]] = insertelement <4 x i1> [[TMP53]], i1 [[TMP50]], i32 2 956; CHECK-NEXT: [[TMP55:%.*]] = insertelement <4 x i1> [[TMP54]], i1 [[TMP51]], i32 3 957; CHECK-NEXT: [[TMP56:%.*]] = load i1, ptr [[TMP28]], align 1 958; CHECK-NEXT: [[TMP57:%.*]] = load i1, ptr [[TMP29]], align 1 959; CHECK-NEXT: [[TMP58:%.*]] = load i1, ptr [[TMP30]], align 1 960; CHECK-NEXT: [[TMP59:%.*]] = load i1, ptr [[TMP31]], align 1 961; CHECK-NEXT: [[TMP60:%.*]] = insertelement <4 x i1> poison, i1 [[TMP56]], i32 0 962; CHECK-NEXT: [[TMP61:%.*]] = insertelement <4 x i1> [[TMP60]], i1 [[TMP57]], i32 1 963; CHECK-NEXT: [[TMP62:%.*]] = insertelement <4 x i1> [[TMP61]], i1 [[TMP58]], i32 2 964; CHECK-NEXT: [[TMP63:%.*]] = insertelement <4 x i1> [[TMP62]], i1 [[TMP59]], i32 3 965; CHECK-NEXT: [[TMP64:%.*]] = getelementptr i32, ptr [[ALLOCA]], i64 [[TMP0]] 966; CHECK-NEXT: [[TMP68:%.*]] = getelementptr i32, ptr [[TMP64]], i32 0 967; CHECK-NEXT: [[TMP69:%.*]] = getelementptr i32, ptr [[TMP64]], i32 4 968; CHECK-NEXT: [[TMP70:%.*]] = getelementptr i32, ptr [[TMP64]], i32 8 969; CHECK-NEXT: [[TMP71:%.*]] = getelementptr i32, ptr [[TMP64]], i32 12 970; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP68]], align 4 971; CHECK-NEXT: [[WIDE_LOAD4:%.*]] = load <4 x i32>, ptr [[TMP69]], align 4 972; CHECK-NEXT: [[WIDE_LOAD5:%.*]] = load <4 x i32>, ptr [[TMP70]], align 4 973; CHECK-NEXT: [[WIDE_LOAD6:%.*]] = load <4 x i32>, ptr [[TMP71]], align 4 974; CHECK-NEXT: [[PREDPHI:%.*]] = select <4 x i1> [[TMP39]], <4 x i32> [[WIDE_LOAD]], <4 x i32> zeroinitializer 975; CHECK-NEXT: [[PREDPHI7:%.*]] = select <4 x i1> [[TMP47]], <4 x i32> [[WIDE_LOAD4]], <4 x i32> zeroinitializer 976; CHECK-NEXT: [[PREDPHI8:%.*]] = select <4 x i1> [[TMP55]], <4 x i32> [[WIDE_LOAD5]], <4 x i32> zeroinitializer 977; CHECK-NEXT: [[PREDPHI9:%.*]] = select <4 x i1> [[TMP63]], <4 x i32> [[WIDE_LOAD6]], <4 x i32> zeroinitializer 978; CHECK-NEXT: [[TMP72]] = add <4 x i32> [[VEC_PHI]], [[PREDPHI]] 979; CHECK-NEXT: [[TMP73]] = add <4 x i32> [[VEC_PHI1]], [[PREDPHI7]] 980; CHECK-NEXT: [[TMP74]] = add <4 x i32> [[VEC_PHI2]], [[PREDPHI8]] 981; CHECK-NEXT: [[TMP75]] = add <4 x i32> [[VEC_PHI3]], [[PREDPHI9]] 982; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16 983; CHECK-NEXT: [[TMP76:%.*]] = icmp eq i64 [[INDEX_NEXT]], 3072 984; CHECK-NEXT: br i1 [[TMP76]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP12:![0-9]+]] 985; CHECK: middle.block: 986; CHECK-NEXT: [[BIN_RDX:%.*]] = add <4 x i32> [[TMP73]], [[TMP72]] 987; CHECK-NEXT: [[BIN_RDX10:%.*]] = add <4 x i32> [[TMP74]], [[BIN_RDX]] 988; CHECK-NEXT: [[BIN_RDX11:%.*]] = add <4 x i32> [[TMP75]], [[BIN_RDX10]] 989; CHECK-NEXT: [[TMP77:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[BIN_RDX11]]) 990; CHECK-NEXT: br i1 true, label [[LOOP_EXIT:%.*]], label [[SCALAR_PH]] 991; CHECK: scalar.ph: 992; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ 4096, [[MIDDLE_BLOCK]] ], [ 1024, [[ENTRY:%.*]] ] 993; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP77]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY]] ] 994; CHECK-NEXT: br label [[LOOP:%.*]] 995; CHECK: loop: 996; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LATCH:%.*]] ] 997; CHECK-NEXT: [[ACCUM:%.*]] = phi i32 [ [[BC_MERGE_RDX]], [[SCALAR_PH]] ], [ [[ACCUM_NEXT:%.*]], [[LATCH]] ] 998; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1 999; CHECK-NEXT: [[TEST_ADDR:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[IV]] 1000; CHECK-NEXT: [[EARLYCND:%.*]] = load i1, ptr [[TEST_ADDR]], align 1 1001; CHECK-NEXT: br i1 [[EARLYCND]], label [[PRED:%.*]], label [[LATCH]] 1002; CHECK: pred: 1003; CHECK-NEXT: [[ADDR:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[IV]] 1004; CHECK-NEXT: [[VAL:%.*]] = load i32, ptr [[ADDR]], align 4 1005; CHECK-NEXT: br label [[LATCH]] 1006; CHECK: latch: 1007; CHECK-NEXT: [[VAL_PHI:%.*]] = phi i32 [ 0, [[LOOP]] ], [ [[VAL]], [[PRED]] ] 1008; CHECK-NEXT: [[ACCUM_NEXT]] = add i32 [[ACCUM]], [[VAL_PHI]] 1009; CHECK-NEXT: [[EXIT:%.*]] = icmp ugt i64 [[IV]], 4094 1010; CHECK-NEXT: br i1 [[EXIT]], label [[LOOP_EXIT]], label [[LOOP]], !llvm.loop [[LOOP13:![0-9]+]] 1011; CHECK: loop_exit: 1012; CHECK-NEXT: [[ACCUM_NEXT_LCSSA:%.*]] = phi i32 [ [[ACCUM_NEXT]], [[LATCH]] ], [ [[TMP77]], [[MIDDLE_BLOCK]] ] 1013; CHECK-NEXT: ret i32 [[ACCUM_NEXT_LCSSA]] 1014; 1015entry: 1016 %alloca = alloca [4096 x i32] 1017 call void @init(ptr %alloca) 1018 br label %loop 1019loop: 1020 %iv = phi i64 [ 1024, %entry ], [ %iv.next, %latch ] 1021 %accum = phi i32 [ 0, %entry ], [ %accum.next, %latch ] 1022 %iv.next = add i64 %iv, 1 1023 %test_addr = getelementptr inbounds i1, ptr %test_base, i64 %iv 1024 %earlycnd = load i1, ptr %test_addr 1025 br i1 %earlycnd, label %pred, label %latch 1026pred: 1027 %addr = getelementptr inbounds i32, ptr %alloca, i64 %iv 1028 %val = load i32, ptr %addr 1029 br label %latch 1030latch: 1031 %val.phi = phi i32 [0, %loop], [%val, %pred] 1032 %accum.next = add i32 %accum, %val.phi 1033 %exit = icmp ugt i64 %iv, 4094 1034 br i1 %exit, label %loop_exit, label %loop 1035 1036loop_exit: 1037 ret i32 %accum.next 1038} 1039 1040define i32 @neg_out_of_bounds_start(i64 %len, ptr %test_base) { 1041; CHECK-LABEL: @neg_out_of_bounds_start( 1042; CHECK-NEXT: entry: 1043; CHECK-NEXT: [[ALLOCA:%.*]] = alloca [4096 x i32], align 4 1044; CHECK-NEXT: call void @init(ptr [[ALLOCA]]) 1045; CHECK-NEXT: br label [[LOOP:%.*]] 1046; CHECK: loop: 1047; CHECK-NEXT: [[IV:%.*]] = phi i64 [ -10, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LATCH:%.*]] ] 1048; CHECK-NEXT: [[ACCUM:%.*]] = phi i32 [ 0, [[ENTRY]] ], [ [[ACCUM_NEXT:%.*]], [[LATCH]] ] 1049; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1 1050; CHECK-NEXT: [[TEST_ADDR:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE:%.*]], i64 [[IV]] 1051; CHECK-NEXT: [[EARLYCND:%.*]] = load i1, ptr [[TEST_ADDR]], align 1 1052; CHECK-NEXT: br i1 [[EARLYCND]], label [[PRED:%.*]], label [[LATCH]] 1053; CHECK: pred: 1054; CHECK-NEXT: [[ADDR:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[IV]] 1055; CHECK-NEXT: [[VAL:%.*]] = load i32, ptr [[ADDR]], align 4 1056; CHECK-NEXT: br label [[LATCH]] 1057; CHECK: latch: 1058; CHECK-NEXT: [[VAL_PHI:%.*]] = phi i32 [ 0, [[LOOP]] ], [ [[VAL]], [[PRED]] ] 1059; CHECK-NEXT: [[ACCUM_NEXT]] = add i32 [[ACCUM]], [[VAL_PHI]] 1060; CHECK-NEXT: [[EXIT:%.*]] = icmp ugt i64 [[IV]], 4094 1061; CHECK-NEXT: br i1 [[EXIT]], label [[LOOP_EXIT:%.*]], label [[LOOP]] 1062; CHECK: loop_exit: 1063; CHECK-NEXT: [[ACCUM_NEXT_LCSSA:%.*]] = phi i32 [ [[ACCUM_NEXT]], [[LATCH]] ] 1064; CHECK-NEXT: ret i32 [[ACCUM_NEXT_LCSSA]] 1065; 1066entry: 1067 %alloca = alloca [4096 x i32] 1068 call void @init(ptr %alloca) 1069 br label %loop 1070loop: 1071 %iv = phi i64 [ -10, %entry ], [ %iv.next, %latch ] 1072 %accum = phi i32 [ 0, %entry ], [ %accum.next, %latch ] 1073 %iv.next = add i64 %iv, 1 1074 %test_addr = getelementptr inbounds i1, ptr %test_base, i64 %iv 1075 %earlycnd = load i1, ptr %test_addr 1076 br i1 %earlycnd, label %pred, label %latch 1077pred: 1078 %addr = getelementptr inbounds i32, ptr %alloca, i64 %iv 1079 %val = load i32, ptr %addr 1080 br label %latch 1081latch: 1082 %val.phi = phi i32 [0, %loop], [%val, %pred] 1083 %accum.next = add i32 %accum, %val.phi 1084 %exit = icmp ugt i64 %iv, 4094 1085 br i1 %exit, label %loop_exit, label %loop 1086 1087loop_exit: 1088 ret i32 %accum.next 1089} 1090 1091define i32 @test_non_unit_stride(i64 %len, ptr %test_base) { 1092; CHECK-LABEL: @test_non_unit_stride( 1093; CHECK-NEXT: entry: 1094; CHECK-NEXT: [[ALLOCA:%.*]] = alloca [4096 x i32], align 4 1095; CHECK-NEXT: call void @init(ptr [[ALLOCA]]) 1096; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] 1097; CHECK: vector.ph: 1098; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] 1099; CHECK: vector.body: 1100; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] 1101; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP112:%.*]], [[VECTOR_BODY]] ] 1102; CHECK-NEXT: [[VEC_PHI1:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP113:%.*]], [[VECTOR_BODY]] ] 1103; CHECK-NEXT: [[VEC_PHI2:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP114:%.*]], [[VECTOR_BODY]] ] 1104; CHECK-NEXT: [[VEC_PHI3:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP115:%.*]], [[VECTOR_BODY]] ] 1105; CHECK-NEXT: [[OFFSET_IDX:%.*]] = mul i64 [[INDEX]], 2 1106; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[OFFSET_IDX]], 0 1107; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[OFFSET_IDX]], 2 1108; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[OFFSET_IDX]], 4 1109; CHECK-NEXT: [[TMP3:%.*]] = add i64 [[OFFSET_IDX]], 6 1110; CHECK-NEXT: [[TMP4:%.*]] = add i64 [[OFFSET_IDX]], 8 1111; CHECK-NEXT: [[TMP5:%.*]] = add i64 [[OFFSET_IDX]], 10 1112; CHECK-NEXT: [[TMP6:%.*]] = add i64 [[OFFSET_IDX]], 12 1113; CHECK-NEXT: [[TMP7:%.*]] = add i64 [[OFFSET_IDX]], 14 1114; CHECK-NEXT: [[TMP8:%.*]] = add i64 [[OFFSET_IDX]], 16 1115; CHECK-NEXT: [[TMP9:%.*]] = add i64 [[OFFSET_IDX]], 18 1116; CHECK-NEXT: [[TMP10:%.*]] = add i64 [[OFFSET_IDX]], 20 1117; CHECK-NEXT: [[TMP11:%.*]] = add i64 [[OFFSET_IDX]], 22 1118; CHECK-NEXT: [[TMP12:%.*]] = add i64 [[OFFSET_IDX]], 24 1119; CHECK-NEXT: [[TMP13:%.*]] = add i64 [[OFFSET_IDX]], 26 1120; CHECK-NEXT: [[TMP14:%.*]] = add i64 [[OFFSET_IDX]], 28 1121; CHECK-NEXT: [[TMP15:%.*]] = add i64 [[OFFSET_IDX]], 30 1122; CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE:%.*]], i64 [[TMP0]] 1123; CHECK-NEXT: [[TMP17:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP1]] 1124; CHECK-NEXT: [[TMP18:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP2]] 1125; CHECK-NEXT: [[TMP19:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP3]] 1126; CHECK-NEXT: [[TMP20:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP4]] 1127; CHECK-NEXT: [[TMP21:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP5]] 1128; CHECK-NEXT: [[TMP22:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP6]] 1129; CHECK-NEXT: [[TMP23:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP7]] 1130; CHECK-NEXT: [[TMP24:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP8]] 1131; CHECK-NEXT: [[TMP25:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP9]] 1132; CHECK-NEXT: [[TMP26:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP10]] 1133; CHECK-NEXT: [[TMP27:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP11]] 1134; CHECK-NEXT: [[TMP28:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP12]] 1135; CHECK-NEXT: [[TMP29:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP13]] 1136; CHECK-NEXT: [[TMP30:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP14]] 1137; CHECK-NEXT: [[TMP31:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP15]] 1138; CHECK-NEXT: [[TMP32:%.*]] = load i1, ptr [[TMP16]], align 1 1139; CHECK-NEXT: [[TMP33:%.*]] = load i1, ptr [[TMP17]], align 1 1140; CHECK-NEXT: [[TMP34:%.*]] = load i1, ptr [[TMP18]], align 1 1141; CHECK-NEXT: [[TMP35:%.*]] = load i1, ptr [[TMP19]], align 1 1142; CHECK-NEXT: [[TMP36:%.*]] = insertelement <4 x i1> poison, i1 [[TMP32]], i32 0 1143; CHECK-NEXT: [[TMP37:%.*]] = insertelement <4 x i1> [[TMP36]], i1 [[TMP33]], i32 1 1144; CHECK-NEXT: [[TMP38:%.*]] = insertelement <4 x i1> [[TMP37]], i1 [[TMP34]], i32 2 1145; CHECK-NEXT: [[TMP39:%.*]] = insertelement <4 x i1> [[TMP38]], i1 [[TMP35]], i32 3 1146; CHECK-NEXT: [[TMP40:%.*]] = load i1, ptr [[TMP20]], align 1 1147; CHECK-NEXT: [[TMP41:%.*]] = load i1, ptr [[TMP21]], align 1 1148; CHECK-NEXT: [[TMP42:%.*]] = load i1, ptr [[TMP22]], align 1 1149; CHECK-NEXT: [[TMP43:%.*]] = load i1, ptr [[TMP23]], align 1 1150; CHECK-NEXT: [[TMP44:%.*]] = insertelement <4 x i1> poison, i1 [[TMP40]], i32 0 1151; CHECK-NEXT: [[TMP45:%.*]] = insertelement <4 x i1> [[TMP44]], i1 [[TMP41]], i32 1 1152; CHECK-NEXT: [[TMP46:%.*]] = insertelement <4 x i1> [[TMP45]], i1 [[TMP42]], i32 2 1153; CHECK-NEXT: [[TMP47:%.*]] = insertelement <4 x i1> [[TMP46]], i1 [[TMP43]], i32 3 1154; CHECK-NEXT: [[TMP48:%.*]] = load i1, ptr [[TMP24]], align 1 1155; CHECK-NEXT: [[TMP49:%.*]] = load i1, ptr [[TMP25]], align 1 1156; CHECK-NEXT: [[TMP50:%.*]] = load i1, ptr [[TMP26]], align 1 1157; CHECK-NEXT: [[TMP51:%.*]] = load i1, ptr [[TMP27]], align 1 1158; CHECK-NEXT: [[TMP52:%.*]] = insertelement <4 x i1> poison, i1 [[TMP48]], i32 0 1159; CHECK-NEXT: [[TMP53:%.*]] = insertelement <4 x i1> [[TMP52]], i1 [[TMP49]], i32 1 1160; CHECK-NEXT: [[TMP54:%.*]] = insertelement <4 x i1> [[TMP53]], i1 [[TMP50]], i32 2 1161; CHECK-NEXT: [[TMP55:%.*]] = insertelement <4 x i1> [[TMP54]], i1 [[TMP51]], i32 3 1162; CHECK-NEXT: [[TMP56:%.*]] = load i1, ptr [[TMP28]], align 1 1163; CHECK-NEXT: [[TMP57:%.*]] = load i1, ptr [[TMP29]], align 1 1164; CHECK-NEXT: [[TMP58:%.*]] = load i1, ptr [[TMP30]], align 1 1165; CHECK-NEXT: [[TMP59:%.*]] = load i1, ptr [[TMP31]], align 1 1166; CHECK-NEXT: [[TMP60:%.*]] = insertelement <4 x i1> poison, i1 [[TMP56]], i32 0 1167; CHECK-NEXT: [[TMP61:%.*]] = insertelement <4 x i1> [[TMP60]], i1 [[TMP57]], i32 1 1168; CHECK-NEXT: [[TMP62:%.*]] = insertelement <4 x i1> [[TMP61]], i1 [[TMP58]], i32 2 1169; CHECK-NEXT: [[TMP63:%.*]] = insertelement <4 x i1> [[TMP62]], i1 [[TMP59]], i32 3 1170; CHECK-NEXT: [[TMP64:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP0]] 1171; CHECK-NEXT: [[TMP65:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP1]] 1172; CHECK-NEXT: [[TMP66:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP2]] 1173; CHECK-NEXT: [[TMP67:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP3]] 1174; CHECK-NEXT: [[TMP68:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP4]] 1175; CHECK-NEXT: [[TMP69:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP5]] 1176; CHECK-NEXT: [[TMP70:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP6]] 1177; CHECK-NEXT: [[TMP71:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP7]] 1178; CHECK-NEXT: [[TMP72:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP8]] 1179; CHECK-NEXT: [[TMP73:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP9]] 1180; CHECK-NEXT: [[TMP74:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP10]] 1181; CHECK-NEXT: [[TMP75:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP11]] 1182; CHECK-NEXT: [[TMP76:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP12]] 1183; CHECK-NEXT: [[TMP77:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP13]] 1184; CHECK-NEXT: [[TMP78:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP14]] 1185; CHECK-NEXT: [[TMP79:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP15]] 1186; CHECK-NEXT: [[TMP80:%.*]] = load i32, ptr [[TMP64]], align 4 1187; CHECK-NEXT: [[TMP81:%.*]] = load i32, ptr [[TMP65]], align 4 1188; CHECK-NEXT: [[TMP82:%.*]] = load i32, ptr [[TMP66]], align 4 1189; CHECK-NEXT: [[TMP83:%.*]] = load i32, ptr [[TMP67]], align 4 1190; CHECK-NEXT: [[TMP84:%.*]] = insertelement <4 x i32> poison, i32 [[TMP80]], i32 0 1191; CHECK-NEXT: [[TMP85:%.*]] = insertelement <4 x i32> [[TMP84]], i32 [[TMP81]], i32 1 1192; CHECK-NEXT: [[TMP86:%.*]] = insertelement <4 x i32> [[TMP85]], i32 [[TMP82]], i32 2 1193; CHECK-NEXT: [[TMP87:%.*]] = insertelement <4 x i32> [[TMP86]], i32 [[TMP83]], i32 3 1194; CHECK-NEXT: [[TMP88:%.*]] = load i32, ptr [[TMP68]], align 4 1195; CHECK-NEXT: [[TMP89:%.*]] = load i32, ptr [[TMP69]], align 4 1196; CHECK-NEXT: [[TMP90:%.*]] = load i32, ptr [[TMP70]], align 4 1197; CHECK-NEXT: [[TMP91:%.*]] = load i32, ptr [[TMP71]], align 4 1198; CHECK-NEXT: [[TMP92:%.*]] = insertelement <4 x i32> poison, i32 [[TMP88]], i32 0 1199; CHECK-NEXT: [[TMP93:%.*]] = insertelement <4 x i32> [[TMP92]], i32 [[TMP89]], i32 1 1200; CHECK-NEXT: [[TMP94:%.*]] = insertelement <4 x i32> [[TMP93]], i32 [[TMP90]], i32 2 1201; CHECK-NEXT: [[TMP95:%.*]] = insertelement <4 x i32> [[TMP94]], i32 [[TMP91]], i32 3 1202; CHECK-NEXT: [[TMP96:%.*]] = load i32, ptr [[TMP72]], align 4 1203; CHECK-NEXT: [[TMP97:%.*]] = load i32, ptr [[TMP73]], align 4 1204; CHECK-NEXT: [[TMP98:%.*]] = load i32, ptr [[TMP74]], align 4 1205; CHECK-NEXT: [[TMP99:%.*]] = load i32, ptr [[TMP75]], align 4 1206; CHECK-NEXT: [[TMP100:%.*]] = insertelement <4 x i32> poison, i32 [[TMP96]], i32 0 1207; CHECK-NEXT: [[TMP101:%.*]] = insertelement <4 x i32> [[TMP100]], i32 [[TMP97]], i32 1 1208; CHECK-NEXT: [[TMP102:%.*]] = insertelement <4 x i32> [[TMP101]], i32 [[TMP98]], i32 2 1209; CHECK-NEXT: [[TMP103:%.*]] = insertelement <4 x i32> [[TMP102]], i32 [[TMP99]], i32 3 1210; CHECK-NEXT: [[TMP104:%.*]] = load i32, ptr [[TMP76]], align 4 1211; CHECK-NEXT: [[TMP105:%.*]] = load i32, ptr [[TMP77]], align 4 1212; CHECK-NEXT: [[TMP106:%.*]] = load i32, ptr [[TMP78]], align 4 1213; CHECK-NEXT: [[TMP107:%.*]] = load i32, ptr [[TMP79]], align 4 1214; CHECK-NEXT: [[TMP108:%.*]] = insertelement <4 x i32> poison, i32 [[TMP104]], i32 0 1215; CHECK-NEXT: [[TMP109:%.*]] = insertelement <4 x i32> [[TMP108]], i32 [[TMP105]], i32 1 1216; CHECK-NEXT: [[TMP110:%.*]] = insertelement <4 x i32> [[TMP109]], i32 [[TMP106]], i32 2 1217; CHECK-NEXT: [[TMP111:%.*]] = insertelement <4 x i32> [[TMP110]], i32 [[TMP107]], i32 3 1218; CHECK-NEXT: [[PREDPHI:%.*]] = select <4 x i1> [[TMP39]], <4 x i32> [[TMP87]], <4 x i32> zeroinitializer 1219; CHECK-NEXT: [[PREDPHI4:%.*]] = select <4 x i1> [[TMP47]], <4 x i32> [[TMP95]], <4 x i32> zeroinitializer 1220; CHECK-NEXT: [[PREDPHI5:%.*]] = select <4 x i1> [[TMP55]], <4 x i32> [[TMP103]], <4 x i32> zeroinitializer 1221; CHECK-NEXT: [[PREDPHI6:%.*]] = select <4 x i1> [[TMP63]], <4 x i32> [[TMP111]], <4 x i32> zeroinitializer 1222; CHECK-NEXT: [[TMP112]] = add <4 x i32> [[VEC_PHI]], [[PREDPHI]] 1223; CHECK-NEXT: [[TMP113]] = add <4 x i32> [[VEC_PHI1]], [[PREDPHI4]] 1224; CHECK-NEXT: [[TMP114]] = add <4 x i32> [[VEC_PHI2]], [[PREDPHI5]] 1225; CHECK-NEXT: [[TMP115]] = add <4 x i32> [[VEC_PHI3]], [[PREDPHI6]] 1226; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16 1227; CHECK-NEXT: [[TMP116:%.*]] = icmp eq i64 [[INDEX_NEXT]], 2048 1228; CHECK-NEXT: br i1 [[TMP116]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP14:![0-9]+]] 1229; CHECK: middle.block: 1230; CHECK-NEXT: [[BIN_RDX:%.*]] = add <4 x i32> [[TMP113]], [[TMP112]] 1231; CHECK-NEXT: [[BIN_RDX7:%.*]] = add <4 x i32> [[TMP114]], [[BIN_RDX]] 1232; CHECK-NEXT: [[BIN_RDX8:%.*]] = add <4 x i32> [[TMP115]], [[BIN_RDX7]] 1233; CHECK-NEXT: [[TMP117:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[BIN_RDX8]]) 1234; CHECK-NEXT: br i1 true, label [[LOOP_EXIT:%.*]], label [[SCALAR_PH]] 1235; CHECK: scalar.ph: 1236; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ 4096, [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ] 1237; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP117]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY]] ] 1238; CHECK-NEXT: br label [[LOOP:%.*]] 1239; CHECK: loop: 1240; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LATCH:%.*]] ] 1241; CHECK-NEXT: [[ACCUM:%.*]] = phi i32 [ [[BC_MERGE_RDX]], [[SCALAR_PH]] ], [ [[ACCUM_NEXT:%.*]], [[LATCH]] ] 1242; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 2 1243; CHECK-NEXT: [[TEST_ADDR:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[IV]] 1244; CHECK-NEXT: [[EARLYCND:%.*]] = load i1, ptr [[TEST_ADDR]], align 1 1245; CHECK-NEXT: br i1 [[EARLYCND]], label [[PRED:%.*]], label [[LATCH]] 1246; CHECK: pred: 1247; CHECK-NEXT: [[ADDR:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[IV]] 1248; CHECK-NEXT: [[VAL:%.*]] = load i32, ptr [[ADDR]], align 4 1249; CHECK-NEXT: br label [[LATCH]] 1250; CHECK: latch: 1251; CHECK-NEXT: [[VAL_PHI:%.*]] = phi i32 [ 0, [[LOOP]] ], [ [[VAL]], [[PRED]] ] 1252; CHECK-NEXT: [[ACCUM_NEXT]] = add i32 [[ACCUM]], [[VAL_PHI]] 1253; CHECK-NEXT: [[EXIT:%.*]] = icmp ugt i64 [[IV]], 4093 1254; CHECK-NEXT: br i1 [[EXIT]], label [[LOOP_EXIT]], label [[LOOP]], !llvm.loop [[LOOP15:![0-9]+]] 1255; CHECK: loop_exit: 1256; CHECK-NEXT: [[ACCUM_NEXT_LCSSA:%.*]] = phi i32 [ [[ACCUM_NEXT]], [[LATCH]] ], [ [[TMP117]], [[MIDDLE_BLOCK]] ] 1257; CHECK-NEXT: ret i32 [[ACCUM_NEXT_LCSSA]] 1258; 1259entry: 1260 %alloca = alloca [4096 x i32] 1261 call void @init(ptr %alloca) 1262 br label %loop 1263loop: 1264 %iv = phi i64 [ 0, %entry ], [ %iv.next, %latch ] 1265 %accum = phi i32 [ 0, %entry ], [ %accum.next, %latch ] 1266 %iv.next = add i64 %iv, 2 1267 %test_addr = getelementptr inbounds i1, ptr %test_base, i64 %iv 1268 %earlycnd = load i1, ptr %test_addr 1269 br i1 %earlycnd, label %pred, label %latch 1270pred: 1271 %addr = getelementptr inbounds i32, ptr %alloca, i64 %iv 1272 %val = load i32, ptr %addr 1273 br label %latch 1274latch: 1275 %val.phi = phi i32 [0, %loop], [%val, %pred] 1276 %accum.next = add i32 %accum, %val.phi 1277 %exit = icmp ugt i64 %iv, 4093 1278 br i1 %exit, label %loop_exit, label %loop 1279 1280loop_exit: 1281 ret i32 %accum.next 1282} 1283 1284define i32 @neg_off_by_many(i64 %len, ptr %test_base) { 1285; CHECK-LABEL: @neg_off_by_many( 1286; CHECK-NEXT: entry: 1287; CHECK-NEXT: [[ALLOCA:%.*]] = alloca [1024 x i32], align 4 1288; CHECK-NEXT: call void @init(ptr [[ALLOCA]]) 1289; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] 1290; CHECK: vector.ph: 1291; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] 1292; CHECK: vector.body: 1293; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] 1294; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP72:%.*]], [[VECTOR_BODY]] ] 1295; CHECK-NEXT: [[VEC_PHI1:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP73:%.*]], [[VECTOR_BODY]] ] 1296; CHECK-NEXT: [[VEC_PHI2:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP74:%.*]], [[VECTOR_BODY]] ] 1297; CHECK-NEXT: [[VEC_PHI3:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP75:%.*]], [[VECTOR_BODY]] ] 1298; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 0 1299; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[INDEX]], 1 1300; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[INDEX]], 2 1301; CHECK-NEXT: [[TMP3:%.*]] = add i64 [[INDEX]], 3 1302; CHECK-NEXT: [[TMP4:%.*]] = add i64 [[INDEX]], 4 1303; CHECK-NEXT: [[TMP5:%.*]] = add i64 [[INDEX]], 5 1304; CHECK-NEXT: [[TMP6:%.*]] = add i64 [[INDEX]], 6 1305; CHECK-NEXT: [[TMP7:%.*]] = add i64 [[INDEX]], 7 1306; CHECK-NEXT: [[TMP8:%.*]] = add i64 [[INDEX]], 8 1307; CHECK-NEXT: [[TMP9:%.*]] = add i64 [[INDEX]], 9 1308; CHECK-NEXT: [[TMP10:%.*]] = add i64 [[INDEX]], 10 1309; CHECK-NEXT: [[TMP11:%.*]] = add i64 [[INDEX]], 11 1310; CHECK-NEXT: [[TMP12:%.*]] = add i64 [[INDEX]], 12 1311; CHECK-NEXT: [[TMP13:%.*]] = add i64 [[INDEX]], 13 1312; CHECK-NEXT: [[TMP14:%.*]] = add i64 [[INDEX]], 14 1313; CHECK-NEXT: [[TMP15:%.*]] = add i64 [[INDEX]], 15 1314; CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE:%.*]], i64 [[TMP0]] 1315; CHECK-NEXT: [[TMP17:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP1]] 1316; CHECK-NEXT: [[TMP18:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP2]] 1317; CHECK-NEXT: [[TMP19:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP3]] 1318; CHECK-NEXT: [[TMP20:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP4]] 1319; CHECK-NEXT: [[TMP21:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP5]] 1320; CHECK-NEXT: [[TMP22:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP6]] 1321; CHECK-NEXT: [[TMP23:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP7]] 1322; CHECK-NEXT: [[TMP24:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP8]] 1323; CHECK-NEXT: [[TMP25:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP9]] 1324; CHECK-NEXT: [[TMP26:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP10]] 1325; CHECK-NEXT: [[TMP27:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP11]] 1326; CHECK-NEXT: [[TMP28:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP12]] 1327; CHECK-NEXT: [[TMP29:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP13]] 1328; CHECK-NEXT: [[TMP30:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP14]] 1329; CHECK-NEXT: [[TMP31:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP15]] 1330; CHECK-NEXT: [[TMP32:%.*]] = load i1, ptr [[TMP16]], align 1 1331; CHECK-NEXT: [[TMP33:%.*]] = load i1, ptr [[TMP17]], align 1 1332; CHECK-NEXT: [[TMP34:%.*]] = load i1, ptr [[TMP18]], align 1 1333; CHECK-NEXT: [[TMP35:%.*]] = load i1, ptr [[TMP19]], align 1 1334; CHECK-NEXT: [[TMP36:%.*]] = insertelement <4 x i1> poison, i1 [[TMP32]], i32 0 1335; CHECK-NEXT: [[TMP37:%.*]] = insertelement <4 x i1> [[TMP36]], i1 [[TMP33]], i32 1 1336; CHECK-NEXT: [[TMP38:%.*]] = insertelement <4 x i1> [[TMP37]], i1 [[TMP34]], i32 2 1337; CHECK-NEXT: [[TMP39:%.*]] = insertelement <4 x i1> [[TMP38]], i1 [[TMP35]], i32 3 1338; CHECK-NEXT: [[TMP40:%.*]] = load i1, ptr [[TMP20]], align 1 1339; CHECK-NEXT: [[TMP41:%.*]] = load i1, ptr [[TMP21]], align 1 1340; CHECK-NEXT: [[TMP42:%.*]] = load i1, ptr [[TMP22]], align 1 1341; CHECK-NEXT: [[TMP43:%.*]] = load i1, ptr [[TMP23]], align 1 1342; CHECK-NEXT: [[TMP44:%.*]] = insertelement <4 x i1> poison, i1 [[TMP40]], i32 0 1343; CHECK-NEXT: [[TMP45:%.*]] = insertelement <4 x i1> [[TMP44]], i1 [[TMP41]], i32 1 1344; CHECK-NEXT: [[TMP46:%.*]] = insertelement <4 x i1> [[TMP45]], i1 [[TMP42]], i32 2 1345; CHECK-NEXT: [[TMP47:%.*]] = insertelement <4 x i1> [[TMP46]], i1 [[TMP43]], i32 3 1346; CHECK-NEXT: [[TMP48:%.*]] = load i1, ptr [[TMP24]], align 1 1347; CHECK-NEXT: [[TMP49:%.*]] = load i1, ptr [[TMP25]], align 1 1348; CHECK-NEXT: [[TMP50:%.*]] = load i1, ptr [[TMP26]], align 1 1349; CHECK-NEXT: [[TMP51:%.*]] = load i1, ptr [[TMP27]], align 1 1350; CHECK-NEXT: [[TMP52:%.*]] = insertelement <4 x i1> poison, i1 [[TMP48]], i32 0 1351; CHECK-NEXT: [[TMP53:%.*]] = insertelement <4 x i1> [[TMP52]], i1 [[TMP49]], i32 1 1352; CHECK-NEXT: [[TMP54:%.*]] = insertelement <4 x i1> [[TMP53]], i1 [[TMP50]], i32 2 1353; CHECK-NEXT: [[TMP55:%.*]] = insertelement <4 x i1> [[TMP54]], i1 [[TMP51]], i32 3 1354; CHECK-NEXT: [[TMP56:%.*]] = load i1, ptr [[TMP28]], align 1 1355; CHECK-NEXT: [[TMP57:%.*]] = load i1, ptr [[TMP29]], align 1 1356; CHECK-NEXT: [[TMP58:%.*]] = load i1, ptr [[TMP30]], align 1 1357; CHECK-NEXT: [[TMP59:%.*]] = load i1, ptr [[TMP31]], align 1 1358; CHECK-NEXT: [[TMP60:%.*]] = insertelement <4 x i1> poison, i1 [[TMP56]], i32 0 1359; CHECK-NEXT: [[TMP61:%.*]] = insertelement <4 x i1> [[TMP60]], i1 [[TMP57]], i32 1 1360; CHECK-NEXT: [[TMP62:%.*]] = insertelement <4 x i1> [[TMP61]], i1 [[TMP58]], i32 2 1361; CHECK-NEXT: [[TMP63:%.*]] = insertelement <4 x i1> [[TMP62]], i1 [[TMP59]], i32 3 1362; CHECK-NEXT: [[TMP64:%.*]] = getelementptr i32, ptr [[ALLOCA]], i64 [[TMP0]] 1363; CHECK-NEXT: [[TMP68:%.*]] = getelementptr i32, ptr [[TMP64]], i32 0 1364; CHECK-NEXT: [[TMP69:%.*]] = getelementptr i32, ptr [[TMP64]], i32 4 1365; CHECK-NEXT: [[TMP70:%.*]] = getelementptr i32, ptr [[TMP64]], i32 8 1366; CHECK-NEXT: [[TMP71:%.*]] = getelementptr i32, ptr [[TMP64]], i32 12 1367; CHECK-NEXT: [[WIDE_MASKED_LOAD:%.*]] = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr [[TMP68]], i32 4, <4 x i1> [[TMP39]], <4 x i32> poison) 1368; CHECK-NEXT: [[WIDE_MASKED_LOAD4:%.*]] = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr [[TMP69]], i32 4, <4 x i1> [[TMP47]], <4 x i32> poison) 1369; CHECK-NEXT: [[WIDE_MASKED_LOAD5:%.*]] = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr [[TMP70]], i32 4, <4 x i1> [[TMP55]], <4 x i32> poison) 1370; CHECK-NEXT: [[WIDE_MASKED_LOAD6:%.*]] = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr [[TMP71]], i32 4, <4 x i1> [[TMP63]], <4 x i32> poison) 1371; CHECK-NEXT: [[PREDPHI:%.*]] = select <4 x i1> [[TMP39]], <4 x i32> [[WIDE_MASKED_LOAD]], <4 x i32> zeroinitializer 1372; CHECK-NEXT: [[PREDPHI7:%.*]] = select <4 x i1> [[TMP47]], <4 x i32> [[WIDE_MASKED_LOAD4]], <4 x i32> zeroinitializer 1373; CHECK-NEXT: [[PREDPHI8:%.*]] = select <4 x i1> [[TMP55]], <4 x i32> [[WIDE_MASKED_LOAD5]], <4 x i32> zeroinitializer 1374; CHECK-NEXT: [[PREDPHI9:%.*]] = select <4 x i1> [[TMP63]], <4 x i32> [[WIDE_MASKED_LOAD6]], <4 x i32> zeroinitializer 1375; CHECK-NEXT: [[TMP72]] = add <4 x i32> [[VEC_PHI]], [[PREDPHI]] 1376; CHECK-NEXT: [[TMP73]] = add <4 x i32> [[VEC_PHI1]], [[PREDPHI7]] 1377; CHECK-NEXT: [[TMP74]] = add <4 x i32> [[VEC_PHI2]], [[PREDPHI8]] 1378; CHECK-NEXT: [[TMP75]] = add <4 x i32> [[VEC_PHI3]], [[PREDPHI9]] 1379; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16 1380; CHECK-NEXT: [[TMP76:%.*]] = icmp eq i64 [[INDEX_NEXT]], 4096 1381; CHECK-NEXT: br i1 [[TMP76]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP16:![0-9]+]] 1382; CHECK: middle.block: 1383; CHECK-NEXT: [[BIN_RDX:%.*]] = add <4 x i32> [[TMP73]], [[TMP72]] 1384; CHECK-NEXT: [[BIN_RDX10:%.*]] = add <4 x i32> [[TMP74]], [[BIN_RDX]] 1385; CHECK-NEXT: [[BIN_RDX11:%.*]] = add <4 x i32> [[TMP75]], [[BIN_RDX10]] 1386; CHECK-NEXT: [[TMP77:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[BIN_RDX11]]) 1387; CHECK-NEXT: br i1 true, label [[LOOP_EXIT:%.*]], label [[SCALAR_PH]] 1388; CHECK: scalar.ph: 1389; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ 4096, [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ] 1390; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP77]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY]] ] 1391; CHECK-NEXT: br label [[LOOP:%.*]] 1392; CHECK: loop: 1393; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LATCH:%.*]] ] 1394; CHECK-NEXT: [[ACCUM:%.*]] = phi i32 [ [[BC_MERGE_RDX]], [[SCALAR_PH]] ], [ [[ACCUM_NEXT:%.*]], [[LATCH]] ] 1395; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1 1396; CHECK-NEXT: [[TEST_ADDR:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[IV]] 1397; CHECK-NEXT: [[EARLYCND:%.*]] = load i1, ptr [[TEST_ADDR]], align 1 1398; CHECK-NEXT: br i1 [[EARLYCND]], label [[PRED:%.*]], label [[LATCH]] 1399; CHECK: pred: 1400; CHECK-NEXT: [[ADDR:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[IV]] 1401; CHECK-NEXT: [[VAL:%.*]] = load i32, ptr [[ADDR]], align 4 1402; CHECK-NEXT: br label [[LATCH]] 1403; CHECK: latch: 1404; CHECK-NEXT: [[VAL_PHI:%.*]] = phi i32 [ 0, [[LOOP]] ], [ [[VAL]], [[PRED]] ] 1405; CHECK-NEXT: [[ACCUM_NEXT]] = add i32 [[ACCUM]], [[VAL_PHI]] 1406; CHECK-NEXT: [[EXIT:%.*]] = icmp ugt i64 [[IV]], 4094 1407; CHECK-NEXT: br i1 [[EXIT]], label [[LOOP_EXIT]], label [[LOOP]], !llvm.loop [[LOOP17:![0-9]+]] 1408; CHECK: loop_exit: 1409; CHECK-NEXT: [[ACCUM_NEXT_LCSSA:%.*]] = phi i32 [ [[ACCUM_NEXT]], [[LATCH]] ], [ [[TMP77]], [[MIDDLE_BLOCK]] ] 1410; CHECK-NEXT: ret i32 [[ACCUM_NEXT_LCSSA]] 1411; 1412entry: 1413 %alloca = alloca [1024 x i32] 1414 call void @init(ptr %alloca) 1415 br label %loop 1416loop: 1417 %iv = phi i64 [ 0, %entry ], [ %iv.next, %latch ] 1418 %accum = phi i32 [ 0, %entry ], [ %accum.next, %latch ] 1419 %iv.next = add i64 %iv, 1 1420 %test_addr = getelementptr inbounds i1, ptr %test_base, i64 %iv 1421 %earlycnd = load i1, ptr %test_addr 1422 br i1 %earlycnd, label %pred, label %latch 1423pred: 1424 %addr = getelementptr inbounds i32, ptr %alloca, i64 %iv 1425 %val = load i32, ptr %addr 1426 br label %latch 1427latch: 1428 %val.phi = phi i32 [0, %loop], [%val, %pred] 1429 %accum.next = add i32 %accum, %val.phi 1430 %exit = icmp ugt i64 %iv, 4094 1431 br i1 %exit, label %loop_exit, label %loop 1432 1433loop_exit: 1434 ret i32 %accum.next 1435} 1436 1437define i32 @neg_off_by_one_iteration(i64 %len, ptr %test_base) { 1438; CHECK-LABEL: @neg_off_by_one_iteration( 1439; CHECK-NEXT: entry: 1440; CHECK-NEXT: [[ALLOCA:%.*]] = alloca [4095 x i32], align 4 1441; CHECK-NEXT: call void @init(ptr [[ALLOCA]]) 1442; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] 1443; CHECK: vector.ph: 1444; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] 1445; CHECK: vector.body: 1446; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] 1447; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP72:%.*]], [[VECTOR_BODY]] ] 1448; CHECK-NEXT: [[VEC_PHI1:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP73:%.*]], [[VECTOR_BODY]] ] 1449; CHECK-NEXT: [[VEC_PHI2:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP74:%.*]], [[VECTOR_BODY]] ] 1450; CHECK-NEXT: [[VEC_PHI3:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP75:%.*]], [[VECTOR_BODY]] ] 1451; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 0 1452; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[INDEX]], 1 1453; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[INDEX]], 2 1454; CHECK-NEXT: [[TMP3:%.*]] = add i64 [[INDEX]], 3 1455; CHECK-NEXT: [[TMP4:%.*]] = add i64 [[INDEX]], 4 1456; CHECK-NEXT: [[TMP5:%.*]] = add i64 [[INDEX]], 5 1457; CHECK-NEXT: [[TMP6:%.*]] = add i64 [[INDEX]], 6 1458; CHECK-NEXT: [[TMP7:%.*]] = add i64 [[INDEX]], 7 1459; CHECK-NEXT: [[TMP8:%.*]] = add i64 [[INDEX]], 8 1460; CHECK-NEXT: [[TMP9:%.*]] = add i64 [[INDEX]], 9 1461; CHECK-NEXT: [[TMP10:%.*]] = add i64 [[INDEX]], 10 1462; CHECK-NEXT: [[TMP11:%.*]] = add i64 [[INDEX]], 11 1463; CHECK-NEXT: [[TMP12:%.*]] = add i64 [[INDEX]], 12 1464; CHECK-NEXT: [[TMP13:%.*]] = add i64 [[INDEX]], 13 1465; CHECK-NEXT: [[TMP14:%.*]] = add i64 [[INDEX]], 14 1466; CHECK-NEXT: [[TMP15:%.*]] = add i64 [[INDEX]], 15 1467; CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE:%.*]], i64 [[TMP0]] 1468; CHECK-NEXT: [[TMP17:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP1]] 1469; CHECK-NEXT: [[TMP18:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP2]] 1470; CHECK-NEXT: [[TMP19:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP3]] 1471; CHECK-NEXT: [[TMP20:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP4]] 1472; CHECK-NEXT: [[TMP21:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP5]] 1473; CHECK-NEXT: [[TMP22:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP6]] 1474; CHECK-NEXT: [[TMP23:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP7]] 1475; CHECK-NEXT: [[TMP24:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP8]] 1476; CHECK-NEXT: [[TMP25:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP9]] 1477; CHECK-NEXT: [[TMP26:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP10]] 1478; CHECK-NEXT: [[TMP27:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP11]] 1479; CHECK-NEXT: [[TMP28:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP12]] 1480; CHECK-NEXT: [[TMP29:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP13]] 1481; CHECK-NEXT: [[TMP30:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP14]] 1482; CHECK-NEXT: [[TMP31:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP15]] 1483; CHECK-NEXT: [[TMP32:%.*]] = load i1, ptr [[TMP16]], align 1 1484; CHECK-NEXT: [[TMP33:%.*]] = load i1, ptr [[TMP17]], align 1 1485; CHECK-NEXT: [[TMP34:%.*]] = load i1, ptr [[TMP18]], align 1 1486; CHECK-NEXT: [[TMP35:%.*]] = load i1, ptr [[TMP19]], align 1 1487; CHECK-NEXT: [[TMP36:%.*]] = insertelement <4 x i1> poison, i1 [[TMP32]], i32 0 1488; CHECK-NEXT: [[TMP37:%.*]] = insertelement <4 x i1> [[TMP36]], i1 [[TMP33]], i32 1 1489; CHECK-NEXT: [[TMP38:%.*]] = insertelement <4 x i1> [[TMP37]], i1 [[TMP34]], i32 2 1490; CHECK-NEXT: [[TMP39:%.*]] = insertelement <4 x i1> [[TMP38]], i1 [[TMP35]], i32 3 1491; CHECK-NEXT: [[TMP40:%.*]] = load i1, ptr [[TMP20]], align 1 1492; CHECK-NEXT: [[TMP41:%.*]] = load i1, ptr [[TMP21]], align 1 1493; CHECK-NEXT: [[TMP42:%.*]] = load i1, ptr [[TMP22]], align 1 1494; CHECK-NEXT: [[TMP43:%.*]] = load i1, ptr [[TMP23]], align 1 1495; CHECK-NEXT: [[TMP44:%.*]] = insertelement <4 x i1> poison, i1 [[TMP40]], i32 0 1496; CHECK-NEXT: [[TMP45:%.*]] = insertelement <4 x i1> [[TMP44]], i1 [[TMP41]], i32 1 1497; CHECK-NEXT: [[TMP46:%.*]] = insertelement <4 x i1> [[TMP45]], i1 [[TMP42]], i32 2 1498; CHECK-NEXT: [[TMP47:%.*]] = insertelement <4 x i1> [[TMP46]], i1 [[TMP43]], i32 3 1499; CHECK-NEXT: [[TMP48:%.*]] = load i1, ptr [[TMP24]], align 1 1500; CHECK-NEXT: [[TMP49:%.*]] = load i1, ptr [[TMP25]], align 1 1501; CHECK-NEXT: [[TMP50:%.*]] = load i1, ptr [[TMP26]], align 1 1502; CHECK-NEXT: [[TMP51:%.*]] = load i1, ptr [[TMP27]], align 1 1503; CHECK-NEXT: [[TMP52:%.*]] = insertelement <4 x i1> poison, i1 [[TMP48]], i32 0 1504; CHECK-NEXT: [[TMP53:%.*]] = insertelement <4 x i1> [[TMP52]], i1 [[TMP49]], i32 1 1505; CHECK-NEXT: [[TMP54:%.*]] = insertelement <4 x i1> [[TMP53]], i1 [[TMP50]], i32 2 1506; CHECK-NEXT: [[TMP55:%.*]] = insertelement <4 x i1> [[TMP54]], i1 [[TMP51]], i32 3 1507; CHECK-NEXT: [[TMP56:%.*]] = load i1, ptr [[TMP28]], align 1 1508; CHECK-NEXT: [[TMP57:%.*]] = load i1, ptr [[TMP29]], align 1 1509; CHECK-NEXT: [[TMP58:%.*]] = load i1, ptr [[TMP30]], align 1 1510; CHECK-NEXT: [[TMP59:%.*]] = load i1, ptr [[TMP31]], align 1 1511; CHECK-NEXT: [[TMP60:%.*]] = insertelement <4 x i1> poison, i1 [[TMP56]], i32 0 1512; CHECK-NEXT: [[TMP61:%.*]] = insertelement <4 x i1> [[TMP60]], i1 [[TMP57]], i32 1 1513; CHECK-NEXT: [[TMP62:%.*]] = insertelement <4 x i1> [[TMP61]], i1 [[TMP58]], i32 2 1514; CHECK-NEXT: [[TMP63:%.*]] = insertelement <4 x i1> [[TMP62]], i1 [[TMP59]], i32 3 1515; CHECK-NEXT: [[TMP64:%.*]] = getelementptr i32, ptr [[ALLOCA]], i64 [[TMP0]] 1516; CHECK-NEXT: [[TMP68:%.*]] = getelementptr i32, ptr [[TMP64]], i32 0 1517; CHECK-NEXT: [[TMP69:%.*]] = getelementptr i32, ptr [[TMP64]], i32 4 1518; CHECK-NEXT: [[TMP70:%.*]] = getelementptr i32, ptr [[TMP64]], i32 8 1519; CHECK-NEXT: [[TMP71:%.*]] = getelementptr i32, ptr [[TMP64]], i32 12 1520; CHECK-NEXT: [[WIDE_MASKED_LOAD:%.*]] = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr [[TMP68]], i32 4, <4 x i1> [[TMP39]], <4 x i32> poison) 1521; CHECK-NEXT: [[WIDE_MASKED_LOAD4:%.*]] = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr [[TMP69]], i32 4, <4 x i1> [[TMP47]], <4 x i32> poison) 1522; CHECK-NEXT: [[WIDE_MASKED_LOAD5:%.*]] = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr [[TMP70]], i32 4, <4 x i1> [[TMP55]], <4 x i32> poison) 1523; CHECK-NEXT: [[WIDE_MASKED_LOAD6:%.*]] = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr [[TMP71]], i32 4, <4 x i1> [[TMP63]], <4 x i32> poison) 1524; CHECK-NEXT: [[PREDPHI:%.*]] = select <4 x i1> [[TMP39]], <4 x i32> [[WIDE_MASKED_LOAD]], <4 x i32> zeroinitializer 1525; CHECK-NEXT: [[PREDPHI7:%.*]] = select <4 x i1> [[TMP47]], <4 x i32> [[WIDE_MASKED_LOAD4]], <4 x i32> zeroinitializer 1526; CHECK-NEXT: [[PREDPHI8:%.*]] = select <4 x i1> [[TMP55]], <4 x i32> [[WIDE_MASKED_LOAD5]], <4 x i32> zeroinitializer 1527; CHECK-NEXT: [[PREDPHI9:%.*]] = select <4 x i1> [[TMP63]], <4 x i32> [[WIDE_MASKED_LOAD6]], <4 x i32> zeroinitializer 1528; CHECK-NEXT: [[TMP72]] = add <4 x i32> [[VEC_PHI]], [[PREDPHI]] 1529; CHECK-NEXT: [[TMP73]] = add <4 x i32> [[VEC_PHI1]], [[PREDPHI7]] 1530; CHECK-NEXT: [[TMP74]] = add <4 x i32> [[VEC_PHI2]], [[PREDPHI8]] 1531; CHECK-NEXT: [[TMP75]] = add <4 x i32> [[VEC_PHI3]], [[PREDPHI9]] 1532; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16 1533; CHECK-NEXT: [[TMP76:%.*]] = icmp eq i64 [[INDEX_NEXT]], 4096 1534; CHECK-NEXT: br i1 [[TMP76]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP18:![0-9]+]] 1535; CHECK: middle.block: 1536; CHECK-NEXT: [[BIN_RDX:%.*]] = add <4 x i32> [[TMP73]], [[TMP72]] 1537; CHECK-NEXT: [[BIN_RDX10:%.*]] = add <4 x i32> [[TMP74]], [[BIN_RDX]] 1538; CHECK-NEXT: [[BIN_RDX11:%.*]] = add <4 x i32> [[TMP75]], [[BIN_RDX10]] 1539; CHECK-NEXT: [[TMP77:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[BIN_RDX11]]) 1540; CHECK-NEXT: br i1 true, label [[LOOP_EXIT:%.*]], label [[SCALAR_PH]] 1541; CHECK: scalar.ph: 1542; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ 4096, [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ] 1543; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP77]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY]] ] 1544; CHECK-NEXT: br label [[LOOP:%.*]] 1545; CHECK: loop: 1546; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LATCH:%.*]] ] 1547; CHECK-NEXT: [[ACCUM:%.*]] = phi i32 [ [[BC_MERGE_RDX]], [[SCALAR_PH]] ], [ [[ACCUM_NEXT:%.*]], [[LATCH]] ] 1548; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1 1549; CHECK-NEXT: [[TEST_ADDR:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[IV]] 1550; CHECK-NEXT: [[EARLYCND:%.*]] = load i1, ptr [[TEST_ADDR]], align 1 1551; CHECK-NEXT: br i1 [[EARLYCND]], label [[PRED:%.*]], label [[LATCH]] 1552; CHECK: pred: 1553; CHECK-NEXT: [[ADDR:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[IV]] 1554; CHECK-NEXT: [[VAL:%.*]] = load i32, ptr [[ADDR]], align 4 1555; CHECK-NEXT: br label [[LATCH]] 1556; CHECK: latch: 1557; CHECK-NEXT: [[VAL_PHI:%.*]] = phi i32 [ 0, [[LOOP]] ], [ [[VAL]], [[PRED]] ] 1558; CHECK-NEXT: [[ACCUM_NEXT]] = add i32 [[ACCUM]], [[VAL_PHI]] 1559; CHECK-NEXT: [[EXIT:%.*]] = icmp ugt i64 [[IV]], 4094 1560; CHECK-NEXT: br i1 [[EXIT]], label [[LOOP_EXIT]], label [[LOOP]], !llvm.loop [[LOOP19:![0-9]+]] 1561; CHECK: loop_exit: 1562; CHECK-NEXT: [[ACCUM_NEXT_LCSSA:%.*]] = phi i32 [ [[ACCUM_NEXT]], [[LATCH]] ], [ [[TMP77]], [[MIDDLE_BLOCK]] ] 1563; CHECK-NEXT: ret i32 [[ACCUM_NEXT_LCSSA]] 1564; 1565entry: 1566 %alloca = alloca [4095 x i32] 1567 call void @init(ptr %alloca) 1568 br label %loop 1569loop: 1570 %iv = phi i64 [ 0, %entry ], [ %iv.next, %latch ] 1571 %accum = phi i32 [ 0, %entry ], [ %accum.next, %latch ] 1572 %iv.next = add i64 %iv, 1 1573 %test_addr = getelementptr inbounds i1, ptr %test_base, i64 %iv 1574 %earlycnd = load i1, ptr %test_addr 1575 br i1 %earlycnd, label %pred, label %latch 1576pred: 1577 %addr = getelementptr inbounds i32, ptr %alloca, i64 %iv 1578 %val = load i32, ptr %addr 1579 br label %latch 1580latch: 1581 %val.phi = phi i32 [0, %loop], [%val, %pred] 1582 %accum.next = add i32 %accum, %val.phi 1583 %exit = icmp ugt i64 %iv, 4094 1584 br i1 %exit, label %loop_exit, label %loop 1585 1586loop_exit: 1587 ret i32 %accum.next 1588} 1589 1590define i32 @neg_off_by_one_byte(i64 %len, ptr %test_base) { 1591; CHECK-LABEL: @neg_off_by_one_byte( 1592; CHECK-NEXT: entry: 1593; CHECK-NEXT: [[ALLOCA:%.*]] = alloca [16383 x i8], align 1 1594; CHECK-NEXT: call void @init(ptr [[ALLOCA]]) 1595; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] 1596; CHECK: vector.ph: 1597; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] 1598; CHECK: vector.body: 1599; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] 1600; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP72:%.*]], [[VECTOR_BODY]] ] 1601; CHECK-NEXT: [[VEC_PHI1:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP73:%.*]], [[VECTOR_BODY]] ] 1602; CHECK-NEXT: [[VEC_PHI2:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP74:%.*]], [[VECTOR_BODY]] ] 1603; CHECK-NEXT: [[VEC_PHI3:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP75:%.*]], [[VECTOR_BODY]] ] 1604; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 0 1605; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[INDEX]], 1 1606; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[INDEX]], 2 1607; CHECK-NEXT: [[TMP3:%.*]] = add i64 [[INDEX]], 3 1608; CHECK-NEXT: [[TMP4:%.*]] = add i64 [[INDEX]], 4 1609; CHECK-NEXT: [[TMP5:%.*]] = add i64 [[INDEX]], 5 1610; CHECK-NEXT: [[TMP6:%.*]] = add i64 [[INDEX]], 6 1611; CHECK-NEXT: [[TMP7:%.*]] = add i64 [[INDEX]], 7 1612; CHECK-NEXT: [[TMP8:%.*]] = add i64 [[INDEX]], 8 1613; CHECK-NEXT: [[TMP9:%.*]] = add i64 [[INDEX]], 9 1614; CHECK-NEXT: [[TMP10:%.*]] = add i64 [[INDEX]], 10 1615; CHECK-NEXT: [[TMP11:%.*]] = add i64 [[INDEX]], 11 1616; CHECK-NEXT: [[TMP12:%.*]] = add i64 [[INDEX]], 12 1617; CHECK-NEXT: [[TMP13:%.*]] = add i64 [[INDEX]], 13 1618; CHECK-NEXT: [[TMP14:%.*]] = add i64 [[INDEX]], 14 1619; CHECK-NEXT: [[TMP15:%.*]] = add i64 [[INDEX]], 15 1620; CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE:%.*]], i64 [[TMP0]] 1621; CHECK-NEXT: [[TMP17:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP1]] 1622; CHECK-NEXT: [[TMP18:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP2]] 1623; CHECK-NEXT: [[TMP19:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP3]] 1624; CHECK-NEXT: [[TMP20:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP4]] 1625; CHECK-NEXT: [[TMP21:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP5]] 1626; CHECK-NEXT: [[TMP22:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP6]] 1627; CHECK-NEXT: [[TMP23:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP7]] 1628; CHECK-NEXT: [[TMP24:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP8]] 1629; CHECK-NEXT: [[TMP25:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP9]] 1630; CHECK-NEXT: [[TMP26:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP10]] 1631; CHECK-NEXT: [[TMP27:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP11]] 1632; CHECK-NEXT: [[TMP28:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP12]] 1633; CHECK-NEXT: [[TMP29:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP13]] 1634; CHECK-NEXT: [[TMP30:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP14]] 1635; CHECK-NEXT: [[TMP31:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP15]] 1636; CHECK-NEXT: [[TMP32:%.*]] = load i1, ptr [[TMP16]], align 1 1637; CHECK-NEXT: [[TMP33:%.*]] = load i1, ptr [[TMP17]], align 1 1638; CHECK-NEXT: [[TMP34:%.*]] = load i1, ptr [[TMP18]], align 1 1639; CHECK-NEXT: [[TMP35:%.*]] = load i1, ptr [[TMP19]], align 1 1640; CHECK-NEXT: [[TMP36:%.*]] = insertelement <4 x i1> poison, i1 [[TMP32]], i32 0 1641; CHECK-NEXT: [[TMP37:%.*]] = insertelement <4 x i1> [[TMP36]], i1 [[TMP33]], i32 1 1642; CHECK-NEXT: [[TMP38:%.*]] = insertelement <4 x i1> [[TMP37]], i1 [[TMP34]], i32 2 1643; CHECK-NEXT: [[TMP39:%.*]] = insertelement <4 x i1> [[TMP38]], i1 [[TMP35]], i32 3 1644; CHECK-NEXT: [[TMP40:%.*]] = load i1, ptr [[TMP20]], align 1 1645; CHECK-NEXT: [[TMP41:%.*]] = load i1, ptr [[TMP21]], align 1 1646; CHECK-NEXT: [[TMP42:%.*]] = load i1, ptr [[TMP22]], align 1 1647; CHECK-NEXT: [[TMP43:%.*]] = load i1, ptr [[TMP23]], align 1 1648; CHECK-NEXT: [[TMP44:%.*]] = insertelement <4 x i1> poison, i1 [[TMP40]], i32 0 1649; CHECK-NEXT: [[TMP45:%.*]] = insertelement <4 x i1> [[TMP44]], i1 [[TMP41]], i32 1 1650; CHECK-NEXT: [[TMP46:%.*]] = insertelement <4 x i1> [[TMP45]], i1 [[TMP42]], i32 2 1651; CHECK-NEXT: [[TMP47:%.*]] = insertelement <4 x i1> [[TMP46]], i1 [[TMP43]], i32 3 1652; CHECK-NEXT: [[TMP48:%.*]] = load i1, ptr [[TMP24]], align 1 1653; CHECK-NEXT: [[TMP49:%.*]] = load i1, ptr [[TMP25]], align 1 1654; CHECK-NEXT: [[TMP50:%.*]] = load i1, ptr [[TMP26]], align 1 1655; CHECK-NEXT: [[TMP51:%.*]] = load i1, ptr [[TMP27]], align 1 1656; CHECK-NEXT: [[TMP52:%.*]] = insertelement <4 x i1> poison, i1 [[TMP48]], i32 0 1657; CHECK-NEXT: [[TMP53:%.*]] = insertelement <4 x i1> [[TMP52]], i1 [[TMP49]], i32 1 1658; CHECK-NEXT: [[TMP54:%.*]] = insertelement <4 x i1> [[TMP53]], i1 [[TMP50]], i32 2 1659; CHECK-NEXT: [[TMP55:%.*]] = insertelement <4 x i1> [[TMP54]], i1 [[TMP51]], i32 3 1660; CHECK-NEXT: [[TMP56:%.*]] = load i1, ptr [[TMP28]], align 1 1661; CHECK-NEXT: [[TMP57:%.*]] = load i1, ptr [[TMP29]], align 1 1662; CHECK-NEXT: [[TMP58:%.*]] = load i1, ptr [[TMP30]], align 1 1663; CHECK-NEXT: [[TMP59:%.*]] = load i1, ptr [[TMP31]], align 1 1664; CHECK-NEXT: [[TMP60:%.*]] = insertelement <4 x i1> poison, i1 [[TMP56]], i32 0 1665; CHECK-NEXT: [[TMP61:%.*]] = insertelement <4 x i1> [[TMP60]], i1 [[TMP57]], i32 1 1666; CHECK-NEXT: [[TMP62:%.*]] = insertelement <4 x i1> [[TMP61]], i1 [[TMP58]], i32 2 1667; CHECK-NEXT: [[TMP63:%.*]] = insertelement <4 x i1> [[TMP62]], i1 [[TMP59]], i32 3 1668; CHECK-NEXT: [[TMP64:%.*]] = getelementptr i32, ptr [[ALLOCA]], i64 [[TMP0]] 1669; CHECK-NEXT: [[TMP68:%.*]] = getelementptr i32, ptr [[TMP64]], i32 0 1670; CHECK-NEXT: [[TMP69:%.*]] = getelementptr i32, ptr [[TMP64]], i32 4 1671; CHECK-NEXT: [[TMP70:%.*]] = getelementptr i32, ptr [[TMP64]], i32 8 1672; CHECK-NEXT: [[TMP71:%.*]] = getelementptr i32, ptr [[TMP64]], i32 12 1673; CHECK-NEXT: [[WIDE_MASKED_LOAD:%.*]] = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr [[TMP68]], i32 4, <4 x i1> [[TMP39]], <4 x i32> poison) 1674; CHECK-NEXT: [[WIDE_MASKED_LOAD4:%.*]] = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr [[TMP69]], i32 4, <4 x i1> [[TMP47]], <4 x i32> poison) 1675; CHECK-NEXT: [[WIDE_MASKED_LOAD5:%.*]] = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr [[TMP70]], i32 4, <4 x i1> [[TMP55]], <4 x i32> poison) 1676; CHECK-NEXT: [[WIDE_MASKED_LOAD6:%.*]] = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr [[TMP71]], i32 4, <4 x i1> [[TMP63]], <4 x i32> poison) 1677; CHECK-NEXT: [[PREDPHI:%.*]] = select <4 x i1> [[TMP39]], <4 x i32> [[WIDE_MASKED_LOAD]], <4 x i32> zeroinitializer 1678; CHECK-NEXT: [[PREDPHI7:%.*]] = select <4 x i1> [[TMP47]], <4 x i32> [[WIDE_MASKED_LOAD4]], <4 x i32> zeroinitializer 1679; CHECK-NEXT: [[PREDPHI8:%.*]] = select <4 x i1> [[TMP55]], <4 x i32> [[WIDE_MASKED_LOAD5]], <4 x i32> zeroinitializer 1680; CHECK-NEXT: [[PREDPHI9:%.*]] = select <4 x i1> [[TMP63]], <4 x i32> [[WIDE_MASKED_LOAD6]], <4 x i32> zeroinitializer 1681; CHECK-NEXT: [[TMP72]] = add <4 x i32> [[VEC_PHI]], [[PREDPHI]] 1682; CHECK-NEXT: [[TMP73]] = add <4 x i32> [[VEC_PHI1]], [[PREDPHI7]] 1683; CHECK-NEXT: [[TMP74]] = add <4 x i32> [[VEC_PHI2]], [[PREDPHI8]] 1684; CHECK-NEXT: [[TMP75]] = add <4 x i32> [[VEC_PHI3]], [[PREDPHI9]] 1685; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16 1686; CHECK-NEXT: [[TMP76:%.*]] = icmp eq i64 [[INDEX_NEXT]], 4096 1687; CHECK-NEXT: br i1 [[TMP76]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP20:![0-9]+]] 1688; CHECK: middle.block: 1689; CHECK-NEXT: [[BIN_RDX:%.*]] = add <4 x i32> [[TMP73]], [[TMP72]] 1690; CHECK-NEXT: [[BIN_RDX10:%.*]] = add <4 x i32> [[TMP74]], [[BIN_RDX]] 1691; CHECK-NEXT: [[BIN_RDX11:%.*]] = add <4 x i32> [[TMP75]], [[BIN_RDX10]] 1692; CHECK-NEXT: [[TMP77:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[BIN_RDX11]]) 1693; CHECK-NEXT: br i1 true, label [[LOOP_EXIT:%.*]], label [[SCALAR_PH]] 1694; CHECK: scalar.ph: 1695; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ 4096, [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ] 1696; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP77]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY]] ] 1697; CHECK-NEXT: br label [[LOOP:%.*]] 1698; CHECK: loop: 1699; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LATCH:%.*]] ] 1700; CHECK-NEXT: [[ACCUM:%.*]] = phi i32 [ [[BC_MERGE_RDX]], [[SCALAR_PH]] ], [ [[ACCUM_NEXT:%.*]], [[LATCH]] ] 1701; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1 1702; CHECK-NEXT: [[TEST_ADDR:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[IV]] 1703; CHECK-NEXT: [[EARLYCND:%.*]] = load i1, ptr [[TEST_ADDR]], align 1 1704; CHECK-NEXT: br i1 [[EARLYCND]], label [[PRED:%.*]], label [[LATCH]] 1705; CHECK: pred: 1706; CHECK-NEXT: [[ADDR:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[IV]] 1707; CHECK-NEXT: [[VAL:%.*]] = load i32, ptr [[ADDR]], align 4 1708; CHECK-NEXT: br label [[LATCH]] 1709; CHECK: latch: 1710; CHECK-NEXT: [[VAL_PHI:%.*]] = phi i32 [ 0, [[LOOP]] ], [ [[VAL]], [[PRED]] ] 1711; CHECK-NEXT: [[ACCUM_NEXT]] = add i32 [[ACCUM]], [[VAL_PHI]] 1712; CHECK-NEXT: [[EXIT:%.*]] = icmp ugt i64 [[IV]], 4094 1713; CHECK-NEXT: br i1 [[EXIT]], label [[LOOP_EXIT]], label [[LOOP]], !llvm.loop [[LOOP21:![0-9]+]] 1714; CHECK: loop_exit: 1715; CHECK-NEXT: [[ACCUM_NEXT_LCSSA:%.*]] = phi i32 [ [[ACCUM_NEXT]], [[LATCH]] ], [ [[TMP77]], [[MIDDLE_BLOCK]] ] 1716; CHECK-NEXT: ret i32 [[ACCUM_NEXT_LCSSA]] 1717; 1718entry: 1719 %alloca = alloca [16383 x i8] 1720 call void @init(ptr %alloca) 1721 br label %loop 1722loop: 1723 %iv = phi i64 [ 0, %entry ], [ %iv.next, %latch ] 1724 %accum = phi i32 [ 0, %entry ], [ %accum.next, %latch ] 1725 %iv.next = add i64 %iv, 1 1726 %test_addr = getelementptr inbounds i1, ptr %test_base, i64 %iv 1727 %earlycnd = load i1, ptr %test_addr 1728 br i1 %earlycnd, label %pred, label %latch 1729pred: 1730 %addr = getelementptr inbounds i32, ptr %alloca, i64 %iv 1731 %val = load i32, ptr %addr 1732 br label %latch 1733latch: 1734 %val.phi = phi i32 [0, %loop], [%val, %pred] 1735 %accum.next = add i32 %accum, %val.phi 1736 %exit = icmp ugt i64 %iv, 4094 1737 br i1 %exit, label %loop_exit, label %loop 1738 1739loop_exit: 1740 ret i32 %accum.next 1741} 1742 1743 1744; Show that we handle case where exit count is non-constant, but that we 1745; have a constant bound on it which is sufficient to show dereferenceability. 1746define i32 @test_constant_max(i64 %len, ptr %test_base) { 1747; CHECK-LABEL: @test_constant_max( 1748; CHECK-NEXT: entry: 1749; CHECK-NEXT: [[ALLOCA:%.*]] = alloca [4096 x i32], align 4 1750; CHECK-NEXT: call void @init(ptr [[ALLOCA]]) 1751; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i64 [[LEN:%.*]], 4094 1752; CHECK-NEXT: [[MIN:%.*]] = select i1 [[CMP]], i64 4094, i64 [[LEN]] 1753; CHECK-NEXT: [[TMP0:%.*]] = add nuw nsw i64 [[MIN]], 2 1754; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP0]], 16 1755; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] 1756; CHECK: vector.ph: 1757; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP0]], 16 1758; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP0]], [[N_MOD_VF]] 1759; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] 1760; CHECK: vector.body: 1761; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] 1762; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP73:%.*]], [[VECTOR_BODY]] ] 1763; CHECK-NEXT: [[VEC_PHI1:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP74:%.*]], [[VECTOR_BODY]] ] 1764; CHECK-NEXT: [[VEC_PHI2:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP75:%.*]], [[VECTOR_BODY]] ] 1765; CHECK-NEXT: [[VEC_PHI3:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP76:%.*]], [[VECTOR_BODY]] ] 1766; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[INDEX]], 0 1767; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[INDEX]], 1 1768; CHECK-NEXT: [[TMP3:%.*]] = add i64 [[INDEX]], 2 1769; CHECK-NEXT: [[TMP4:%.*]] = add i64 [[INDEX]], 3 1770; CHECK-NEXT: [[TMP5:%.*]] = add i64 [[INDEX]], 4 1771; CHECK-NEXT: [[TMP6:%.*]] = add i64 [[INDEX]], 5 1772; CHECK-NEXT: [[TMP7:%.*]] = add i64 [[INDEX]], 6 1773; CHECK-NEXT: [[TMP8:%.*]] = add i64 [[INDEX]], 7 1774; CHECK-NEXT: [[TMP9:%.*]] = add i64 [[INDEX]], 8 1775; CHECK-NEXT: [[TMP10:%.*]] = add i64 [[INDEX]], 9 1776; CHECK-NEXT: [[TMP11:%.*]] = add i64 [[INDEX]], 10 1777; CHECK-NEXT: [[TMP12:%.*]] = add i64 [[INDEX]], 11 1778; CHECK-NEXT: [[TMP13:%.*]] = add i64 [[INDEX]], 12 1779; CHECK-NEXT: [[TMP14:%.*]] = add i64 [[INDEX]], 13 1780; CHECK-NEXT: [[TMP15:%.*]] = add i64 [[INDEX]], 14 1781; CHECK-NEXT: [[TMP16:%.*]] = add i64 [[INDEX]], 15 1782; CHECK-NEXT: [[TMP17:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE:%.*]], i64 [[TMP1]] 1783; CHECK-NEXT: [[TMP18:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP2]] 1784; CHECK-NEXT: [[TMP19:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP3]] 1785; CHECK-NEXT: [[TMP20:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP4]] 1786; CHECK-NEXT: [[TMP21:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP5]] 1787; CHECK-NEXT: [[TMP22:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP6]] 1788; CHECK-NEXT: [[TMP23:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP7]] 1789; CHECK-NEXT: [[TMP24:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP8]] 1790; CHECK-NEXT: [[TMP25:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP9]] 1791; CHECK-NEXT: [[TMP26:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP10]] 1792; CHECK-NEXT: [[TMP27:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP11]] 1793; CHECK-NEXT: [[TMP28:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP12]] 1794; CHECK-NEXT: [[TMP29:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP13]] 1795; CHECK-NEXT: [[TMP30:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP14]] 1796; CHECK-NEXT: [[TMP31:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP15]] 1797; CHECK-NEXT: [[TMP32:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP16]] 1798; CHECK-NEXT: [[TMP33:%.*]] = load i1, ptr [[TMP17]], align 1 1799; CHECK-NEXT: [[TMP34:%.*]] = load i1, ptr [[TMP18]], align 1 1800; CHECK-NEXT: [[TMP35:%.*]] = load i1, ptr [[TMP19]], align 1 1801; CHECK-NEXT: [[TMP36:%.*]] = load i1, ptr [[TMP20]], align 1 1802; CHECK-NEXT: [[TMP37:%.*]] = insertelement <4 x i1> poison, i1 [[TMP33]], i32 0 1803; CHECK-NEXT: [[TMP38:%.*]] = insertelement <4 x i1> [[TMP37]], i1 [[TMP34]], i32 1 1804; CHECK-NEXT: [[TMP39:%.*]] = insertelement <4 x i1> [[TMP38]], i1 [[TMP35]], i32 2 1805; CHECK-NEXT: [[TMP40:%.*]] = insertelement <4 x i1> [[TMP39]], i1 [[TMP36]], i32 3 1806; CHECK-NEXT: [[TMP41:%.*]] = load i1, ptr [[TMP21]], align 1 1807; CHECK-NEXT: [[TMP42:%.*]] = load i1, ptr [[TMP22]], align 1 1808; CHECK-NEXT: [[TMP43:%.*]] = load i1, ptr [[TMP23]], align 1 1809; CHECK-NEXT: [[TMP44:%.*]] = load i1, ptr [[TMP24]], align 1 1810; CHECK-NEXT: [[TMP45:%.*]] = insertelement <4 x i1> poison, i1 [[TMP41]], i32 0 1811; CHECK-NEXT: [[TMP46:%.*]] = insertelement <4 x i1> [[TMP45]], i1 [[TMP42]], i32 1 1812; CHECK-NEXT: [[TMP47:%.*]] = insertelement <4 x i1> [[TMP46]], i1 [[TMP43]], i32 2 1813; CHECK-NEXT: [[TMP48:%.*]] = insertelement <4 x i1> [[TMP47]], i1 [[TMP44]], i32 3 1814; CHECK-NEXT: [[TMP49:%.*]] = load i1, ptr [[TMP25]], align 1 1815; CHECK-NEXT: [[TMP50:%.*]] = load i1, ptr [[TMP26]], align 1 1816; CHECK-NEXT: [[TMP51:%.*]] = load i1, ptr [[TMP27]], align 1 1817; CHECK-NEXT: [[TMP52:%.*]] = load i1, ptr [[TMP28]], align 1 1818; CHECK-NEXT: [[TMP53:%.*]] = insertelement <4 x i1> poison, i1 [[TMP49]], i32 0 1819; CHECK-NEXT: [[TMP54:%.*]] = insertelement <4 x i1> [[TMP53]], i1 [[TMP50]], i32 1 1820; CHECK-NEXT: [[TMP55:%.*]] = insertelement <4 x i1> [[TMP54]], i1 [[TMP51]], i32 2 1821; CHECK-NEXT: [[TMP56:%.*]] = insertelement <4 x i1> [[TMP55]], i1 [[TMP52]], i32 3 1822; CHECK-NEXT: [[TMP57:%.*]] = load i1, ptr [[TMP29]], align 1 1823; CHECK-NEXT: [[TMP58:%.*]] = load i1, ptr [[TMP30]], align 1 1824; CHECK-NEXT: [[TMP59:%.*]] = load i1, ptr [[TMP31]], align 1 1825; CHECK-NEXT: [[TMP60:%.*]] = load i1, ptr [[TMP32]], align 1 1826; CHECK-NEXT: [[TMP61:%.*]] = insertelement <4 x i1> poison, i1 [[TMP57]], i32 0 1827; CHECK-NEXT: [[TMP62:%.*]] = insertelement <4 x i1> [[TMP61]], i1 [[TMP58]], i32 1 1828; CHECK-NEXT: [[TMP63:%.*]] = insertelement <4 x i1> [[TMP62]], i1 [[TMP59]], i32 2 1829; CHECK-NEXT: [[TMP64:%.*]] = insertelement <4 x i1> [[TMP63]], i1 [[TMP60]], i32 3 1830; CHECK-NEXT: [[TMP65:%.*]] = getelementptr i32, ptr [[ALLOCA]], i64 [[TMP1]] 1831; CHECK-NEXT: [[TMP69:%.*]] = getelementptr i32, ptr [[TMP65]], i32 0 1832; CHECK-NEXT: [[TMP70:%.*]] = getelementptr i32, ptr [[TMP65]], i32 4 1833; CHECK-NEXT: [[TMP71:%.*]] = getelementptr i32, ptr [[TMP65]], i32 8 1834; CHECK-NEXT: [[TMP72:%.*]] = getelementptr i32, ptr [[TMP65]], i32 12 1835; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP69]], align 4 1836; CHECK-NEXT: [[WIDE_LOAD4:%.*]] = load <4 x i32>, ptr [[TMP70]], align 4 1837; CHECK-NEXT: [[WIDE_LOAD5:%.*]] = load <4 x i32>, ptr [[TMP71]], align 4 1838; CHECK-NEXT: [[WIDE_LOAD6:%.*]] = load <4 x i32>, ptr [[TMP72]], align 4 1839; CHECK-NEXT: [[PREDPHI:%.*]] = select <4 x i1> [[TMP40]], <4 x i32> [[WIDE_LOAD]], <4 x i32> zeroinitializer 1840; CHECK-NEXT: [[PREDPHI7:%.*]] = select <4 x i1> [[TMP48]], <4 x i32> [[WIDE_LOAD4]], <4 x i32> zeroinitializer 1841; CHECK-NEXT: [[PREDPHI8:%.*]] = select <4 x i1> [[TMP56]], <4 x i32> [[WIDE_LOAD5]], <4 x i32> zeroinitializer 1842; CHECK-NEXT: [[PREDPHI9:%.*]] = select <4 x i1> [[TMP64]], <4 x i32> [[WIDE_LOAD6]], <4 x i32> zeroinitializer 1843; CHECK-NEXT: [[TMP73]] = add <4 x i32> [[VEC_PHI]], [[PREDPHI]] 1844; CHECK-NEXT: [[TMP74]] = add <4 x i32> [[VEC_PHI1]], [[PREDPHI7]] 1845; CHECK-NEXT: [[TMP75]] = add <4 x i32> [[VEC_PHI2]], [[PREDPHI8]] 1846; CHECK-NEXT: [[TMP76]] = add <4 x i32> [[VEC_PHI3]], [[PREDPHI9]] 1847; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16 1848; CHECK-NEXT: [[TMP77:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] 1849; CHECK-NEXT: br i1 [[TMP77]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP22:![0-9]+]] 1850; CHECK: middle.block: 1851; CHECK-NEXT: [[BIN_RDX:%.*]] = add <4 x i32> [[TMP74]], [[TMP73]] 1852; CHECK-NEXT: [[BIN_RDX10:%.*]] = add <4 x i32> [[TMP75]], [[BIN_RDX]] 1853; CHECK-NEXT: [[BIN_RDX11:%.*]] = add <4 x i32> [[TMP76]], [[BIN_RDX10]] 1854; CHECK-NEXT: [[TMP78:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[BIN_RDX11]]) 1855; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP0]], [[N_VEC]] 1856; CHECK-NEXT: br i1 [[CMP_N]], label [[LOOP_EXIT:%.*]], label [[SCALAR_PH]] 1857; CHECK: scalar.ph: 1858; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ] 1859; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP78]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY]] ] 1860; CHECK-NEXT: br label [[LOOP:%.*]] 1861; CHECK: loop: 1862; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LATCH:%.*]] ] 1863; CHECK-NEXT: [[ACCUM:%.*]] = phi i32 [ [[BC_MERGE_RDX]], [[SCALAR_PH]] ], [ [[ACCUM_NEXT:%.*]], [[LATCH]] ] 1864; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1 1865; CHECK-NEXT: [[TEST_ADDR:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[IV]] 1866; CHECK-NEXT: [[EARLYCND:%.*]] = load i1, ptr [[TEST_ADDR]], align 1 1867; CHECK-NEXT: br i1 [[EARLYCND]], label [[PRED:%.*]], label [[LATCH]] 1868; CHECK: pred: 1869; CHECK-NEXT: [[ADDR:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[IV]] 1870; CHECK-NEXT: [[VAL:%.*]] = load i32, ptr [[ADDR]], align 4 1871; CHECK-NEXT: br label [[LATCH]] 1872; CHECK: latch: 1873; CHECK-NEXT: [[VAL_PHI:%.*]] = phi i32 [ 0, [[LOOP]] ], [ [[VAL]], [[PRED]] ] 1874; CHECK-NEXT: [[ACCUM_NEXT]] = add i32 [[ACCUM]], [[VAL_PHI]] 1875; CHECK-NEXT: [[EXIT:%.*]] = icmp ugt i64 [[IV]], [[MIN]] 1876; CHECK-NEXT: br i1 [[EXIT]], label [[LOOP_EXIT]], label [[LOOP]], !llvm.loop [[LOOP23:![0-9]+]] 1877; CHECK: loop_exit: 1878; CHECK-NEXT: [[ACCUM_NEXT_LCSSA:%.*]] = phi i32 [ [[ACCUM_NEXT]], [[LATCH]] ], [ [[TMP78]], [[MIDDLE_BLOCK]] ] 1879; CHECK-NEXT: ret i32 [[ACCUM_NEXT_LCSSA]] 1880; 1881entry: 1882 %alloca = alloca [4096 x i32] 1883 call void @init(ptr %alloca) 1884 %cmp = icmp ugt i64 %len, 4094 1885 %min = select i1 %cmp, i64 4094, i64 %len 1886 br label %loop 1887loop: 1888 %iv = phi i64 [ 0, %entry ], [ %iv.next, %latch ] 1889 %accum = phi i32 [ 0, %entry ], [ %accum.next, %latch ] 1890 %iv.next = add i64 %iv, 1 1891 %test_addr = getelementptr inbounds i1, ptr %test_base, i64 %iv 1892 %earlycnd = load i1, ptr %test_addr 1893 br i1 %earlycnd, label %pred, label %latch 1894pred: 1895 %addr = getelementptr inbounds i32, ptr %alloca, i64 %iv 1896 %val = load i32, ptr %addr 1897 br label %latch 1898latch: 1899 %val.phi = phi i32 [0, %loop], [%val, %pred] 1900 %accum.next = add i32 %accum, %val.phi 1901 %exit = icmp ugt i64 %iv, %min 1902 br i1 %exit, label %loop_exit, label %loop 1903 1904loop_exit: 1905 ret i32 %accum.next 1906} 1907 1908 1909;; Model a custom allocate which allocates in chunks of 8 bytes 1910declare align 8 dereferenceable_or_null(8) ptr @my_alloc(i32) allocsize(0) 1911declare align 8 dereferenceable_or_null(8) ptr @my_array_alloc(i32, i32) allocsize(0, 1) 1912 1913define i32 @test_allocsize(i64 %len, ptr %test_base) nofree nosync { 1914; CHECK-LABEL: @test_allocsize( 1915; CHECK-NEXT: entry: 1916; CHECK-NEXT: [[ALLOCATION:%.*]] = call nonnull ptr @my_alloc(i32 16384) 1917; CHECK-NEXT: call void @init(ptr [[ALLOCATION]]) 1918; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] 1919; CHECK: vector.ph: 1920; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] 1921; CHECK: vector.body: 1922; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] 1923; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP72:%.*]], [[VECTOR_BODY]] ] 1924; CHECK-NEXT: [[VEC_PHI1:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP73:%.*]], [[VECTOR_BODY]] ] 1925; CHECK-NEXT: [[VEC_PHI2:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP74:%.*]], [[VECTOR_BODY]] ] 1926; CHECK-NEXT: [[VEC_PHI3:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP75:%.*]], [[VECTOR_BODY]] ] 1927; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 0 1928; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[INDEX]], 1 1929; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[INDEX]], 2 1930; CHECK-NEXT: [[TMP3:%.*]] = add i64 [[INDEX]], 3 1931; CHECK-NEXT: [[TMP4:%.*]] = add i64 [[INDEX]], 4 1932; CHECK-NEXT: [[TMP5:%.*]] = add i64 [[INDEX]], 5 1933; CHECK-NEXT: [[TMP6:%.*]] = add i64 [[INDEX]], 6 1934; CHECK-NEXT: [[TMP7:%.*]] = add i64 [[INDEX]], 7 1935; CHECK-NEXT: [[TMP8:%.*]] = add i64 [[INDEX]], 8 1936; CHECK-NEXT: [[TMP9:%.*]] = add i64 [[INDEX]], 9 1937; CHECK-NEXT: [[TMP10:%.*]] = add i64 [[INDEX]], 10 1938; CHECK-NEXT: [[TMP11:%.*]] = add i64 [[INDEX]], 11 1939; CHECK-NEXT: [[TMP12:%.*]] = add i64 [[INDEX]], 12 1940; CHECK-NEXT: [[TMP13:%.*]] = add i64 [[INDEX]], 13 1941; CHECK-NEXT: [[TMP14:%.*]] = add i64 [[INDEX]], 14 1942; CHECK-NEXT: [[TMP15:%.*]] = add i64 [[INDEX]], 15 1943; CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE:%.*]], i64 [[TMP0]] 1944; CHECK-NEXT: [[TMP17:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP1]] 1945; CHECK-NEXT: [[TMP18:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP2]] 1946; CHECK-NEXT: [[TMP19:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP3]] 1947; CHECK-NEXT: [[TMP20:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP4]] 1948; CHECK-NEXT: [[TMP21:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP5]] 1949; CHECK-NEXT: [[TMP22:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP6]] 1950; CHECK-NEXT: [[TMP23:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP7]] 1951; CHECK-NEXT: [[TMP24:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP8]] 1952; CHECK-NEXT: [[TMP25:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP9]] 1953; CHECK-NEXT: [[TMP26:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP10]] 1954; CHECK-NEXT: [[TMP27:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP11]] 1955; CHECK-NEXT: [[TMP28:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP12]] 1956; CHECK-NEXT: [[TMP29:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP13]] 1957; CHECK-NEXT: [[TMP30:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP14]] 1958; CHECK-NEXT: [[TMP31:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP15]] 1959; CHECK-NEXT: [[TMP32:%.*]] = load i1, ptr [[TMP16]], align 1 1960; CHECK-NEXT: [[TMP33:%.*]] = load i1, ptr [[TMP17]], align 1 1961; CHECK-NEXT: [[TMP34:%.*]] = load i1, ptr [[TMP18]], align 1 1962; CHECK-NEXT: [[TMP35:%.*]] = load i1, ptr [[TMP19]], align 1 1963; CHECK-NEXT: [[TMP36:%.*]] = insertelement <4 x i1> poison, i1 [[TMP32]], i32 0 1964; CHECK-NEXT: [[TMP37:%.*]] = insertelement <4 x i1> [[TMP36]], i1 [[TMP33]], i32 1 1965; CHECK-NEXT: [[TMP38:%.*]] = insertelement <4 x i1> [[TMP37]], i1 [[TMP34]], i32 2 1966; CHECK-NEXT: [[TMP39:%.*]] = insertelement <4 x i1> [[TMP38]], i1 [[TMP35]], i32 3 1967; CHECK-NEXT: [[TMP40:%.*]] = load i1, ptr [[TMP20]], align 1 1968; CHECK-NEXT: [[TMP41:%.*]] = load i1, ptr [[TMP21]], align 1 1969; CHECK-NEXT: [[TMP42:%.*]] = load i1, ptr [[TMP22]], align 1 1970; CHECK-NEXT: [[TMP43:%.*]] = load i1, ptr [[TMP23]], align 1 1971; CHECK-NEXT: [[TMP44:%.*]] = insertelement <4 x i1> poison, i1 [[TMP40]], i32 0 1972; CHECK-NEXT: [[TMP45:%.*]] = insertelement <4 x i1> [[TMP44]], i1 [[TMP41]], i32 1 1973; CHECK-NEXT: [[TMP46:%.*]] = insertelement <4 x i1> [[TMP45]], i1 [[TMP42]], i32 2 1974; CHECK-NEXT: [[TMP47:%.*]] = insertelement <4 x i1> [[TMP46]], i1 [[TMP43]], i32 3 1975; CHECK-NEXT: [[TMP48:%.*]] = load i1, ptr [[TMP24]], align 1 1976; CHECK-NEXT: [[TMP49:%.*]] = load i1, ptr [[TMP25]], align 1 1977; CHECK-NEXT: [[TMP50:%.*]] = load i1, ptr [[TMP26]], align 1 1978; CHECK-NEXT: [[TMP51:%.*]] = load i1, ptr [[TMP27]], align 1 1979; CHECK-NEXT: [[TMP52:%.*]] = insertelement <4 x i1> poison, i1 [[TMP48]], i32 0 1980; CHECK-NEXT: [[TMP53:%.*]] = insertelement <4 x i1> [[TMP52]], i1 [[TMP49]], i32 1 1981; CHECK-NEXT: [[TMP54:%.*]] = insertelement <4 x i1> [[TMP53]], i1 [[TMP50]], i32 2 1982; CHECK-NEXT: [[TMP55:%.*]] = insertelement <4 x i1> [[TMP54]], i1 [[TMP51]], i32 3 1983; CHECK-NEXT: [[TMP56:%.*]] = load i1, ptr [[TMP28]], align 1 1984; CHECK-NEXT: [[TMP57:%.*]] = load i1, ptr [[TMP29]], align 1 1985; CHECK-NEXT: [[TMP58:%.*]] = load i1, ptr [[TMP30]], align 1 1986; CHECK-NEXT: [[TMP59:%.*]] = load i1, ptr [[TMP31]], align 1 1987; CHECK-NEXT: [[TMP60:%.*]] = insertelement <4 x i1> poison, i1 [[TMP56]], i32 0 1988; CHECK-NEXT: [[TMP61:%.*]] = insertelement <4 x i1> [[TMP60]], i1 [[TMP57]], i32 1 1989; CHECK-NEXT: [[TMP62:%.*]] = insertelement <4 x i1> [[TMP61]], i1 [[TMP58]], i32 2 1990; CHECK-NEXT: [[TMP63:%.*]] = insertelement <4 x i1> [[TMP62]], i1 [[TMP59]], i32 3 1991; CHECK-NEXT: [[TMP64:%.*]] = getelementptr i32, ptr [[ALLOCATION]], i64 [[TMP0]] 1992; CHECK-NEXT: [[TMP68:%.*]] = getelementptr i32, ptr [[TMP64]], i32 0 1993; CHECK-NEXT: [[TMP69:%.*]] = getelementptr i32, ptr [[TMP64]], i32 4 1994; CHECK-NEXT: [[TMP70:%.*]] = getelementptr i32, ptr [[TMP64]], i32 8 1995; CHECK-NEXT: [[TMP71:%.*]] = getelementptr i32, ptr [[TMP64]], i32 12 1996; CHECK-NEXT: [[WIDE_MASKED_LOAD:%.*]] = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr [[TMP68]], i32 4, <4 x i1> [[TMP39]], <4 x i32> poison) 1997; CHECK-NEXT: [[WIDE_MASKED_LOAD4:%.*]] = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr [[TMP69]], i32 4, <4 x i1> [[TMP47]], <4 x i32> poison) 1998; CHECK-NEXT: [[WIDE_MASKED_LOAD5:%.*]] = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr [[TMP70]], i32 4, <4 x i1> [[TMP55]], <4 x i32> poison) 1999; CHECK-NEXT: [[WIDE_MASKED_LOAD6:%.*]] = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr [[TMP71]], i32 4, <4 x i1> [[TMP63]], <4 x i32> poison) 2000; CHECK-NEXT: [[PREDPHI:%.*]] = select <4 x i1> [[TMP39]], <4 x i32> [[WIDE_MASKED_LOAD]], <4 x i32> zeroinitializer 2001; CHECK-NEXT: [[PREDPHI7:%.*]] = select <4 x i1> [[TMP47]], <4 x i32> [[WIDE_MASKED_LOAD4]], <4 x i32> zeroinitializer 2002; CHECK-NEXT: [[PREDPHI8:%.*]] = select <4 x i1> [[TMP55]], <4 x i32> [[WIDE_MASKED_LOAD5]], <4 x i32> zeroinitializer 2003; CHECK-NEXT: [[PREDPHI9:%.*]] = select <4 x i1> [[TMP63]], <4 x i32> [[WIDE_MASKED_LOAD6]], <4 x i32> zeroinitializer 2004; CHECK-NEXT: [[TMP72]] = add <4 x i32> [[VEC_PHI]], [[PREDPHI]] 2005; CHECK-NEXT: [[TMP73]] = add <4 x i32> [[VEC_PHI1]], [[PREDPHI7]] 2006; CHECK-NEXT: [[TMP74]] = add <4 x i32> [[VEC_PHI2]], [[PREDPHI8]] 2007; CHECK-NEXT: [[TMP75]] = add <4 x i32> [[VEC_PHI3]], [[PREDPHI9]] 2008; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16 2009; CHECK-NEXT: [[TMP76:%.*]] = icmp eq i64 [[INDEX_NEXT]], 4096 2010; CHECK-NEXT: br i1 [[TMP76]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP24:![0-9]+]] 2011; CHECK: middle.block: 2012; CHECK-NEXT: [[BIN_RDX:%.*]] = add <4 x i32> [[TMP73]], [[TMP72]] 2013; CHECK-NEXT: [[BIN_RDX10:%.*]] = add <4 x i32> [[TMP74]], [[BIN_RDX]] 2014; CHECK-NEXT: [[BIN_RDX11:%.*]] = add <4 x i32> [[TMP75]], [[BIN_RDX10]] 2015; CHECK-NEXT: [[TMP77:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[BIN_RDX11]]) 2016; CHECK-NEXT: br i1 true, label [[LOOP_EXIT:%.*]], label [[SCALAR_PH]] 2017; CHECK: scalar.ph: 2018; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ 4096, [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ] 2019; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP77]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY]] ] 2020; CHECK-NEXT: br label [[LOOP:%.*]] 2021; CHECK: loop: 2022; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LATCH:%.*]] ] 2023; CHECK-NEXT: [[ACCUM:%.*]] = phi i32 [ [[BC_MERGE_RDX]], [[SCALAR_PH]] ], [ [[ACCUM_NEXT:%.*]], [[LATCH]] ] 2024; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1 2025; CHECK-NEXT: [[TEST_ADDR:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[IV]] 2026; CHECK-NEXT: [[EARLYCND:%.*]] = load i1, ptr [[TEST_ADDR]], align 1 2027; CHECK-NEXT: br i1 [[EARLYCND]], label [[PRED:%.*]], label [[LATCH]] 2028; CHECK: pred: 2029; CHECK-NEXT: [[ADDR:%.*]] = getelementptr inbounds i32, ptr [[ALLOCATION]], i64 [[IV]] 2030; CHECK-NEXT: [[VAL:%.*]] = load i32, ptr [[ADDR]], align 4 2031; CHECK-NEXT: br label [[LATCH]] 2032; CHECK: latch: 2033; CHECK-NEXT: [[VAL_PHI:%.*]] = phi i32 [ 0, [[LOOP]] ], [ [[VAL]], [[PRED]] ] 2034; CHECK-NEXT: [[ACCUM_NEXT]] = add i32 [[ACCUM]], [[VAL_PHI]] 2035; CHECK-NEXT: [[EXIT:%.*]] = icmp ugt i64 [[IV]], 4094 2036; CHECK-NEXT: br i1 [[EXIT]], label [[LOOP_EXIT]], label [[LOOP]], !llvm.loop [[LOOP25:![0-9]+]] 2037; CHECK: loop_exit: 2038; CHECK-NEXT: [[ACCUM_NEXT_LCSSA:%.*]] = phi i32 [ [[ACCUM_NEXT]], [[LATCH]] ], [ [[TMP77]], [[MIDDLE_BLOCK]] ] 2039; CHECK-NEXT: ret i32 [[ACCUM_NEXT_LCSSA]] 2040; 2041entry: 2042 %allocation = call nonnull ptr @my_alloc(i32 16384) 2043 call void @init(ptr %allocation) 2044 br label %loop 2045loop: 2046 %iv = phi i64 [ 0, %entry ], [ %iv.next, %latch ] 2047 %accum = phi i32 [ 0, %entry ], [ %accum.next, %latch ] 2048 %iv.next = add i64 %iv, 1 2049 %test_addr = getelementptr inbounds i1, ptr %test_base, i64 %iv 2050 %earlycnd = load i1, ptr %test_addr 2051 br i1 %earlycnd, label %pred, label %latch 2052pred: 2053 %addr = getelementptr inbounds i32, ptr %allocation, i64 %iv 2054 %val = load i32, ptr %addr 2055 br label %latch 2056latch: 2057 %val.phi = phi i32 [0, %loop], [%val, %pred] 2058 %accum.next = add i32 %accum, %val.phi 2059 %exit = icmp ugt i64 %iv, 4094 2060 br i1 %exit, label %loop_exit, label %loop 2061 2062loop_exit: 2063 ret i32 %accum.next 2064} 2065 2066 2067define i32 @test_allocsize_array(i64 %len, ptr %test_base) nofree nosync { 2068; CHECK-LABEL: @test_allocsize_array( 2069; CHECK-NEXT: entry: 2070; CHECK-NEXT: [[ALLOCATION:%.*]] = call nonnull ptr @my_array_alloc(i32 4096, i32 4) 2071; CHECK-NEXT: call void @init(ptr [[ALLOCATION]]) 2072; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] 2073; CHECK: vector.ph: 2074; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] 2075; CHECK: vector.body: 2076; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] 2077; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP72:%.*]], [[VECTOR_BODY]] ] 2078; CHECK-NEXT: [[VEC_PHI1:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP73:%.*]], [[VECTOR_BODY]] ] 2079; CHECK-NEXT: [[VEC_PHI2:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP74:%.*]], [[VECTOR_BODY]] ] 2080; CHECK-NEXT: [[VEC_PHI3:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP75:%.*]], [[VECTOR_BODY]] ] 2081; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 0 2082; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[INDEX]], 1 2083; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[INDEX]], 2 2084; CHECK-NEXT: [[TMP3:%.*]] = add i64 [[INDEX]], 3 2085; CHECK-NEXT: [[TMP4:%.*]] = add i64 [[INDEX]], 4 2086; CHECK-NEXT: [[TMP5:%.*]] = add i64 [[INDEX]], 5 2087; CHECK-NEXT: [[TMP6:%.*]] = add i64 [[INDEX]], 6 2088; CHECK-NEXT: [[TMP7:%.*]] = add i64 [[INDEX]], 7 2089; CHECK-NEXT: [[TMP8:%.*]] = add i64 [[INDEX]], 8 2090; CHECK-NEXT: [[TMP9:%.*]] = add i64 [[INDEX]], 9 2091; CHECK-NEXT: [[TMP10:%.*]] = add i64 [[INDEX]], 10 2092; CHECK-NEXT: [[TMP11:%.*]] = add i64 [[INDEX]], 11 2093; CHECK-NEXT: [[TMP12:%.*]] = add i64 [[INDEX]], 12 2094; CHECK-NEXT: [[TMP13:%.*]] = add i64 [[INDEX]], 13 2095; CHECK-NEXT: [[TMP14:%.*]] = add i64 [[INDEX]], 14 2096; CHECK-NEXT: [[TMP15:%.*]] = add i64 [[INDEX]], 15 2097; CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE:%.*]], i64 [[TMP0]] 2098; CHECK-NEXT: [[TMP17:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP1]] 2099; CHECK-NEXT: [[TMP18:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP2]] 2100; CHECK-NEXT: [[TMP19:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP3]] 2101; CHECK-NEXT: [[TMP20:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP4]] 2102; CHECK-NEXT: [[TMP21:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP5]] 2103; CHECK-NEXT: [[TMP22:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP6]] 2104; CHECK-NEXT: [[TMP23:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP7]] 2105; CHECK-NEXT: [[TMP24:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP8]] 2106; CHECK-NEXT: [[TMP25:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP9]] 2107; CHECK-NEXT: [[TMP26:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP10]] 2108; CHECK-NEXT: [[TMP27:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP11]] 2109; CHECK-NEXT: [[TMP28:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP12]] 2110; CHECK-NEXT: [[TMP29:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP13]] 2111; CHECK-NEXT: [[TMP30:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP14]] 2112; CHECK-NEXT: [[TMP31:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP15]] 2113; CHECK-NEXT: [[TMP32:%.*]] = load i1, ptr [[TMP16]], align 1 2114; CHECK-NEXT: [[TMP33:%.*]] = load i1, ptr [[TMP17]], align 1 2115; CHECK-NEXT: [[TMP34:%.*]] = load i1, ptr [[TMP18]], align 1 2116; CHECK-NEXT: [[TMP35:%.*]] = load i1, ptr [[TMP19]], align 1 2117; CHECK-NEXT: [[TMP36:%.*]] = insertelement <4 x i1> poison, i1 [[TMP32]], i32 0 2118; CHECK-NEXT: [[TMP37:%.*]] = insertelement <4 x i1> [[TMP36]], i1 [[TMP33]], i32 1 2119; CHECK-NEXT: [[TMP38:%.*]] = insertelement <4 x i1> [[TMP37]], i1 [[TMP34]], i32 2 2120; CHECK-NEXT: [[TMP39:%.*]] = insertelement <4 x i1> [[TMP38]], i1 [[TMP35]], i32 3 2121; CHECK-NEXT: [[TMP40:%.*]] = load i1, ptr [[TMP20]], align 1 2122; CHECK-NEXT: [[TMP41:%.*]] = load i1, ptr [[TMP21]], align 1 2123; CHECK-NEXT: [[TMP42:%.*]] = load i1, ptr [[TMP22]], align 1 2124; CHECK-NEXT: [[TMP43:%.*]] = load i1, ptr [[TMP23]], align 1 2125; CHECK-NEXT: [[TMP44:%.*]] = insertelement <4 x i1> poison, i1 [[TMP40]], i32 0 2126; CHECK-NEXT: [[TMP45:%.*]] = insertelement <4 x i1> [[TMP44]], i1 [[TMP41]], i32 1 2127; CHECK-NEXT: [[TMP46:%.*]] = insertelement <4 x i1> [[TMP45]], i1 [[TMP42]], i32 2 2128; CHECK-NEXT: [[TMP47:%.*]] = insertelement <4 x i1> [[TMP46]], i1 [[TMP43]], i32 3 2129; CHECK-NEXT: [[TMP48:%.*]] = load i1, ptr [[TMP24]], align 1 2130; CHECK-NEXT: [[TMP49:%.*]] = load i1, ptr [[TMP25]], align 1 2131; CHECK-NEXT: [[TMP50:%.*]] = load i1, ptr [[TMP26]], align 1 2132; CHECK-NEXT: [[TMP51:%.*]] = load i1, ptr [[TMP27]], align 1 2133; CHECK-NEXT: [[TMP52:%.*]] = insertelement <4 x i1> poison, i1 [[TMP48]], i32 0 2134; CHECK-NEXT: [[TMP53:%.*]] = insertelement <4 x i1> [[TMP52]], i1 [[TMP49]], i32 1 2135; CHECK-NEXT: [[TMP54:%.*]] = insertelement <4 x i1> [[TMP53]], i1 [[TMP50]], i32 2 2136; CHECK-NEXT: [[TMP55:%.*]] = insertelement <4 x i1> [[TMP54]], i1 [[TMP51]], i32 3 2137; CHECK-NEXT: [[TMP56:%.*]] = load i1, ptr [[TMP28]], align 1 2138; CHECK-NEXT: [[TMP57:%.*]] = load i1, ptr [[TMP29]], align 1 2139; CHECK-NEXT: [[TMP58:%.*]] = load i1, ptr [[TMP30]], align 1 2140; CHECK-NEXT: [[TMP59:%.*]] = load i1, ptr [[TMP31]], align 1 2141; CHECK-NEXT: [[TMP60:%.*]] = insertelement <4 x i1> poison, i1 [[TMP56]], i32 0 2142; CHECK-NEXT: [[TMP61:%.*]] = insertelement <4 x i1> [[TMP60]], i1 [[TMP57]], i32 1 2143; CHECK-NEXT: [[TMP62:%.*]] = insertelement <4 x i1> [[TMP61]], i1 [[TMP58]], i32 2 2144; CHECK-NEXT: [[TMP63:%.*]] = insertelement <4 x i1> [[TMP62]], i1 [[TMP59]], i32 3 2145; CHECK-NEXT: [[TMP64:%.*]] = getelementptr i32, ptr [[ALLOCATION]], i64 [[TMP0]] 2146; CHECK-NEXT: [[TMP68:%.*]] = getelementptr i32, ptr [[TMP64]], i32 0 2147; CHECK-NEXT: [[TMP69:%.*]] = getelementptr i32, ptr [[TMP64]], i32 4 2148; CHECK-NEXT: [[TMP70:%.*]] = getelementptr i32, ptr [[TMP64]], i32 8 2149; CHECK-NEXT: [[TMP71:%.*]] = getelementptr i32, ptr [[TMP64]], i32 12 2150; CHECK-NEXT: [[WIDE_MASKED_LOAD:%.*]] = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr [[TMP68]], i32 4, <4 x i1> [[TMP39]], <4 x i32> poison) 2151; CHECK-NEXT: [[WIDE_MASKED_LOAD4:%.*]] = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr [[TMP69]], i32 4, <4 x i1> [[TMP47]], <4 x i32> poison) 2152; CHECK-NEXT: [[WIDE_MASKED_LOAD5:%.*]] = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr [[TMP70]], i32 4, <4 x i1> [[TMP55]], <4 x i32> poison) 2153; CHECK-NEXT: [[WIDE_MASKED_LOAD6:%.*]] = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr [[TMP71]], i32 4, <4 x i1> [[TMP63]], <4 x i32> poison) 2154; CHECK-NEXT: [[PREDPHI:%.*]] = select <4 x i1> [[TMP39]], <4 x i32> [[WIDE_MASKED_LOAD]], <4 x i32> zeroinitializer 2155; CHECK-NEXT: [[PREDPHI7:%.*]] = select <4 x i1> [[TMP47]], <4 x i32> [[WIDE_MASKED_LOAD4]], <4 x i32> zeroinitializer 2156; CHECK-NEXT: [[PREDPHI8:%.*]] = select <4 x i1> [[TMP55]], <4 x i32> [[WIDE_MASKED_LOAD5]], <4 x i32> zeroinitializer 2157; CHECK-NEXT: [[PREDPHI9:%.*]] = select <4 x i1> [[TMP63]], <4 x i32> [[WIDE_MASKED_LOAD6]], <4 x i32> zeroinitializer 2158; CHECK-NEXT: [[TMP72]] = add <4 x i32> [[VEC_PHI]], [[PREDPHI]] 2159; CHECK-NEXT: [[TMP73]] = add <4 x i32> [[VEC_PHI1]], [[PREDPHI7]] 2160; CHECK-NEXT: [[TMP74]] = add <4 x i32> [[VEC_PHI2]], [[PREDPHI8]] 2161; CHECK-NEXT: [[TMP75]] = add <4 x i32> [[VEC_PHI3]], [[PREDPHI9]] 2162; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16 2163; CHECK-NEXT: [[TMP76:%.*]] = icmp eq i64 [[INDEX_NEXT]], 4096 2164; CHECK-NEXT: br i1 [[TMP76]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP26:![0-9]+]] 2165; CHECK: middle.block: 2166; CHECK-NEXT: [[BIN_RDX:%.*]] = add <4 x i32> [[TMP73]], [[TMP72]] 2167; CHECK-NEXT: [[BIN_RDX10:%.*]] = add <4 x i32> [[TMP74]], [[BIN_RDX]] 2168; CHECK-NEXT: [[BIN_RDX11:%.*]] = add <4 x i32> [[TMP75]], [[BIN_RDX10]] 2169; CHECK-NEXT: [[TMP77:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[BIN_RDX11]]) 2170; CHECK-NEXT: br i1 true, label [[LOOP_EXIT:%.*]], label [[SCALAR_PH]] 2171; CHECK: scalar.ph: 2172; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ 4096, [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ] 2173; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP77]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY]] ] 2174; CHECK-NEXT: br label [[LOOP:%.*]] 2175; CHECK: loop: 2176; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LATCH:%.*]] ] 2177; CHECK-NEXT: [[ACCUM:%.*]] = phi i32 [ [[BC_MERGE_RDX]], [[SCALAR_PH]] ], [ [[ACCUM_NEXT:%.*]], [[LATCH]] ] 2178; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1 2179; CHECK-NEXT: [[TEST_ADDR:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[IV]] 2180; CHECK-NEXT: [[EARLYCND:%.*]] = load i1, ptr [[TEST_ADDR]], align 1 2181; CHECK-NEXT: br i1 [[EARLYCND]], label [[PRED:%.*]], label [[LATCH]] 2182; CHECK: pred: 2183; CHECK-NEXT: [[ADDR:%.*]] = getelementptr inbounds i32, ptr [[ALLOCATION]], i64 [[IV]] 2184; CHECK-NEXT: [[VAL:%.*]] = load i32, ptr [[ADDR]], align 4 2185; CHECK-NEXT: br label [[LATCH]] 2186; CHECK: latch: 2187; CHECK-NEXT: [[VAL_PHI:%.*]] = phi i32 [ 0, [[LOOP]] ], [ [[VAL]], [[PRED]] ] 2188; CHECK-NEXT: [[ACCUM_NEXT]] = add i32 [[ACCUM]], [[VAL_PHI]] 2189; CHECK-NEXT: [[EXIT:%.*]] = icmp ugt i64 [[IV]], 4094 2190; CHECK-NEXT: br i1 [[EXIT]], label [[LOOP_EXIT]], label [[LOOP]], !llvm.loop [[LOOP27:![0-9]+]] 2191; CHECK: loop_exit: 2192; CHECK-NEXT: [[ACCUM_NEXT_LCSSA:%.*]] = phi i32 [ [[ACCUM_NEXT]], [[LATCH]] ], [ [[TMP77]], [[MIDDLE_BLOCK]] ] 2193; CHECK-NEXT: ret i32 [[ACCUM_NEXT_LCSSA]] 2194; 2195entry: 2196 %allocation = call nonnull ptr @my_array_alloc(i32 4096, i32 4) 2197 call void @init(ptr %allocation) 2198 br label %loop 2199loop: 2200 %iv = phi i64 [ 0, %entry ], [ %iv.next, %latch ] 2201 %accum = phi i32 [ 0, %entry ], [ %accum.next, %latch ] 2202 %iv.next = add i64 %iv, 1 2203 %test_addr = getelementptr inbounds i1, ptr %test_base, i64 %iv 2204 %earlycnd = load i1, ptr %test_addr 2205 br i1 %earlycnd, label %pred, label %latch 2206pred: 2207 %addr = getelementptr inbounds i32, ptr %allocation, i64 %iv 2208 %val = load i32, ptr %addr 2209 br label %latch 2210latch: 2211 %val.phi = phi i32 [0, %loop], [%val, %pred] 2212 %accum.next = add i32 %accum, %val.phi 2213 %exit = icmp ugt i64 %iv, 4094 2214 br i1 %exit, label %loop_exit, label %loop 2215 2216loop_exit: 2217 ret i32 %accum.next 2218} 2219 2220declare void @my_free(ptr) 2221 2222; For the point in time variant of deref(N) semantics, show a negative 2223; example where hoisting without explicit predication might introduce a 2224; dynamic use after free. (e.g. allzero is true when all elements of the 2225; test vector are false and thus base is never accessed.) 2226define i32 @test_allocsize_cond_deref(i1 %allzero, ptr %test_base) { 2227; CHECK-LABEL: @test_allocsize_cond_deref( 2228; CHECK-NEXT: entry: 2229; CHECK-NEXT: [[ALLOCATION:%.*]] = call nonnull ptr @my_alloc(i32 16384) 2230; CHECK-NEXT: call void @init(ptr [[ALLOCATION]]) 2231; CHECK-NEXT: br i1 [[ALLZERO:%.*]], label [[FREEIT:%.*]], label [[PREHEADER:%.*]] 2232; CHECK: freeit: 2233; CHECK-NEXT: call void @my_free(ptr [[ALLOCATION]]) 2234; CHECK-NEXT: br label [[PREHEADER]] 2235; CHECK: preheader: 2236; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] 2237; CHECK: vector.ph: 2238; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] 2239; CHECK: vector.body: 2240; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] 2241; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP72:%.*]], [[VECTOR_BODY]] ] 2242; CHECK-NEXT: [[VEC_PHI1:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP73:%.*]], [[VECTOR_BODY]] ] 2243; CHECK-NEXT: [[VEC_PHI2:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP74:%.*]], [[VECTOR_BODY]] ] 2244; CHECK-NEXT: [[VEC_PHI3:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP75:%.*]], [[VECTOR_BODY]] ] 2245; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 0 2246; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[INDEX]], 1 2247; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[INDEX]], 2 2248; CHECK-NEXT: [[TMP3:%.*]] = add i64 [[INDEX]], 3 2249; CHECK-NEXT: [[TMP4:%.*]] = add i64 [[INDEX]], 4 2250; CHECK-NEXT: [[TMP5:%.*]] = add i64 [[INDEX]], 5 2251; CHECK-NEXT: [[TMP6:%.*]] = add i64 [[INDEX]], 6 2252; CHECK-NEXT: [[TMP7:%.*]] = add i64 [[INDEX]], 7 2253; CHECK-NEXT: [[TMP8:%.*]] = add i64 [[INDEX]], 8 2254; CHECK-NEXT: [[TMP9:%.*]] = add i64 [[INDEX]], 9 2255; CHECK-NEXT: [[TMP10:%.*]] = add i64 [[INDEX]], 10 2256; CHECK-NEXT: [[TMP11:%.*]] = add i64 [[INDEX]], 11 2257; CHECK-NEXT: [[TMP12:%.*]] = add i64 [[INDEX]], 12 2258; CHECK-NEXT: [[TMP13:%.*]] = add i64 [[INDEX]], 13 2259; CHECK-NEXT: [[TMP14:%.*]] = add i64 [[INDEX]], 14 2260; CHECK-NEXT: [[TMP15:%.*]] = add i64 [[INDEX]], 15 2261; CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE:%.*]], i64 [[TMP0]] 2262; CHECK-NEXT: [[TMP17:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP1]] 2263; CHECK-NEXT: [[TMP18:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP2]] 2264; CHECK-NEXT: [[TMP19:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP3]] 2265; CHECK-NEXT: [[TMP20:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP4]] 2266; CHECK-NEXT: [[TMP21:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP5]] 2267; CHECK-NEXT: [[TMP22:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP6]] 2268; CHECK-NEXT: [[TMP23:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP7]] 2269; CHECK-NEXT: [[TMP24:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP8]] 2270; CHECK-NEXT: [[TMP25:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP9]] 2271; CHECK-NEXT: [[TMP26:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP10]] 2272; CHECK-NEXT: [[TMP27:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP11]] 2273; CHECK-NEXT: [[TMP28:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP12]] 2274; CHECK-NEXT: [[TMP29:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP13]] 2275; CHECK-NEXT: [[TMP30:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP14]] 2276; CHECK-NEXT: [[TMP31:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP15]] 2277; CHECK-NEXT: [[TMP32:%.*]] = load i1, ptr [[TMP16]], align 1 2278; CHECK-NEXT: [[TMP33:%.*]] = load i1, ptr [[TMP17]], align 1 2279; CHECK-NEXT: [[TMP34:%.*]] = load i1, ptr [[TMP18]], align 1 2280; CHECK-NEXT: [[TMP35:%.*]] = load i1, ptr [[TMP19]], align 1 2281; CHECK-NEXT: [[TMP36:%.*]] = insertelement <4 x i1> poison, i1 [[TMP32]], i32 0 2282; CHECK-NEXT: [[TMP37:%.*]] = insertelement <4 x i1> [[TMP36]], i1 [[TMP33]], i32 1 2283; CHECK-NEXT: [[TMP38:%.*]] = insertelement <4 x i1> [[TMP37]], i1 [[TMP34]], i32 2 2284; CHECK-NEXT: [[TMP39:%.*]] = insertelement <4 x i1> [[TMP38]], i1 [[TMP35]], i32 3 2285; CHECK-NEXT: [[TMP40:%.*]] = load i1, ptr [[TMP20]], align 1 2286; CHECK-NEXT: [[TMP41:%.*]] = load i1, ptr [[TMP21]], align 1 2287; CHECK-NEXT: [[TMP42:%.*]] = load i1, ptr [[TMP22]], align 1 2288; CHECK-NEXT: [[TMP43:%.*]] = load i1, ptr [[TMP23]], align 1 2289; CHECK-NEXT: [[TMP44:%.*]] = insertelement <4 x i1> poison, i1 [[TMP40]], i32 0 2290; CHECK-NEXT: [[TMP45:%.*]] = insertelement <4 x i1> [[TMP44]], i1 [[TMP41]], i32 1 2291; CHECK-NEXT: [[TMP46:%.*]] = insertelement <4 x i1> [[TMP45]], i1 [[TMP42]], i32 2 2292; CHECK-NEXT: [[TMP47:%.*]] = insertelement <4 x i1> [[TMP46]], i1 [[TMP43]], i32 3 2293; CHECK-NEXT: [[TMP48:%.*]] = load i1, ptr [[TMP24]], align 1 2294; CHECK-NEXT: [[TMP49:%.*]] = load i1, ptr [[TMP25]], align 1 2295; CHECK-NEXT: [[TMP50:%.*]] = load i1, ptr [[TMP26]], align 1 2296; CHECK-NEXT: [[TMP51:%.*]] = load i1, ptr [[TMP27]], align 1 2297; CHECK-NEXT: [[TMP52:%.*]] = insertelement <4 x i1> poison, i1 [[TMP48]], i32 0 2298; CHECK-NEXT: [[TMP53:%.*]] = insertelement <4 x i1> [[TMP52]], i1 [[TMP49]], i32 1 2299; CHECK-NEXT: [[TMP54:%.*]] = insertelement <4 x i1> [[TMP53]], i1 [[TMP50]], i32 2 2300; CHECK-NEXT: [[TMP55:%.*]] = insertelement <4 x i1> [[TMP54]], i1 [[TMP51]], i32 3 2301; CHECK-NEXT: [[TMP56:%.*]] = load i1, ptr [[TMP28]], align 1 2302; CHECK-NEXT: [[TMP57:%.*]] = load i1, ptr [[TMP29]], align 1 2303; CHECK-NEXT: [[TMP58:%.*]] = load i1, ptr [[TMP30]], align 1 2304; CHECK-NEXT: [[TMP59:%.*]] = load i1, ptr [[TMP31]], align 1 2305; CHECK-NEXT: [[TMP60:%.*]] = insertelement <4 x i1> poison, i1 [[TMP56]], i32 0 2306; CHECK-NEXT: [[TMP61:%.*]] = insertelement <4 x i1> [[TMP60]], i1 [[TMP57]], i32 1 2307; CHECK-NEXT: [[TMP62:%.*]] = insertelement <4 x i1> [[TMP61]], i1 [[TMP58]], i32 2 2308; CHECK-NEXT: [[TMP63:%.*]] = insertelement <4 x i1> [[TMP62]], i1 [[TMP59]], i32 3 2309; CHECK-NEXT: [[TMP64:%.*]] = getelementptr i32, ptr [[ALLOCATION]], i64 [[TMP0]] 2310; CHECK-NEXT: [[TMP68:%.*]] = getelementptr i32, ptr [[TMP64]], i32 0 2311; CHECK-NEXT: [[TMP69:%.*]] = getelementptr i32, ptr [[TMP64]], i32 4 2312; CHECK-NEXT: [[TMP70:%.*]] = getelementptr i32, ptr [[TMP64]], i32 8 2313; CHECK-NEXT: [[TMP71:%.*]] = getelementptr i32, ptr [[TMP64]], i32 12 2314; CHECK-NEXT: [[WIDE_MASKED_LOAD:%.*]] = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr [[TMP68]], i32 4, <4 x i1> [[TMP39]], <4 x i32> poison) 2315; CHECK-NEXT: [[WIDE_MASKED_LOAD4:%.*]] = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr [[TMP69]], i32 4, <4 x i1> [[TMP47]], <4 x i32> poison) 2316; CHECK-NEXT: [[WIDE_MASKED_LOAD5:%.*]] = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr [[TMP70]], i32 4, <4 x i1> [[TMP55]], <4 x i32> poison) 2317; CHECK-NEXT: [[WIDE_MASKED_LOAD6:%.*]] = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr [[TMP71]], i32 4, <4 x i1> [[TMP63]], <4 x i32> poison) 2318; CHECK-NEXT: [[PREDPHI:%.*]] = select <4 x i1> [[TMP39]], <4 x i32> [[WIDE_MASKED_LOAD]], <4 x i32> zeroinitializer 2319; CHECK-NEXT: [[PREDPHI7:%.*]] = select <4 x i1> [[TMP47]], <4 x i32> [[WIDE_MASKED_LOAD4]], <4 x i32> zeroinitializer 2320; CHECK-NEXT: [[PREDPHI8:%.*]] = select <4 x i1> [[TMP55]], <4 x i32> [[WIDE_MASKED_LOAD5]], <4 x i32> zeroinitializer 2321; CHECK-NEXT: [[PREDPHI9:%.*]] = select <4 x i1> [[TMP63]], <4 x i32> [[WIDE_MASKED_LOAD6]], <4 x i32> zeroinitializer 2322; CHECK-NEXT: [[TMP72]] = add <4 x i32> [[VEC_PHI]], [[PREDPHI]] 2323; CHECK-NEXT: [[TMP73]] = add <4 x i32> [[VEC_PHI1]], [[PREDPHI7]] 2324; CHECK-NEXT: [[TMP74]] = add <4 x i32> [[VEC_PHI2]], [[PREDPHI8]] 2325; CHECK-NEXT: [[TMP75]] = add <4 x i32> [[VEC_PHI3]], [[PREDPHI9]] 2326; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16 2327; CHECK-NEXT: [[TMP76:%.*]] = icmp eq i64 [[INDEX_NEXT]], 4096 2328; CHECK-NEXT: br i1 [[TMP76]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP28:![0-9]+]] 2329; CHECK: middle.block: 2330; CHECK-NEXT: [[BIN_RDX:%.*]] = add <4 x i32> [[TMP73]], [[TMP72]] 2331; CHECK-NEXT: [[BIN_RDX10:%.*]] = add <4 x i32> [[TMP74]], [[BIN_RDX]] 2332; CHECK-NEXT: [[BIN_RDX11:%.*]] = add <4 x i32> [[TMP75]], [[BIN_RDX10]] 2333; CHECK-NEXT: [[TMP77:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[BIN_RDX11]]) 2334; CHECK-NEXT: br i1 true, label [[LOOP_EXIT:%.*]], label [[SCALAR_PH]] 2335; CHECK: scalar.ph: 2336; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ 4096, [[MIDDLE_BLOCK]] ], [ 0, [[PREHEADER]] ] 2337; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP77]], [[MIDDLE_BLOCK]] ], [ 0, [[PREHEADER]] ] 2338; CHECK-NEXT: br label [[LOOP:%.*]] 2339; CHECK: loop: 2340; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LATCH:%.*]] ] 2341; CHECK-NEXT: [[ACCUM:%.*]] = phi i32 [ [[BC_MERGE_RDX]], [[SCALAR_PH]] ], [ [[ACCUM_NEXT:%.*]], [[LATCH]] ] 2342; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1 2343; CHECK-NEXT: [[TEST_ADDR:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[IV]] 2344; CHECK-NEXT: [[EARLYCND:%.*]] = load i1, ptr [[TEST_ADDR]], align 1 2345; CHECK-NEXT: br i1 [[EARLYCND]], label [[PRED:%.*]], label [[LATCH]] 2346; CHECK: pred: 2347; CHECK-NEXT: [[ADDR:%.*]] = getelementptr inbounds i32, ptr [[ALLOCATION]], i64 [[IV]] 2348; CHECK-NEXT: [[VAL:%.*]] = load i32, ptr [[ADDR]], align 4 2349; CHECK-NEXT: br label [[LATCH]] 2350; CHECK: latch: 2351; CHECK-NEXT: [[VAL_PHI:%.*]] = phi i32 [ 0, [[LOOP]] ], [ [[VAL]], [[PRED]] ] 2352; CHECK-NEXT: [[ACCUM_NEXT]] = add i32 [[ACCUM]], [[VAL_PHI]] 2353; CHECK-NEXT: [[EXIT:%.*]] = icmp ugt i64 [[IV]], 4094 2354; CHECK-NEXT: br i1 [[EXIT]], label [[LOOP_EXIT]], label [[LOOP]], !llvm.loop [[LOOP29:![0-9]+]] 2355; CHECK: loop_exit: 2356; CHECK-NEXT: [[ACCUM_NEXT_LCSSA:%.*]] = phi i32 [ [[ACCUM_NEXT]], [[LATCH]] ], [ [[TMP77]], [[MIDDLE_BLOCK]] ] 2357; CHECK-NEXT: ret i32 [[ACCUM_NEXT_LCSSA]] 2358; 2359entry: 2360 %allocation = call nonnull ptr @my_alloc(i32 16384) 2361 call void @init(ptr %allocation) 2362 br i1 %allzero, label %freeit, label %preheader 2363freeit: 2364 call void @my_free(ptr %allocation) 2365 br label %preheader 2366preheader: 2367 br label %loop 2368loop: 2369 %iv = phi i64 [ 0, %preheader ], [ %iv.next, %latch ] 2370 %accum = phi i32 [ 0, %preheader ], [ %accum.next, %latch ] 2371 %iv.next = add i64 %iv, 1 2372 %test_addr = getelementptr inbounds i1, ptr %test_base, i64 %iv 2373 %earlycnd = load i1, ptr %test_addr 2374 br i1 %earlycnd, label %pred, label %latch 2375pred: 2376 %addr = getelementptr inbounds i32, ptr %allocation, i64 %iv 2377 %val = load i32, ptr %addr 2378 br label %latch 2379latch: 2380 %val.phi = phi i32 [0, %loop], [%val, %pred] 2381 %accum.next = add i32 %accum, %val.phi 2382 %exit = icmp ugt i64 %iv, 4094 2383 br i1 %exit, label %loop_exit, label %loop 2384 2385loop_exit: 2386 ret i32 %accum.next 2387} 2388 2389 2390; All non-unit stride test cases below. 2391; These will be masked gathers with AVX-512 support. 2392define i32 @test_stride_three(i64 %len, ptr %test_base) { 2393; CHECK-LABEL: @test_stride_three( 2394; CHECK-NEXT: entry: 2395; CHECK-NEXT: [[ALLOCA:%.*]] = alloca [105 x i32], align 4 2396; CHECK-NEXT: call void @init(ptr [[ALLOCA]]) 2397; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] 2398; CHECK: vector.ph: 2399; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] 2400; CHECK: vector.body: 2401; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] 2402; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP112:%.*]], [[VECTOR_BODY]] ] 2403; CHECK-NEXT: [[VEC_PHI1:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP113:%.*]], [[VECTOR_BODY]] ] 2404; CHECK-NEXT: [[VEC_PHI2:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP114:%.*]], [[VECTOR_BODY]] ] 2405; CHECK-NEXT: [[VEC_PHI3:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP115:%.*]], [[VECTOR_BODY]] ] 2406; CHECK-NEXT: [[OFFSET_IDX:%.*]] = mul i64 [[INDEX]], 3 2407; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[OFFSET_IDX]], 0 2408; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[OFFSET_IDX]], 3 2409; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[OFFSET_IDX]], 6 2410; CHECK-NEXT: [[TMP3:%.*]] = add i64 [[OFFSET_IDX]], 9 2411; CHECK-NEXT: [[TMP4:%.*]] = add i64 [[OFFSET_IDX]], 12 2412; CHECK-NEXT: [[TMP5:%.*]] = add i64 [[OFFSET_IDX]], 15 2413; CHECK-NEXT: [[TMP6:%.*]] = add i64 [[OFFSET_IDX]], 18 2414; CHECK-NEXT: [[TMP7:%.*]] = add i64 [[OFFSET_IDX]], 21 2415; CHECK-NEXT: [[TMP8:%.*]] = add i64 [[OFFSET_IDX]], 24 2416; CHECK-NEXT: [[TMP9:%.*]] = add i64 [[OFFSET_IDX]], 27 2417; CHECK-NEXT: [[TMP10:%.*]] = add i64 [[OFFSET_IDX]], 30 2418; CHECK-NEXT: [[TMP11:%.*]] = add i64 [[OFFSET_IDX]], 33 2419; CHECK-NEXT: [[TMP12:%.*]] = add i64 [[OFFSET_IDX]], 36 2420; CHECK-NEXT: [[TMP13:%.*]] = add i64 [[OFFSET_IDX]], 39 2421; CHECK-NEXT: [[TMP14:%.*]] = add i64 [[OFFSET_IDX]], 42 2422; CHECK-NEXT: [[TMP15:%.*]] = add i64 [[OFFSET_IDX]], 45 2423; CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE:%.*]], i64 [[TMP0]] 2424; CHECK-NEXT: [[TMP17:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP1]] 2425; CHECK-NEXT: [[TMP18:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP2]] 2426; CHECK-NEXT: [[TMP19:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP3]] 2427; CHECK-NEXT: [[TMP20:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP4]] 2428; CHECK-NEXT: [[TMP21:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP5]] 2429; CHECK-NEXT: [[TMP22:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP6]] 2430; CHECK-NEXT: [[TMP23:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP7]] 2431; CHECK-NEXT: [[TMP24:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP8]] 2432; CHECK-NEXT: [[TMP25:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP9]] 2433; CHECK-NEXT: [[TMP26:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP10]] 2434; CHECK-NEXT: [[TMP27:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP11]] 2435; CHECK-NEXT: [[TMP28:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP12]] 2436; CHECK-NEXT: [[TMP29:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP13]] 2437; CHECK-NEXT: [[TMP30:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP14]] 2438; CHECK-NEXT: [[TMP31:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP15]] 2439; CHECK-NEXT: [[TMP32:%.*]] = load i1, ptr [[TMP16]], align 1 2440; CHECK-NEXT: [[TMP33:%.*]] = load i1, ptr [[TMP17]], align 1 2441; CHECK-NEXT: [[TMP34:%.*]] = load i1, ptr [[TMP18]], align 1 2442; CHECK-NEXT: [[TMP35:%.*]] = load i1, ptr [[TMP19]], align 1 2443; CHECK-NEXT: [[TMP36:%.*]] = insertelement <4 x i1> poison, i1 [[TMP32]], i32 0 2444; CHECK-NEXT: [[TMP37:%.*]] = insertelement <4 x i1> [[TMP36]], i1 [[TMP33]], i32 1 2445; CHECK-NEXT: [[TMP38:%.*]] = insertelement <4 x i1> [[TMP37]], i1 [[TMP34]], i32 2 2446; CHECK-NEXT: [[TMP39:%.*]] = insertelement <4 x i1> [[TMP38]], i1 [[TMP35]], i32 3 2447; CHECK-NEXT: [[TMP40:%.*]] = load i1, ptr [[TMP20]], align 1 2448; CHECK-NEXT: [[TMP41:%.*]] = load i1, ptr [[TMP21]], align 1 2449; CHECK-NEXT: [[TMP42:%.*]] = load i1, ptr [[TMP22]], align 1 2450; CHECK-NEXT: [[TMP43:%.*]] = load i1, ptr [[TMP23]], align 1 2451; CHECK-NEXT: [[TMP44:%.*]] = insertelement <4 x i1> poison, i1 [[TMP40]], i32 0 2452; CHECK-NEXT: [[TMP45:%.*]] = insertelement <4 x i1> [[TMP44]], i1 [[TMP41]], i32 1 2453; CHECK-NEXT: [[TMP46:%.*]] = insertelement <4 x i1> [[TMP45]], i1 [[TMP42]], i32 2 2454; CHECK-NEXT: [[TMP47:%.*]] = insertelement <4 x i1> [[TMP46]], i1 [[TMP43]], i32 3 2455; CHECK-NEXT: [[TMP48:%.*]] = load i1, ptr [[TMP24]], align 1 2456; CHECK-NEXT: [[TMP49:%.*]] = load i1, ptr [[TMP25]], align 1 2457; CHECK-NEXT: [[TMP50:%.*]] = load i1, ptr [[TMP26]], align 1 2458; CHECK-NEXT: [[TMP51:%.*]] = load i1, ptr [[TMP27]], align 1 2459; CHECK-NEXT: [[TMP52:%.*]] = insertelement <4 x i1> poison, i1 [[TMP48]], i32 0 2460; CHECK-NEXT: [[TMP53:%.*]] = insertelement <4 x i1> [[TMP52]], i1 [[TMP49]], i32 1 2461; CHECK-NEXT: [[TMP54:%.*]] = insertelement <4 x i1> [[TMP53]], i1 [[TMP50]], i32 2 2462; CHECK-NEXT: [[TMP55:%.*]] = insertelement <4 x i1> [[TMP54]], i1 [[TMP51]], i32 3 2463; CHECK-NEXT: [[TMP56:%.*]] = load i1, ptr [[TMP28]], align 1 2464; CHECK-NEXT: [[TMP57:%.*]] = load i1, ptr [[TMP29]], align 1 2465; CHECK-NEXT: [[TMP58:%.*]] = load i1, ptr [[TMP30]], align 1 2466; CHECK-NEXT: [[TMP59:%.*]] = load i1, ptr [[TMP31]], align 1 2467; CHECK-NEXT: [[TMP60:%.*]] = insertelement <4 x i1> poison, i1 [[TMP56]], i32 0 2468; CHECK-NEXT: [[TMP61:%.*]] = insertelement <4 x i1> [[TMP60]], i1 [[TMP57]], i32 1 2469; CHECK-NEXT: [[TMP62:%.*]] = insertelement <4 x i1> [[TMP61]], i1 [[TMP58]], i32 2 2470; CHECK-NEXT: [[TMP63:%.*]] = insertelement <4 x i1> [[TMP62]], i1 [[TMP59]], i32 3 2471; CHECK-NEXT: [[TMP64:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP0]] 2472; CHECK-NEXT: [[TMP65:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP1]] 2473; CHECK-NEXT: [[TMP66:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP2]] 2474; CHECK-NEXT: [[TMP67:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP3]] 2475; CHECK-NEXT: [[TMP68:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP4]] 2476; CHECK-NEXT: [[TMP69:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP5]] 2477; CHECK-NEXT: [[TMP70:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP6]] 2478; CHECK-NEXT: [[TMP71:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP7]] 2479; CHECK-NEXT: [[TMP72:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP8]] 2480; CHECK-NEXT: [[TMP73:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP9]] 2481; CHECK-NEXT: [[TMP74:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP10]] 2482; CHECK-NEXT: [[TMP75:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP11]] 2483; CHECK-NEXT: [[TMP76:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP12]] 2484; CHECK-NEXT: [[TMP77:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP13]] 2485; CHECK-NEXT: [[TMP78:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP14]] 2486; CHECK-NEXT: [[TMP79:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP15]] 2487; CHECK-NEXT: [[TMP80:%.*]] = load i32, ptr [[TMP64]], align 4 2488; CHECK-NEXT: [[TMP81:%.*]] = load i32, ptr [[TMP65]], align 4 2489; CHECK-NEXT: [[TMP82:%.*]] = load i32, ptr [[TMP66]], align 4 2490; CHECK-NEXT: [[TMP83:%.*]] = load i32, ptr [[TMP67]], align 4 2491; CHECK-NEXT: [[TMP84:%.*]] = insertelement <4 x i32> poison, i32 [[TMP80]], i32 0 2492; CHECK-NEXT: [[TMP85:%.*]] = insertelement <4 x i32> [[TMP84]], i32 [[TMP81]], i32 1 2493; CHECK-NEXT: [[TMP86:%.*]] = insertelement <4 x i32> [[TMP85]], i32 [[TMP82]], i32 2 2494; CHECK-NEXT: [[TMP87:%.*]] = insertelement <4 x i32> [[TMP86]], i32 [[TMP83]], i32 3 2495; CHECK-NEXT: [[TMP88:%.*]] = load i32, ptr [[TMP68]], align 4 2496; CHECK-NEXT: [[TMP89:%.*]] = load i32, ptr [[TMP69]], align 4 2497; CHECK-NEXT: [[TMP90:%.*]] = load i32, ptr [[TMP70]], align 4 2498; CHECK-NEXT: [[TMP91:%.*]] = load i32, ptr [[TMP71]], align 4 2499; CHECK-NEXT: [[TMP92:%.*]] = insertelement <4 x i32> poison, i32 [[TMP88]], i32 0 2500; CHECK-NEXT: [[TMP93:%.*]] = insertelement <4 x i32> [[TMP92]], i32 [[TMP89]], i32 1 2501; CHECK-NEXT: [[TMP94:%.*]] = insertelement <4 x i32> [[TMP93]], i32 [[TMP90]], i32 2 2502; CHECK-NEXT: [[TMP95:%.*]] = insertelement <4 x i32> [[TMP94]], i32 [[TMP91]], i32 3 2503; CHECK-NEXT: [[TMP96:%.*]] = load i32, ptr [[TMP72]], align 4 2504; CHECK-NEXT: [[TMP97:%.*]] = load i32, ptr [[TMP73]], align 4 2505; CHECK-NEXT: [[TMP98:%.*]] = load i32, ptr [[TMP74]], align 4 2506; CHECK-NEXT: [[TMP99:%.*]] = load i32, ptr [[TMP75]], align 4 2507; CHECK-NEXT: [[TMP100:%.*]] = insertelement <4 x i32> poison, i32 [[TMP96]], i32 0 2508; CHECK-NEXT: [[TMP101:%.*]] = insertelement <4 x i32> [[TMP100]], i32 [[TMP97]], i32 1 2509; CHECK-NEXT: [[TMP102:%.*]] = insertelement <4 x i32> [[TMP101]], i32 [[TMP98]], i32 2 2510; CHECK-NEXT: [[TMP103:%.*]] = insertelement <4 x i32> [[TMP102]], i32 [[TMP99]], i32 3 2511; CHECK-NEXT: [[TMP104:%.*]] = load i32, ptr [[TMP76]], align 4 2512; CHECK-NEXT: [[TMP105:%.*]] = load i32, ptr [[TMP77]], align 4 2513; CHECK-NEXT: [[TMP106:%.*]] = load i32, ptr [[TMP78]], align 4 2514; CHECK-NEXT: [[TMP107:%.*]] = load i32, ptr [[TMP79]], align 4 2515; CHECK-NEXT: [[TMP108:%.*]] = insertelement <4 x i32> poison, i32 [[TMP104]], i32 0 2516; CHECK-NEXT: [[TMP109:%.*]] = insertelement <4 x i32> [[TMP108]], i32 [[TMP105]], i32 1 2517; CHECK-NEXT: [[TMP110:%.*]] = insertelement <4 x i32> [[TMP109]], i32 [[TMP106]], i32 2 2518; CHECK-NEXT: [[TMP111:%.*]] = insertelement <4 x i32> [[TMP110]], i32 [[TMP107]], i32 3 2519; CHECK-NEXT: [[PREDPHI:%.*]] = select <4 x i1> [[TMP39]], <4 x i32> [[TMP87]], <4 x i32> zeroinitializer 2520; CHECK-NEXT: [[PREDPHI4:%.*]] = select <4 x i1> [[TMP47]], <4 x i32> [[TMP95]], <4 x i32> zeroinitializer 2521; CHECK-NEXT: [[PREDPHI5:%.*]] = select <4 x i1> [[TMP55]], <4 x i32> [[TMP103]], <4 x i32> zeroinitializer 2522; CHECK-NEXT: [[PREDPHI6:%.*]] = select <4 x i1> [[TMP63]], <4 x i32> [[TMP111]], <4 x i32> zeroinitializer 2523; CHECK-NEXT: [[TMP112]] = add <4 x i32> [[VEC_PHI]], [[PREDPHI]] 2524; CHECK-NEXT: [[TMP113]] = add <4 x i32> [[VEC_PHI1]], [[PREDPHI4]] 2525; CHECK-NEXT: [[TMP114]] = add <4 x i32> [[VEC_PHI2]], [[PREDPHI5]] 2526; CHECK-NEXT: [[TMP115]] = add <4 x i32> [[VEC_PHI3]], [[PREDPHI6]] 2527; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16 2528; CHECK-NEXT: [[TMP116:%.*]] = icmp eq i64 [[INDEX_NEXT]], 32 2529; CHECK-NEXT: br i1 [[TMP116]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP30:![0-9]+]] 2530; CHECK: middle.block: 2531; CHECK-NEXT: [[BIN_RDX:%.*]] = add <4 x i32> [[TMP113]], [[TMP112]] 2532; CHECK-NEXT: [[BIN_RDX7:%.*]] = add <4 x i32> [[TMP114]], [[BIN_RDX]] 2533; CHECK-NEXT: [[BIN_RDX8:%.*]] = add <4 x i32> [[TMP115]], [[BIN_RDX7]] 2534; CHECK-NEXT: [[TMP117:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[BIN_RDX8]]) 2535; CHECK-NEXT: br i1 false, label [[LOOP_EXIT:%.*]], label [[SCALAR_PH]] 2536; CHECK: scalar.ph: 2537; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ 96, [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ] 2538; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP117]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY]] ] 2539; CHECK-NEXT: br label [[LOOP:%.*]] 2540; CHECK: loop: 2541; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LATCH:%.*]] ] 2542; CHECK-NEXT: [[ACCUM:%.*]] = phi i32 [ [[BC_MERGE_RDX]], [[SCALAR_PH]] ], [ [[ACCUM_NEXT:%.*]], [[LATCH]] ] 2543; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 3 2544; CHECK-NEXT: [[TEST_ADDR:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[IV]] 2545; CHECK-NEXT: [[EARLYCND:%.*]] = load i1, ptr [[TEST_ADDR]], align 1 2546; CHECK-NEXT: br i1 [[EARLYCND]], label [[PRED:%.*]], label [[LATCH]] 2547; CHECK: pred: 2548; CHECK-NEXT: [[ADDR:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[IV]] 2549; CHECK-NEXT: [[VAL:%.*]] = load i32, ptr [[ADDR]], align 4 2550; CHECK-NEXT: br label [[LATCH]] 2551; CHECK: latch: 2552; CHECK-NEXT: [[VAL_PHI:%.*]] = phi i32 [ 0, [[LOOP]] ], [ [[VAL]], [[PRED]] ] 2553; CHECK-NEXT: [[ACCUM_NEXT]] = add i32 [[ACCUM]], [[VAL_PHI]] 2554; CHECK-NEXT: [[EXIT:%.*]] = icmp ugt i64 [[IV]], 100 2555; CHECK-NEXT: br i1 [[EXIT]], label [[LOOP_EXIT]], label [[LOOP]], !llvm.loop [[LOOP31:![0-9]+]] 2556; CHECK: loop_exit: 2557; CHECK-NEXT: [[ACCUM_NEXT_LCSSA:%.*]] = phi i32 [ [[ACCUM_NEXT]], [[LATCH]] ], [ [[TMP117]], [[MIDDLE_BLOCK]] ] 2558; CHECK-NEXT: ret i32 [[ACCUM_NEXT_LCSSA]] 2559; 2560entry: 2561 %alloca = alloca [105 x i32] 2562 call void @init(ptr %alloca) 2563 br label %loop 2564loop: 2565 %iv = phi i64 [ 0, %entry ], [ %iv.next, %latch ] 2566 %accum = phi i32 [ 0, %entry ], [ %accum.next, %latch ] 2567 %iv.next = add i64 %iv, 3 2568 %test_addr = getelementptr inbounds i1, ptr %test_base, i64 %iv 2569 %earlycnd = load i1, ptr %test_addr 2570 br i1 %earlycnd, label %pred, label %latch 2571pred: 2572 %addr = getelementptr inbounds i32, ptr %alloca, i64 %iv 2573 %val = load i32, ptr %addr 2574 br label %latch 2575latch: 2576 %val.phi = phi i32 [0, %loop], [%val, %pred] 2577 %accum.next = add i32 %accum, %val.phi 2578 %exit = icmp ugt i64 %iv, 100 2579 br i1 %exit, label %loop_exit, label %loop 2580 2581loop_exit: 2582 ret i32 %accum.next 2583} 2584 2585define i32 @test_non_unit_stride_four(i64 %len, ptr %test_base) { 2586; CHECK-LABEL: @test_non_unit_stride_four( 2587; CHECK-NEXT: entry: 2588; CHECK-NEXT: [[ALLOCA:%.*]] = alloca [108 x i32], align 4 2589; CHECK-NEXT: call void @init(ptr [[ALLOCA]]) 2590; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] 2591; CHECK: vector.ph: 2592; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] 2593; CHECK: vector.body: 2594; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] 2595; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP56:%.*]], [[VECTOR_BODY]] ] 2596; CHECK-NEXT: [[VEC_PHI1:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP57:%.*]], [[VECTOR_BODY]] ] 2597; CHECK-NEXT: [[OFFSET_IDX:%.*]] = mul i64 [[INDEX]], 4 2598; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[OFFSET_IDX]], 0 2599; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[OFFSET_IDX]], 4 2600; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[OFFSET_IDX]], 8 2601; CHECK-NEXT: [[TMP3:%.*]] = add i64 [[OFFSET_IDX]], 12 2602; CHECK-NEXT: [[TMP4:%.*]] = add i64 [[OFFSET_IDX]], 16 2603; CHECK-NEXT: [[TMP5:%.*]] = add i64 [[OFFSET_IDX]], 20 2604; CHECK-NEXT: [[TMP6:%.*]] = add i64 [[OFFSET_IDX]], 24 2605; CHECK-NEXT: [[TMP7:%.*]] = add i64 [[OFFSET_IDX]], 28 2606; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE:%.*]], i64 [[TMP0]] 2607; CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP1]] 2608; CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP2]] 2609; CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP3]] 2610; CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP4]] 2611; CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP5]] 2612; CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP6]] 2613; CHECK-NEXT: [[TMP15:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP7]] 2614; CHECK-NEXT: [[TMP16:%.*]] = load i1, ptr [[TMP8]], align 1 2615; CHECK-NEXT: [[TMP17:%.*]] = load i1, ptr [[TMP9]], align 1 2616; CHECK-NEXT: [[TMP18:%.*]] = load i1, ptr [[TMP10]], align 1 2617; CHECK-NEXT: [[TMP19:%.*]] = load i1, ptr [[TMP11]], align 1 2618; CHECK-NEXT: [[TMP20:%.*]] = insertelement <4 x i1> poison, i1 [[TMP16]], i32 0 2619; CHECK-NEXT: [[TMP21:%.*]] = insertelement <4 x i1> [[TMP20]], i1 [[TMP17]], i32 1 2620; CHECK-NEXT: [[TMP22:%.*]] = insertelement <4 x i1> [[TMP21]], i1 [[TMP18]], i32 2 2621; CHECK-NEXT: [[TMP23:%.*]] = insertelement <4 x i1> [[TMP22]], i1 [[TMP19]], i32 3 2622; CHECK-NEXT: [[TMP24:%.*]] = load i1, ptr [[TMP12]], align 1 2623; CHECK-NEXT: [[TMP25:%.*]] = load i1, ptr [[TMP13]], align 1 2624; CHECK-NEXT: [[TMP26:%.*]] = load i1, ptr [[TMP14]], align 1 2625; CHECK-NEXT: [[TMP27:%.*]] = load i1, ptr [[TMP15]], align 1 2626; CHECK-NEXT: [[TMP28:%.*]] = insertelement <4 x i1> poison, i1 [[TMP24]], i32 0 2627; CHECK-NEXT: [[TMP29:%.*]] = insertelement <4 x i1> [[TMP28]], i1 [[TMP25]], i32 1 2628; CHECK-NEXT: [[TMP30:%.*]] = insertelement <4 x i1> [[TMP29]], i1 [[TMP26]], i32 2 2629; CHECK-NEXT: [[TMP31:%.*]] = insertelement <4 x i1> [[TMP30]], i1 [[TMP27]], i32 3 2630; CHECK-NEXT: [[TMP32:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP0]] 2631; CHECK-NEXT: [[TMP33:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP1]] 2632; CHECK-NEXT: [[TMP34:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP2]] 2633; CHECK-NEXT: [[TMP35:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP3]] 2634; CHECK-NEXT: [[TMP36:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP4]] 2635; CHECK-NEXT: [[TMP37:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP5]] 2636; CHECK-NEXT: [[TMP38:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP6]] 2637; CHECK-NEXT: [[TMP39:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP7]] 2638; CHECK-NEXT: [[TMP40:%.*]] = load i32, ptr [[TMP32]], align 4 2639; CHECK-NEXT: [[TMP41:%.*]] = load i32, ptr [[TMP33]], align 4 2640; CHECK-NEXT: [[TMP42:%.*]] = load i32, ptr [[TMP34]], align 4 2641; CHECK-NEXT: [[TMP43:%.*]] = load i32, ptr [[TMP35]], align 4 2642; CHECK-NEXT: [[TMP44:%.*]] = insertelement <4 x i32> poison, i32 [[TMP40]], i32 0 2643; CHECK-NEXT: [[TMP45:%.*]] = insertelement <4 x i32> [[TMP44]], i32 [[TMP41]], i32 1 2644; CHECK-NEXT: [[TMP46:%.*]] = insertelement <4 x i32> [[TMP45]], i32 [[TMP42]], i32 2 2645; CHECK-NEXT: [[TMP47:%.*]] = insertelement <4 x i32> [[TMP46]], i32 [[TMP43]], i32 3 2646; CHECK-NEXT: [[TMP48:%.*]] = load i32, ptr [[TMP36]], align 4 2647; CHECK-NEXT: [[TMP49:%.*]] = load i32, ptr [[TMP37]], align 4 2648; CHECK-NEXT: [[TMP50:%.*]] = load i32, ptr [[TMP38]], align 4 2649; CHECK-NEXT: [[TMP51:%.*]] = load i32, ptr [[TMP39]], align 4 2650; CHECK-NEXT: [[TMP52:%.*]] = insertelement <4 x i32> poison, i32 [[TMP48]], i32 0 2651; CHECK-NEXT: [[TMP53:%.*]] = insertelement <4 x i32> [[TMP52]], i32 [[TMP49]], i32 1 2652; CHECK-NEXT: [[TMP54:%.*]] = insertelement <4 x i32> [[TMP53]], i32 [[TMP50]], i32 2 2653; CHECK-NEXT: [[TMP55:%.*]] = insertelement <4 x i32> [[TMP54]], i32 [[TMP51]], i32 3 2654; CHECK-NEXT: [[PREDPHI:%.*]] = select <4 x i1> [[TMP23]], <4 x i32> [[TMP47]], <4 x i32> zeroinitializer 2655; CHECK-NEXT: [[PREDPHI2:%.*]] = select <4 x i1> [[TMP31]], <4 x i32> [[TMP55]], <4 x i32> zeroinitializer 2656; CHECK-NEXT: [[TMP56]] = add <4 x i32> [[VEC_PHI]], [[PREDPHI]] 2657; CHECK-NEXT: [[TMP57]] = add <4 x i32> [[VEC_PHI1]], [[PREDPHI2]] 2658; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8 2659; CHECK-NEXT: [[TMP58:%.*]] = icmp eq i64 [[INDEX_NEXT]], 24 2660; CHECK-NEXT: br i1 [[TMP58]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP32:![0-9]+]] 2661; CHECK: middle.block: 2662; CHECK-NEXT: [[BIN_RDX:%.*]] = add <4 x i32> [[TMP57]], [[TMP56]] 2663; CHECK-NEXT: [[TMP59:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[BIN_RDX]]) 2664; CHECK-NEXT: br i1 false, label [[LOOP_EXIT:%.*]], label [[SCALAR_PH]] 2665; CHECK: scalar.ph: 2666; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ 96, [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ] 2667; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP59]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY]] ] 2668; CHECK-NEXT: br label [[LOOP:%.*]] 2669; CHECK: loop: 2670; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LATCH:%.*]] ] 2671; CHECK-NEXT: [[ACCUM:%.*]] = phi i32 [ [[BC_MERGE_RDX]], [[SCALAR_PH]] ], [ [[ACCUM_NEXT:%.*]], [[LATCH]] ] 2672; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 4 2673; CHECK-NEXT: [[TEST_ADDR:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[IV]] 2674; CHECK-NEXT: [[EARLYCND:%.*]] = load i1, ptr [[TEST_ADDR]], align 1 2675; CHECK-NEXT: br i1 [[EARLYCND]], label [[PRED:%.*]], label [[LATCH]] 2676; CHECK: pred: 2677; CHECK-NEXT: [[ADDR:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[IV]] 2678; CHECK-NEXT: [[VAL:%.*]] = load i32, ptr [[ADDR]], align 4 2679; CHECK-NEXT: br label [[LATCH]] 2680; CHECK: latch: 2681; CHECK-NEXT: [[VAL_PHI:%.*]] = phi i32 [ 0, [[LOOP]] ], [ [[VAL]], [[PRED]] ] 2682; CHECK-NEXT: [[ACCUM_NEXT]] = add i32 [[ACCUM]], [[VAL_PHI]] 2683; CHECK-NEXT: [[EXIT:%.*]] = icmp ugt i64 [[IV]], 100 2684; CHECK-NEXT: br i1 [[EXIT]], label [[LOOP_EXIT]], label [[LOOP]], !llvm.loop [[LOOP33:![0-9]+]] 2685; CHECK: loop_exit: 2686; CHECK-NEXT: [[ACCUM_NEXT_LCSSA:%.*]] = phi i32 [ [[ACCUM_NEXT]], [[LATCH]] ], [ [[TMP59]], [[MIDDLE_BLOCK]] ] 2687; CHECK-NEXT: ret i32 [[ACCUM_NEXT_LCSSA]] 2688; 2689entry: 2690 %alloca = alloca [108 x i32] 2691 call void @init(ptr %alloca) 2692 br label %loop 2693loop: 2694 %iv = phi i64 [ 0, %entry ], [ %iv.next, %latch ] 2695 %accum = phi i32 [ 0, %entry ], [ %accum.next, %latch ] 2696 %iv.next = add i64 %iv, 4 2697 %test_addr = getelementptr inbounds i1, ptr %test_base, i64 %iv 2698 %earlycnd = load i1, ptr %test_addr 2699 br i1 %earlycnd, label %pred, label %latch 2700pred: 2701 %addr = getelementptr inbounds i32, ptr %alloca, i64 %iv 2702 %val = load i32, ptr %addr 2703 br label %latch 2704latch: 2705 %val.phi = phi i32 [0, %loop], [%val, %pred] 2706 %accum.next = add i32 %accum, %val.phi 2707 %exit = icmp ugt i64 %iv, 100 2708 br i1 %exit, label %loop_exit, label %loop 2709 2710loop_exit: 2711 ret i32 %accum.next 2712} 2713 2714define i32 @test_non_unit_stride_five(i64 %len, ptr %test_base) { 2715; CHECK-LABEL: @test_non_unit_stride_five( 2716; CHECK-NEXT: entry: 2717; CHECK-NEXT: [[ALLOCA:%.*]] = alloca [110 x i32], align 4 2718; CHECK-NEXT: call void @init(ptr [[ALLOCA]]) 2719; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] 2720; CHECK: vector.ph: 2721; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] 2722; CHECK: vector.body: 2723; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] 2724; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP112:%.*]], [[VECTOR_BODY]] ] 2725; CHECK-NEXT: [[VEC_PHI1:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP113:%.*]], [[VECTOR_BODY]] ] 2726; CHECK-NEXT: [[VEC_PHI2:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP114:%.*]], [[VECTOR_BODY]] ] 2727; CHECK-NEXT: [[VEC_PHI3:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP115:%.*]], [[VECTOR_BODY]] ] 2728; CHECK-NEXT: [[OFFSET_IDX:%.*]] = mul i64 [[INDEX]], 5 2729; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[OFFSET_IDX]], 0 2730; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[OFFSET_IDX]], 5 2731; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[OFFSET_IDX]], 10 2732; CHECK-NEXT: [[TMP3:%.*]] = add i64 [[OFFSET_IDX]], 15 2733; CHECK-NEXT: [[TMP4:%.*]] = add i64 [[OFFSET_IDX]], 20 2734; CHECK-NEXT: [[TMP5:%.*]] = add i64 [[OFFSET_IDX]], 25 2735; CHECK-NEXT: [[TMP6:%.*]] = add i64 [[OFFSET_IDX]], 30 2736; CHECK-NEXT: [[TMP7:%.*]] = add i64 [[OFFSET_IDX]], 35 2737; CHECK-NEXT: [[TMP8:%.*]] = add i64 [[OFFSET_IDX]], 40 2738; CHECK-NEXT: [[TMP9:%.*]] = add i64 [[OFFSET_IDX]], 45 2739; CHECK-NEXT: [[TMP10:%.*]] = add i64 [[OFFSET_IDX]], 50 2740; CHECK-NEXT: [[TMP11:%.*]] = add i64 [[OFFSET_IDX]], 55 2741; CHECK-NEXT: [[TMP12:%.*]] = add i64 [[OFFSET_IDX]], 60 2742; CHECK-NEXT: [[TMP13:%.*]] = add i64 [[OFFSET_IDX]], 65 2743; CHECK-NEXT: [[TMP14:%.*]] = add i64 [[OFFSET_IDX]], 70 2744; CHECK-NEXT: [[TMP15:%.*]] = add i64 [[OFFSET_IDX]], 75 2745; CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE:%.*]], i64 [[TMP0]] 2746; CHECK-NEXT: [[TMP17:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP1]] 2747; CHECK-NEXT: [[TMP18:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP2]] 2748; CHECK-NEXT: [[TMP19:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP3]] 2749; CHECK-NEXT: [[TMP20:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP4]] 2750; CHECK-NEXT: [[TMP21:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP5]] 2751; CHECK-NEXT: [[TMP22:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP6]] 2752; CHECK-NEXT: [[TMP23:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP7]] 2753; CHECK-NEXT: [[TMP24:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP8]] 2754; CHECK-NEXT: [[TMP25:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP9]] 2755; CHECK-NEXT: [[TMP26:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP10]] 2756; CHECK-NEXT: [[TMP27:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP11]] 2757; CHECK-NEXT: [[TMP28:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP12]] 2758; CHECK-NEXT: [[TMP29:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP13]] 2759; CHECK-NEXT: [[TMP30:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP14]] 2760; CHECK-NEXT: [[TMP31:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP15]] 2761; CHECK-NEXT: [[TMP32:%.*]] = load i1, ptr [[TMP16]], align 1 2762; CHECK-NEXT: [[TMP33:%.*]] = load i1, ptr [[TMP17]], align 1 2763; CHECK-NEXT: [[TMP34:%.*]] = load i1, ptr [[TMP18]], align 1 2764; CHECK-NEXT: [[TMP35:%.*]] = load i1, ptr [[TMP19]], align 1 2765; CHECK-NEXT: [[TMP36:%.*]] = insertelement <4 x i1> poison, i1 [[TMP32]], i32 0 2766; CHECK-NEXT: [[TMP37:%.*]] = insertelement <4 x i1> [[TMP36]], i1 [[TMP33]], i32 1 2767; CHECK-NEXT: [[TMP38:%.*]] = insertelement <4 x i1> [[TMP37]], i1 [[TMP34]], i32 2 2768; CHECK-NEXT: [[TMP39:%.*]] = insertelement <4 x i1> [[TMP38]], i1 [[TMP35]], i32 3 2769; CHECK-NEXT: [[TMP40:%.*]] = load i1, ptr [[TMP20]], align 1 2770; CHECK-NEXT: [[TMP41:%.*]] = load i1, ptr [[TMP21]], align 1 2771; CHECK-NEXT: [[TMP42:%.*]] = load i1, ptr [[TMP22]], align 1 2772; CHECK-NEXT: [[TMP43:%.*]] = load i1, ptr [[TMP23]], align 1 2773; CHECK-NEXT: [[TMP44:%.*]] = insertelement <4 x i1> poison, i1 [[TMP40]], i32 0 2774; CHECK-NEXT: [[TMP45:%.*]] = insertelement <4 x i1> [[TMP44]], i1 [[TMP41]], i32 1 2775; CHECK-NEXT: [[TMP46:%.*]] = insertelement <4 x i1> [[TMP45]], i1 [[TMP42]], i32 2 2776; CHECK-NEXT: [[TMP47:%.*]] = insertelement <4 x i1> [[TMP46]], i1 [[TMP43]], i32 3 2777; CHECK-NEXT: [[TMP48:%.*]] = load i1, ptr [[TMP24]], align 1 2778; CHECK-NEXT: [[TMP49:%.*]] = load i1, ptr [[TMP25]], align 1 2779; CHECK-NEXT: [[TMP50:%.*]] = load i1, ptr [[TMP26]], align 1 2780; CHECK-NEXT: [[TMP51:%.*]] = load i1, ptr [[TMP27]], align 1 2781; CHECK-NEXT: [[TMP52:%.*]] = insertelement <4 x i1> poison, i1 [[TMP48]], i32 0 2782; CHECK-NEXT: [[TMP53:%.*]] = insertelement <4 x i1> [[TMP52]], i1 [[TMP49]], i32 1 2783; CHECK-NEXT: [[TMP54:%.*]] = insertelement <4 x i1> [[TMP53]], i1 [[TMP50]], i32 2 2784; CHECK-NEXT: [[TMP55:%.*]] = insertelement <4 x i1> [[TMP54]], i1 [[TMP51]], i32 3 2785; CHECK-NEXT: [[TMP56:%.*]] = load i1, ptr [[TMP28]], align 1 2786; CHECK-NEXT: [[TMP57:%.*]] = load i1, ptr [[TMP29]], align 1 2787; CHECK-NEXT: [[TMP58:%.*]] = load i1, ptr [[TMP30]], align 1 2788; CHECK-NEXT: [[TMP59:%.*]] = load i1, ptr [[TMP31]], align 1 2789; CHECK-NEXT: [[TMP60:%.*]] = insertelement <4 x i1> poison, i1 [[TMP56]], i32 0 2790; CHECK-NEXT: [[TMP61:%.*]] = insertelement <4 x i1> [[TMP60]], i1 [[TMP57]], i32 1 2791; CHECK-NEXT: [[TMP62:%.*]] = insertelement <4 x i1> [[TMP61]], i1 [[TMP58]], i32 2 2792; CHECK-NEXT: [[TMP63:%.*]] = insertelement <4 x i1> [[TMP62]], i1 [[TMP59]], i32 3 2793; CHECK-NEXT: [[TMP64:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP0]] 2794; CHECK-NEXT: [[TMP65:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP1]] 2795; CHECK-NEXT: [[TMP66:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP2]] 2796; CHECK-NEXT: [[TMP67:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP3]] 2797; CHECK-NEXT: [[TMP68:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP4]] 2798; CHECK-NEXT: [[TMP69:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP5]] 2799; CHECK-NEXT: [[TMP70:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP6]] 2800; CHECK-NEXT: [[TMP71:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP7]] 2801; CHECK-NEXT: [[TMP72:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP8]] 2802; CHECK-NEXT: [[TMP73:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP9]] 2803; CHECK-NEXT: [[TMP74:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP10]] 2804; CHECK-NEXT: [[TMP75:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP11]] 2805; CHECK-NEXT: [[TMP76:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP12]] 2806; CHECK-NEXT: [[TMP77:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP13]] 2807; CHECK-NEXT: [[TMP78:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP14]] 2808; CHECK-NEXT: [[TMP79:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP15]] 2809; CHECK-NEXT: [[TMP80:%.*]] = load i32, ptr [[TMP64]], align 4 2810; CHECK-NEXT: [[TMP81:%.*]] = load i32, ptr [[TMP65]], align 4 2811; CHECK-NEXT: [[TMP82:%.*]] = load i32, ptr [[TMP66]], align 4 2812; CHECK-NEXT: [[TMP83:%.*]] = load i32, ptr [[TMP67]], align 4 2813; CHECK-NEXT: [[TMP84:%.*]] = insertelement <4 x i32> poison, i32 [[TMP80]], i32 0 2814; CHECK-NEXT: [[TMP85:%.*]] = insertelement <4 x i32> [[TMP84]], i32 [[TMP81]], i32 1 2815; CHECK-NEXT: [[TMP86:%.*]] = insertelement <4 x i32> [[TMP85]], i32 [[TMP82]], i32 2 2816; CHECK-NEXT: [[TMP87:%.*]] = insertelement <4 x i32> [[TMP86]], i32 [[TMP83]], i32 3 2817; CHECK-NEXT: [[TMP88:%.*]] = load i32, ptr [[TMP68]], align 4 2818; CHECK-NEXT: [[TMP89:%.*]] = load i32, ptr [[TMP69]], align 4 2819; CHECK-NEXT: [[TMP90:%.*]] = load i32, ptr [[TMP70]], align 4 2820; CHECK-NEXT: [[TMP91:%.*]] = load i32, ptr [[TMP71]], align 4 2821; CHECK-NEXT: [[TMP92:%.*]] = insertelement <4 x i32> poison, i32 [[TMP88]], i32 0 2822; CHECK-NEXT: [[TMP93:%.*]] = insertelement <4 x i32> [[TMP92]], i32 [[TMP89]], i32 1 2823; CHECK-NEXT: [[TMP94:%.*]] = insertelement <4 x i32> [[TMP93]], i32 [[TMP90]], i32 2 2824; CHECK-NEXT: [[TMP95:%.*]] = insertelement <4 x i32> [[TMP94]], i32 [[TMP91]], i32 3 2825; CHECK-NEXT: [[TMP96:%.*]] = load i32, ptr [[TMP72]], align 4 2826; CHECK-NEXT: [[TMP97:%.*]] = load i32, ptr [[TMP73]], align 4 2827; CHECK-NEXT: [[TMP98:%.*]] = load i32, ptr [[TMP74]], align 4 2828; CHECK-NEXT: [[TMP99:%.*]] = load i32, ptr [[TMP75]], align 4 2829; CHECK-NEXT: [[TMP100:%.*]] = insertelement <4 x i32> poison, i32 [[TMP96]], i32 0 2830; CHECK-NEXT: [[TMP101:%.*]] = insertelement <4 x i32> [[TMP100]], i32 [[TMP97]], i32 1 2831; CHECK-NEXT: [[TMP102:%.*]] = insertelement <4 x i32> [[TMP101]], i32 [[TMP98]], i32 2 2832; CHECK-NEXT: [[TMP103:%.*]] = insertelement <4 x i32> [[TMP102]], i32 [[TMP99]], i32 3 2833; CHECK-NEXT: [[TMP104:%.*]] = load i32, ptr [[TMP76]], align 4 2834; CHECK-NEXT: [[TMP105:%.*]] = load i32, ptr [[TMP77]], align 4 2835; CHECK-NEXT: [[TMP106:%.*]] = load i32, ptr [[TMP78]], align 4 2836; CHECK-NEXT: [[TMP107:%.*]] = load i32, ptr [[TMP79]], align 4 2837; CHECK-NEXT: [[TMP108:%.*]] = insertelement <4 x i32> poison, i32 [[TMP104]], i32 0 2838; CHECK-NEXT: [[TMP109:%.*]] = insertelement <4 x i32> [[TMP108]], i32 [[TMP105]], i32 1 2839; CHECK-NEXT: [[TMP110:%.*]] = insertelement <4 x i32> [[TMP109]], i32 [[TMP106]], i32 2 2840; CHECK-NEXT: [[TMP111:%.*]] = insertelement <4 x i32> [[TMP110]], i32 [[TMP107]], i32 3 2841; CHECK-NEXT: [[PREDPHI:%.*]] = select <4 x i1> [[TMP39]], <4 x i32> [[TMP87]], <4 x i32> zeroinitializer 2842; CHECK-NEXT: [[PREDPHI4:%.*]] = select <4 x i1> [[TMP47]], <4 x i32> [[TMP95]], <4 x i32> zeroinitializer 2843; CHECK-NEXT: [[PREDPHI5:%.*]] = select <4 x i1> [[TMP55]], <4 x i32> [[TMP103]], <4 x i32> zeroinitializer 2844; CHECK-NEXT: [[PREDPHI6:%.*]] = select <4 x i1> [[TMP63]], <4 x i32> [[TMP111]], <4 x i32> zeroinitializer 2845; CHECK-NEXT: [[TMP112]] = add <4 x i32> [[VEC_PHI]], [[PREDPHI]] 2846; CHECK-NEXT: [[TMP113]] = add <4 x i32> [[VEC_PHI1]], [[PREDPHI4]] 2847; CHECK-NEXT: [[TMP114]] = add <4 x i32> [[VEC_PHI2]], [[PREDPHI5]] 2848; CHECK-NEXT: [[TMP115]] = add <4 x i32> [[VEC_PHI3]], [[PREDPHI6]] 2849; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16 2850; CHECK-NEXT: [[TMP116:%.*]] = icmp eq i64 [[INDEX_NEXT]], 16 2851; CHECK-NEXT: br i1 [[TMP116]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP34:![0-9]+]] 2852; CHECK: middle.block: 2853; CHECK-NEXT: [[BIN_RDX:%.*]] = add <4 x i32> [[TMP113]], [[TMP112]] 2854; CHECK-NEXT: [[BIN_RDX7:%.*]] = add <4 x i32> [[TMP114]], [[BIN_RDX]] 2855; CHECK-NEXT: [[BIN_RDX8:%.*]] = add <4 x i32> [[TMP115]], [[BIN_RDX7]] 2856; CHECK-NEXT: [[TMP117:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[BIN_RDX8]]) 2857; CHECK-NEXT: br i1 false, label [[LOOP_EXIT:%.*]], label [[SCALAR_PH]] 2858; CHECK: scalar.ph: 2859; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ 80, [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ] 2860; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP117]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY]] ] 2861; CHECK-NEXT: br label [[LOOP:%.*]] 2862; CHECK: loop: 2863; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LATCH:%.*]] ] 2864; CHECK-NEXT: [[ACCUM:%.*]] = phi i32 [ [[BC_MERGE_RDX]], [[SCALAR_PH]] ], [ [[ACCUM_NEXT:%.*]], [[LATCH]] ] 2865; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 5 2866; CHECK-NEXT: [[TEST_ADDR:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[IV]] 2867; CHECK-NEXT: [[EARLYCND:%.*]] = load i1, ptr [[TEST_ADDR]], align 1 2868; CHECK-NEXT: br i1 [[EARLYCND]], label [[PRED:%.*]], label [[LATCH]] 2869; CHECK: pred: 2870; CHECK-NEXT: [[ADDR:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[IV]] 2871; CHECK-NEXT: [[VAL:%.*]] = load i32, ptr [[ADDR]], align 4 2872; CHECK-NEXT: br label [[LATCH]] 2873; CHECK: latch: 2874; CHECK-NEXT: [[VAL_PHI:%.*]] = phi i32 [ 0, [[LOOP]] ], [ [[VAL]], [[PRED]] ] 2875; CHECK-NEXT: [[ACCUM_NEXT]] = add i32 [[ACCUM]], [[VAL_PHI]] 2876; CHECK-NEXT: [[EXIT:%.*]] = icmp ugt i64 [[IV]], 100 2877; CHECK-NEXT: br i1 [[EXIT]], label [[LOOP_EXIT]], label [[LOOP]], !llvm.loop [[LOOP35:![0-9]+]] 2878; CHECK: loop_exit: 2879; CHECK-NEXT: [[ACCUM_NEXT_LCSSA:%.*]] = phi i32 [ [[ACCUM_NEXT]], [[LATCH]] ], [ [[TMP117]], [[MIDDLE_BLOCK]] ] 2880; CHECK-NEXT: ret i32 [[ACCUM_NEXT_LCSSA]] 2881; 2882entry: 2883 %alloca = alloca [110 x i32] 2884 call void @init(ptr %alloca) 2885 br label %loop 2886loop: 2887 %iv = phi i64 [ 0, %entry ], [ %iv.next, %latch ] 2888 %accum = phi i32 [ 0, %entry ], [ %accum.next, %latch ] 2889 %iv.next = add i64 %iv, 5 2890 %test_addr = getelementptr inbounds i1, ptr %test_base, i64 %iv 2891 %earlycnd = load i1, ptr %test_addr 2892 br i1 %earlycnd, label %pred, label %latch 2893pred: 2894 %addr = getelementptr inbounds i32, ptr %alloca, i64 %iv 2895 %val = load i32, ptr %addr 2896 br label %latch 2897latch: 2898 %val.phi = phi i32 [0, %loop], [%val, %pred] 2899 %accum.next = add i32 %accum, %val.phi 2900 %exit = icmp ugt i64 %iv, 100 2901 br i1 %exit, label %loop_exit, label %loop 2902 2903loop_exit: 2904 ret i32 %accum.next 2905} 2906 2907define i32 @test_non_unit_stride_off_by_four_bytes(i64 %len, ptr %test_base) { 2908; CHECK-LABEL: @test_non_unit_stride_off_by_four_bytes( 2909; CHECK-NEXT: entry: 2910; CHECK-NEXT: [[ALLOCA:%.*]] = alloca [103 x i32], align 4 2911; CHECK-NEXT: call void @init(ptr [[ALLOCA]]) 2912; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] 2913; CHECK: vector.ph: 2914; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] 2915; CHECK: vector.body: 2916; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] 2917; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP112:%.*]], [[VECTOR_BODY]] ] 2918; CHECK-NEXT: [[VEC_PHI1:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP113:%.*]], [[VECTOR_BODY]] ] 2919; CHECK-NEXT: [[VEC_PHI2:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP114:%.*]], [[VECTOR_BODY]] ] 2920; CHECK-NEXT: [[VEC_PHI3:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP115:%.*]], [[VECTOR_BODY]] ] 2921; CHECK-NEXT: [[OFFSET_IDX:%.*]] = mul i64 [[INDEX]], 2 2922; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[OFFSET_IDX]], 0 2923; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[OFFSET_IDX]], 2 2924; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[OFFSET_IDX]], 4 2925; CHECK-NEXT: [[TMP3:%.*]] = add i64 [[OFFSET_IDX]], 6 2926; CHECK-NEXT: [[TMP4:%.*]] = add i64 [[OFFSET_IDX]], 8 2927; CHECK-NEXT: [[TMP5:%.*]] = add i64 [[OFFSET_IDX]], 10 2928; CHECK-NEXT: [[TMP6:%.*]] = add i64 [[OFFSET_IDX]], 12 2929; CHECK-NEXT: [[TMP7:%.*]] = add i64 [[OFFSET_IDX]], 14 2930; CHECK-NEXT: [[TMP8:%.*]] = add i64 [[OFFSET_IDX]], 16 2931; CHECK-NEXT: [[TMP9:%.*]] = add i64 [[OFFSET_IDX]], 18 2932; CHECK-NEXT: [[TMP10:%.*]] = add i64 [[OFFSET_IDX]], 20 2933; CHECK-NEXT: [[TMP11:%.*]] = add i64 [[OFFSET_IDX]], 22 2934; CHECK-NEXT: [[TMP12:%.*]] = add i64 [[OFFSET_IDX]], 24 2935; CHECK-NEXT: [[TMP13:%.*]] = add i64 [[OFFSET_IDX]], 26 2936; CHECK-NEXT: [[TMP14:%.*]] = add i64 [[OFFSET_IDX]], 28 2937; CHECK-NEXT: [[TMP15:%.*]] = add i64 [[OFFSET_IDX]], 30 2938; CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE:%.*]], i64 [[TMP0]] 2939; CHECK-NEXT: [[TMP17:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP1]] 2940; CHECK-NEXT: [[TMP18:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP2]] 2941; CHECK-NEXT: [[TMP19:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP3]] 2942; CHECK-NEXT: [[TMP20:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP4]] 2943; CHECK-NEXT: [[TMP21:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP5]] 2944; CHECK-NEXT: [[TMP22:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP6]] 2945; CHECK-NEXT: [[TMP23:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP7]] 2946; CHECK-NEXT: [[TMP24:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP8]] 2947; CHECK-NEXT: [[TMP25:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP9]] 2948; CHECK-NEXT: [[TMP26:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP10]] 2949; CHECK-NEXT: [[TMP27:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP11]] 2950; CHECK-NEXT: [[TMP28:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP12]] 2951; CHECK-NEXT: [[TMP29:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP13]] 2952; CHECK-NEXT: [[TMP30:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP14]] 2953; CHECK-NEXT: [[TMP31:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP15]] 2954; CHECK-NEXT: [[TMP32:%.*]] = load i1, ptr [[TMP16]], align 1 2955; CHECK-NEXT: [[TMP33:%.*]] = load i1, ptr [[TMP17]], align 1 2956; CHECK-NEXT: [[TMP34:%.*]] = load i1, ptr [[TMP18]], align 1 2957; CHECK-NEXT: [[TMP35:%.*]] = load i1, ptr [[TMP19]], align 1 2958; CHECK-NEXT: [[TMP36:%.*]] = insertelement <4 x i1> poison, i1 [[TMP32]], i32 0 2959; CHECK-NEXT: [[TMP37:%.*]] = insertelement <4 x i1> [[TMP36]], i1 [[TMP33]], i32 1 2960; CHECK-NEXT: [[TMP38:%.*]] = insertelement <4 x i1> [[TMP37]], i1 [[TMP34]], i32 2 2961; CHECK-NEXT: [[TMP39:%.*]] = insertelement <4 x i1> [[TMP38]], i1 [[TMP35]], i32 3 2962; CHECK-NEXT: [[TMP40:%.*]] = load i1, ptr [[TMP20]], align 1 2963; CHECK-NEXT: [[TMP41:%.*]] = load i1, ptr [[TMP21]], align 1 2964; CHECK-NEXT: [[TMP42:%.*]] = load i1, ptr [[TMP22]], align 1 2965; CHECK-NEXT: [[TMP43:%.*]] = load i1, ptr [[TMP23]], align 1 2966; CHECK-NEXT: [[TMP44:%.*]] = insertelement <4 x i1> poison, i1 [[TMP40]], i32 0 2967; CHECK-NEXT: [[TMP45:%.*]] = insertelement <4 x i1> [[TMP44]], i1 [[TMP41]], i32 1 2968; CHECK-NEXT: [[TMP46:%.*]] = insertelement <4 x i1> [[TMP45]], i1 [[TMP42]], i32 2 2969; CHECK-NEXT: [[TMP47:%.*]] = insertelement <4 x i1> [[TMP46]], i1 [[TMP43]], i32 3 2970; CHECK-NEXT: [[TMP48:%.*]] = load i1, ptr [[TMP24]], align 1 2971; CHECK-NEXT: [[TMP49:%.*]] = load i1, ptr [[TMP25]], align 1 2972; CHECK-NEXT: [[TMP50:%.*]] = load i1, ptr [[TMP26]], align 1 2973; CHECK-NEXT: [[TMP51:%.*]] = load i1, ptr [[TMP27]], align 1 2974; CHECK-NEXT: [[TMP52:%.*]] = insertelement <4 x i1> poison, i1 [[TMP48]], i32 0 2975; CHECK-NEXT: [[TMP53:%.*]] = insertelement <4 x i1> [[TMP52]], i1 [[TMP49]], i32 1 2976; CHECK-NEXT: [[TMP54:%.*]] = insertelement <4 x i1> [[TMP53]], i1 [[TMP50]], i32 2 2977; CHECK-NEXT: [[TMP55:%.*]] = insertelement <4 x i1> [[TMP54]], i1 [[TMP51]], i32 3 2978; CHECK-NEXT: [[TMP56:%.*]] = load i1, ptr [[TMP28]], align 1 2979; CHECK-NEXT: [[TMP57:%.*]] = load i1, ptr [[TMP29]], align 1 2980; CHECK-NEXT: [[TMP58:%.*]] = load i1, ptr [[TMP30]], align 1 2981; CHECK-NEXT: [[TMP59:%.*]] = load i1, ptr [[TMP31]], align 1 2982; CHECK-NEXT: [[TMP60:%.*]] = insertelement <4 x i1> poison, i1 [[TMP56]], i32 0 2983; CHECK-NEXT: [[TMP61:%.*]] = insertelement <4 x i1> [[TMP60]], i1 [[TMP57]], i32 1 2984; CHECK-NEXT: [[TMP62:%.*]] = insertelement <4 x i1> [[TMP61]], i1 [[TMP58]], i32 2 2985; CHECK-NEXT: [[TMP63:%.*]] = insertelement <4 x i1> [[TMP62]], i1 [[TMP59]], i32 3 2986; CHECK-NEXT: [[TMP64:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP0]] 2987; CHECK-NEXT: [[TMP65:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP1]] 2988; CHECK-NEXT: [[TMP66:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP2]] 2989; CHECK-NEXT: [[TMP67:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP3]] 2990; CHECK-NEXT: [[TMP68:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP4]] 2991; CHECK-NEXT: [[TMP69:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP5]] 2992; CHECK-NEXT: [[TMP70:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP6]] 2993; CHECK-NEXT: [[TMP71:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP7]] 2994; CHECK-NEXT: [[TMP72:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP8]] 2995; CHECK-NEXT: [[TMP73:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP9]] 2996; CHECK-NEXT: [[TMP74:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP10]] 2997; CHECK-NEXT: [[TMP75:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP11]] 2998; CHECK-NEXT: [[TMP76:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP12]] 2999; CHECK-NEXT: [[TMP77:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP13]] 3000; CHECK-NEXT: [[TMP78:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP14]] 3001; CHECK-NEXT: [[TMP79:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP15]] 3002; CHECK-NEXT: [[TMP80:%.*]] = load i32, ptr [[TMP64]], align 4 3003; CHECK-NEXT: [[TMP81:%.*]] = load i32, ptr [[TMP65]], align 4 3004; CHECK-NEXT: [[TMP82:%.*]] = load i32, ptr [[TMP66]], align 4 3005; CHECK-NEXT: [[TMP83:%.*]] = load i32, ptr [[TMP67]], align 4 3006; CHECK-NEXT: [[TMP84:%.*]] = insertelement <4 x i32> poison, i32 [[TMP80]], i32 0 3007; CHECK-NEXT: [[TMP85:%.*]] = insertelement <4 x i32> [[TMP84]], i32 [[TMP81]], i32 1 3008; CHECK-NEXT: [[TMP86:%.*]] = insertelement <4 x i32> [[TMP85]], i32 [[TMP82]], i32 2 3009; CHECK-NEXT: [[TMP87:%.*]] = insertelement <4 x i32> [[TMP86]], i32 [[TMP83]], i32 3 3010; CHECK-NEXT: [[TMP88:%.*]] = load i32, ptr [[TMP68]], align 4 3011; CHECK-NEXT: [[TMP89:%.*]] = load i32, ptr [[TMP69]], align 4 3012; CHECK-NEXT: [[TMP90:%.*]] = load i32, ptr [[TMP70]], align 4 3013; CHECK-NEXT: [[TMP91:%.*]] = load i32, ptr [[TMP71]], align 4 3014; CHECK-NEXT: [[TMP92:%.*]] = insertelement <4 x i32> poison, i32 [[TMP88]], i32 0 3015; CHECK-NEXT: [[TMP93:%.*]] = insertelement <4 x i32> [[TMP92]], i32 [[TMP89]], i32 1 3016; CHECK-NEXT: [[TMP94:%.*]] = insertelement <4 x i32> [[TMP93]], i32 [[TMP90]], i32 2 3017; CHECK-NEXT: [[TMP95:%.*]] = insertelement <4 x i32> [[TMP94]], i32 [[TMP91]], i32 3 3018; CHECK-NEXT: [[TMP96:%.*]] = load i32, ptr [[TMP72]], align 4 3019; CHECK-NEXT: [[TMP97:%.*]] = load i32, ptr [[TMP73]], align 4 3020; CHECK-NEXT: [[TMP98:%.*]] = load i32, ptr [[TMP74]], align 4 3021; CHECK-NEXT: [[TMP99:%.*]] = load i32, ptr [[TMP75]], align 4 3022; CHECK-NEXT: [[TMP100:%.*]] = insertelement <4 x i32> poison, i32 [[TMP96]], i32 0 3023; CHECK-NEXT: [[TMP101:%.*]] = insertelement <4 x i32> [[TMP100]], i32 [[TMP97]], i32 1 3024; CHECK-NEXT: [[TMP102:%.*]] = insertelement <4 x i32> [[TMP101]], i32 [[TMP98]], i32 2 3025; CHECK-NEXT: [[TMP103:%.*]] = insertelement <4 x i32> [[TMP102]], i32 [[TMP99]], i32 3 3026; CHECK-NEXT: [[TMP104:%.*]] = load i32, ptr [[TMP76]], align 4 3027; CHECK-NEXT: [[TMP105:%.*]] = load i32, ptr [[TMP77]], align 4 3028; CHECK-NEXT: [[TMP106:%.*]] = load i32, ptr [[TMP78]], align 4 3029; CHECK-NEXT: [[TMP107:%.*]] = load i32, ptr [[TMP79]], align 4 3030; CHECK-NEXT: [[TMP108:%.*]] = insertelement <4 x i32> poison, i32 [[TMP104]], i32 0 3031; CHECK-NEXT: [[TMP109:%.*]] = insertelement <4 x i32> [[TMP108]], i32 [[TMP105]], i32 1 3032; CHECK-NEXT: [[TMP110:%.*]] = insertelement <4 x i32> [[TMP109]], i32 [[TMP106]], i32 2 3033; CHECK-NEXT: [[TMP111:%.*]] = insertelement <4 x i32> [[TMP110]], i32 [[TMP107]], i32 3 3034; CHECK-NEXT: [[PREDPHI:%.*]] = select <4 x i1> [[TMP39]], <4 x i32> [[TMP87]], <4 x i32> zeroinitializer 3035; CHECK-NEXT: [[PREDPHI4:%.*]] = select <4 x i1> [[TMP47]], <4 x i32> [[TMP95]], <4 x i32> zeroinitializer 3036; CHECK-NEXT: [[PREDPHI5:%.*]] = select <4 x i1> [[TMP55]], <4 x i32> [[TMP103]], <4 x i32> zeroinitializer 3037; CHECK-NEXT: [[PREDPHI6:%.*]] = select <4 x i1> [[TMP63]], <4 x i32> [[TMP111]], <4 x i32> zeroinitializer 3038; CHECK-NEXT: [[TMP112]] = add <4 x i32> [[VEC_PHI]], [[PREDPHI]] 3039; CHECK-NEXT: [[TMP113]] = add <4 x i32> [[VEC_PHI1]], [[PREDPHI4]] 3040; CHECK-NEXT: [[TMP114]] = add <4 x i32> [[VEC_PHI2]], [[PREDPHI5]] 3041; CHECK-NEXT: [[TMP115]] = add <4 x i32> [[VEC_PHI3]], [[PREDPHI6]] 3042; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16 3043; CHECK-NEXT: [[TMP116:%.*]] = icmp eq i64 [[INDEX_NEXT]], 48 3044; CHECK-NEXT: br i1 [[TMP116]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP36:![0-9]+]] 3045; CHECK: middle.block: 3046; CHECK-NEXT: [[BIN_RDX:%.*]] = add <4 x i32> [[TMP113]], [[TMP112]] 3047; CHECK-NEXT: [[BIN_RDX7:%.*]] = add <4 x i32> [[TMP114]], [[BIN_RDX]] 3048; CHECK-NEXT: [[BIN_RDX8:%.*]] = add <4 x i32> [[TMP115]], [[BIN_RDX7]] 3049; CHECK-NEXT: [[TMP117:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[BIN_RDX8]]) 3050; CHECK-NEXT: br i1 false, label [[LOOP_EXIT:%.*]], label [[SCALAR_PH]] 3051; CHECK: scalar.ph: 3052; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ 96, [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ] 3053; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP117]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY]] ] 3054; CHECK-NEXT: br label [[LOOP:%.*]] 3055; CHECK: loop: 3056; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LATCH:%.*]] ] 3057; CHECK-NEXT: [[ACCUM:%.*]] = phi i32 [ [[BC_MERGE_RDX]], [[SCALAR_PH]] ], [ [[ACCUM_NEXT:%.*]], [[LATCH]] ] 3058; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 2 3059; CHECK-NEXT: [[TEST_ADDR:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[IV]] 3060; CHECK-NEXT: [[EARLYCND:%.*]] = load i1, ptr [[TEST_ADDR]], align 1 3061; CHECK-NEXT: br i1 [[EARLYCND]], label [[PRED:%.*]], label [[LATCH]] 3062; CHECK: pred: 3063; CHECK-NEXT: [[ADDR:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[IV]] 3064; CHECK-NEXT: [[VAL:%.*]] = load i32, ptr [[ADDR]], align 4 3065; CHECK-NEXT: br label [[LATCH]] 3066; CHECK: latch: 3067; CHECK-NEXT: [[VAL_PHI:%.*]] = phi i32 [ 0, [[LOOP]] ], [ [[VAL]], [[PRED]] ] 3068; CHECK-NEXT: [[ACCUM_NEXT]] = add i32 [[ACCUM]], [[VAL_PHI]] 3069; CHECK-NEXT: [[EXIT:%.*]] = icmp ugt i64 [[IV]], 100 3070; CHECK-NEXT: br i1 [[EXIT]], label [[LOOP_EXIT]], label [[LOOP]], !llvm.loop [[LOOP37:![0-9]+]] 3071; CHECK: loop_exit: 3072; CHECK-NEXT: [[ACCUM_NEXT_LCSSA:%.*]] = phi i32 [ [[ACCUM_NEXT]], [[LATCH]] ], [ [[TMP117]], [[MIDDLE_BLOCK]] ] 3073; CHECK-NEXT: ret i32 [[ACCUM_NEXT_LCSSA]] 3074; 3075entry: 3076 %alloca = alloca [103 x i32] 3077 call void @init(ptr %alloca) 3078 br label %loop 3079loop: 3080 %iv = phi i64 [ 0, %entry ], [ %iv.next, %latch ] 3081 %accum = phi i32 [ 0, %entry ], [ %accum.next, %latch ] 3082 %iv.next = add i64 %iv, 2 3083 %test_addr = getelementptr inbounds i1, ptr %test_base, i64 %iv 3084 %earlycnd = load i1, ptr %test_addr 3085 br i1 %earlycnd, label %pred, label %latch 3086pred: 3087 %addr = getelementptr inbounds i32, ptr %alloca, i64 %iv 3088 %val = load i32, ptr %addr 3089 br label %latch 3090latch: 3091 %val.phi = phi i32 [0, %loop], [%val, %pred] 3092 %accum.next = add i32 %accum, %val.phi 3093 %exit = icmp ugt i64 %iv, 100 3094 br i1 %exit, label %loop_exit, label %loop 3095 3096loop_exit: 3097 ret i32 %accum.next 3098} 3099 3100; Start value of AddRec is not a value (%alloca + 4) 3101define i32 @test_non_unit_stride_with_first_iteration_step_access(i64 %len, ptr %test_base) { 3102; CHECK-LABEL: @test_non_unit_stride_with_first_iteration_step_access( 3103; CHECK-NEXT: entry: 3104; CHECK-NEXT: [[ALLOCA:%.*]] = alloca [4096 x i32], align 4 3105; CHECK-NEXT: call void @init(ptr [[ALLOCA]]) 3106; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] 3107; CHECK: vector.ph: 3108; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] 3109; CHECK: vector.body: 3110; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] 3111; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP128:%.*]], [[VECTOR_BODY]] ] 3112; CHECK-NEXT: [[VEC_PHI1:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP129:%.*]], [[VECTOR_BODY]] ] 3113; CHECK-NEXT: [[VEC_PHI2:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP130:%.*]], [[VECTOR_BODY]] ] 3114; CHECK-NEXT: [[VEC_PHI3:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP131:%.*]], [[VECTOR_BODY]] ] 3115; CHECK-NEXT: [[OFFSET_IDX:%.*]] = mul i64 [[INDEX]], 2 3116; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[OFFSET_IDX]], 0 3117; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[OFFSET_IDX]], 2 3118; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[OFFSET_IDX]], 4 3119; CHECK-NEXT: [[TMP3:%.*]] = add i64 [[OFFSET_IDX]], 6 3120; CHECK-NEXT: [[TMP4:%.*]] = add i64 [[OFFSET_IDX]], 8 3121; CHECK-NEXT: [[TMP5:%.*]] = add i64 [[OFFSET_IDX]], 10 3122; CHECK-NEXT: [[TMP6:%.*]] = add i64 [[OFFSET_IDX]], 12 3123; CHECK-NEXT: [[TMP7:%.*]] = add i64 [[OFFSET_IDX]], 14 3124; CHECK-NEXT: [[TMP8:%.*]] = add i64 [[OFFSET_IDX]], 16 3125; CHECK-NEXT: [[TMP9:%.*]] = add i64 [[OFFSET_IDX]], 18 3126; CHECK-NEXT: [[TMP10:%.*]] = add i64 [[OFFSET_IDX]], 20 3127; CHECK-NEXT: [[TMP11:%.*]] = add i64 [[OFFSET_IDX]], 22 3128; CHECK-NEXT: [[TMP12:%.*]] = add i64 [[OFFSET_IDX]], 24 3129; CHECK-NEXT: [[TMP13:%.*]] = add i64 [[OFFSET_IDX]], 26 3130; CHECK-NEXT: [[TMP14:%.*]] = add i64 [[OFFSET_IDX]], 28 3131; CHECK-NEXT: [[TMP15:%.*]] = add i64 [[OFFSET_IDX]], 30 3132; CHECK-NEXT: [[TMP16:%.*]] = add i64 [[TMP0]], 2 3133; CHECK-NEXT: [[TMP17:%.*]] = add i64 [[TMP1]], 2 3134; CHECK-NEXT: [[TMP18:%.*]] = add i64 [[TMP2]], 2 3135; CHECK-NEXT: [[TMP19:%.*]] = add i64 [[TMP3]], 2 3136; CHECK-NEXT: [[TMP20:%.*]] = add i64 [[TMP4]], 2 3137; CHECK-NEXT: [[TMP21:%.*]] = add i64 [[TMP5]], 2 3138; CHECK-NEXT: [[TMP22:%.*]] = add i64 [[TMP6]], 2 3139; CHECK-NEXT: [[TMP23:%.*]] = add i64 [[TMP7]], 2 3140; CHECK-NEXT: [[TMP24:%.*]] = add i64 [[TMP8]], 2 3141; CHECK-NEXT: [[TMP25:%.*]] = add i64 [[TMP9]], 2 3142; CHECK-NEXT: [[TMP26:%.*]] = add i64 [[TMP10]], 2 3143; CHECK-NEXT: [[TMP27:%.*]] = add i64 [[TMP11]], 2 3144; CHECK-NEXT: [[TMP28:%.*]] = add i64 [[TMP12]], 2 3145; CHECK-NEXT: [[TMP29:%.*]] = add i64 [[TMP13]], 2 3146; CHECK-NEXT: [[TMP30:%.*]] = add i64 [[TMP14]], 2 3147; CHECK-NEXT: [[TMP31:%.*]] = add i64 [[TMP15]], 2 3148; CHECK-NEXT: [[TMP32:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE:%.*]], i64 [[TMP0]] 3149; CHECK-NEXT: [[TMP33:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP1]] 3150; CHECK-NEXT: [[TMP34:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP2]] 3151; CHECK-NEXT: [[TMP35:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP3]] 3152; CHECK-NEXT: [[TMP36:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP4]] 3153; CHECK-NEXT: [[TMP37:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP5]] 3154; CHECK-NEXT: [[TMP38:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP6]] 3155; CHECK-NEXT: [[TMP39:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP7]] 3156; CHECK-NEXT: [[TMP40:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP8]] 3157; CHECK-NEXT: [[TMP41:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP9]] 3158; CHECK-NEXT: [[TMP42:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP10]] 3159; CHECK-NEXT: [[TMP43:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP11]] 3160; CHECK-NEXT: [[TMP44:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP12]] 3161; CHECK-NEXT: [[TMP45:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP13]] 3162; CHECK-NEXT: [[TMP46:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP14]] 3163; CHECK-NEXT: [[TMP47:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[TMP15]] 3164; CHECK-NEXT: [[TMP48:%.*]] = load i1, ptr [[TMP32]], align 1 3165; CHECK-NEXT: [[TMP49:%.*]] = load i1, ptr [[TMP33]], align 1 3166; CHECK-NEXT: [[TMP50:%.*]] = load i1, ptr [[TMP34]], align 1 3167; CHECK-NEXT: [[TMP51:%.*]] = load i1, ptr [[TMP35]], align 1 3168; CHECK-NEXT: [[TMP52:%.*]] = insertelement <4 x i1> poison, i1 [[TMP48]], i32 0 3169; CHECK-NEXT: [[TMP53:%.*]] = insertelement <4 x i1> [[TMP52]], i1 [[TMP49]], i32 1 3170; CHECK-NEXT: [[TMP54:%.*]] = insertelement <4 x i1> [[TMP53]], i1 [[TMP50]], i32 2 3171; CHECK-NEXT: [[TMP55:%.*]] = insertelement <4 x i1> [[TMP54]], i1 [[TMP51]], i32 3 3172; CHECK-NEXT: [[TMP56:%.*]] = load i1, ptr [[TMP36]], align 1 3173; CHECK-NEXT: [[TMP57:%.*]] = load i1, ptr [[TMP37]], align 1 3174; CHECK-NEXT: [[TMP58:%.*]] = load i1, ptr [[TMP38]], align 1 3175; CHECK-NEXT: [[TMP59:%.*]] = load i1, ptr [[TMP39]], align 1 3176; CHECK-NEXT: [[TMP60:%.*]] = insertelement <4 x i1> poison, i1 [[TMP56]], i32 0 3177; CHECK-NEXT: [[TMP61:%.*]] = insertelement <4 x i1> [[TMP60]], i1 [[TMP57]], i32 1 3178; CHECK-NEXT: [[TMP62:%.*]] = insertelement <4 x i1> [[TMP61]], i1 [[TMP58]], i32 2 3179; CHECK-NEXT: [[TMP63:%.*]] = insertelement <4 x i1> [[TMP62]], i1 [[TMP59]], i32 3 3180; CHECK-NEXT: [[TMP64:%.*]] = load i1, ptr [[TMP40]], align 1 3181; CHECK-NEXT: [[TMP65:%.*]] = load i1, ptr [[TMP41]], align 1 3182; CHECK-NEXT: [[TMP66:%.*]] = load i1, ptr [[TMP42]], align 1 3183; CHECK-NEXT: [[TMP67:%.*]] = load i1, ptr [[TMP43]], align 1 3184; CHECK-NEXT: [[TMP68:%.*]] = insertelement <4 x i1> poison, i1 [[TMP64]], i32 0 3185; CHECK-NEXT: [[TMP69:%.*]] = insertelement <4 x i1> [[TMP68]], i1 [[TMP65]], i32 1 3186; CHECK-NEXT: [[TMP70:%.*]] = insertelement <4 x i1> [[TMP69]], i1 [[TMP66]], i32 2 3187; CHECK-NEXT: [[TMP71:%.*]] = insertelement <4 x i1> [[TMP70]], i1 [[TMP67]], i32 3 3188; CHECK-NEXT: [[TMP72:%.*]] = load i1, ptr [[TMP44]], align 1 3189; CHECK-NEXT: [[TMP73:%.*]] = load i1, ptr [[TMP45]], align 1 3190; CHECK-NEXT: [[TMP74:%.*]] = load i1, ptr [[TMP46]], align 1 3191; CHECK-NEXT: [[TMP75:%.*]] = load i1, ptr [[TMP47]], align 1 3192; CHECK-NEXT: [[TMP76:%.*]] = insertelement <4 x i1> poison, i1 [[TMP72]], i32 0 3193; CHECK-NEXT: [[TMP77:%.*]] = insertelement <4 x i1> [[TMP76]], i1 [[TMP73]], i32 1 3194; CHECK-NEXT: [[TMP78:%.*]] = insertelement <4 x i1> [[TMP77]], i1 [[TMP74]], i32 2 3195; CHECK-NEXT: [[TMP79:%.*]] = insertelement <4 x i1> [[TMP78]], i1 [[TMP75]], i32 3 3196; CHECK-NEXT: [[TMP80:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP16]] 3197; CHECK-NEXT: [[TMP81:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP17]] 3198; CHECK-NEXT: [[TMP82:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP18]] 3199; CHECK-NEXT: [[TMP83:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP19]] 3200; CHECK-NEXT: [[TMP84:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP20]] 3201; CHECK-NEXT: [[TMP85:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP21]] 3202; CHECK-NEXT: [[TMP86:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP22]] 3203; CHECK-NEXT: [[TMP87:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP23]] 3204; CHECK-NEXT: [[TMP88:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP24]] 3205; CHECK-NEXT: [[TMP89:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP25]] 3206; CHECK-NEXT: [[TMP90:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP26]] 3207; CHECK-NEXT: [[TMP91:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP27]] 3208; CHECK-NEXT: [[TMP92:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP28]] 3209; CHECK-NEXT: [[TMP93:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP29]] 3210; CHECK-NEXT: [[TMP94:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP30]] 3211; CHECK-NEXT: [[TMP95:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[TMP31]] 3212; CHECK-NEXT: [[TMP96:%.*]] = load i32, ptr [[TMP80]], align 4 3213; CHECK-NEXT: [[TMP97:%.*]] = load i32, ptr [[TMP81]], align 4 3214; CHECK-NEXT: [[TMP98:%.*]] = load i32, ptr [[TMP82]], align 4 3215; CHECK-NEXT: [[TMP99:%.*]] = load i32, ptr [[TMP83]], align 4 3216; CHECK-NEXT: [[TMP100:%.*]] = insertelement <4 x i32> poison, i32 [[TMP96]], i32 0 3217; CHECK-NEXT: [[TMP101:%.*]] = insertelement <4 x i32> [[TMP100]], i32 [[TMP97]], i32 1 3218; CHECK-NEXT: [[TMP102:%.*]] = insertelement <4 x i32> [[TMP101]], i32 [[TMP98]], i32 2 3219; CHECK-NEXT: [[TMP103:%.*]] = insertelement <4 x i32> [[TMP102]], i32 [[TMP99]], i32 3 3220; CHECK-NEXT: [[TMP104:%.*]] = load i32, ptr [[TMP84]], align 4 3221; CHECK-NEXT: [[TMP105:%.*]] = load i32, ptr [[TMP85]], align 4 3222; CHECK-NEXT: [[TMP106:%.*]] = load i32, ptr [[TMP86]], align 4 3223; CHECK-NEXT: [[TMP107:%.*]] = load i32, ptr [[TMP87]], align 4 3224; CHECK-NEXT: [[TMP108:%.*]] = insertelement <4 x i32> poison, i32 [[TMP104]], i32 0 3225; CHECK-NEXT: [[TMP109:%.*]] = insertelement <4 x i32> [[TMP108]], i32 [[TMP105]], i32 1 3226; CHECK-NEXT: [[TMP110:%.*]] = insertelement <4 x i32> [[TMP109]], i32 [[TMP106]], i32 2 3227; CHECK-NEXT: [[TMP111:%.*]] = insertelement <4 x i32> [[TMP110]], i32 [[TMP107]], i32 3 3228; CHECK-NEXT: [[TMP112:%.*]] = load i32, ptr [[TMP88]], align 4 3229; CHECK-NEXT: [[TMP113:%.*]] = load i32, ptr [[TMP89]], align 4 3230; CHECK-NEXT: [[TMP114:%.*]] = load i32, ptr [[TMP90]], align 4 3231; CHECK-NEXT: [[TMP115:%.*]] = load i32, ptr [[TMP91]], align 4 3232; CHECK-NEXT: [[TMP116:%.*]] = insertelement <4 x i32> poison, i32 [[TMP112]], i32 0 3233; CHECK-NEXT: [[TMP117:%.*]] = insertelement <4 x i32> [[TMP116]], i32 [[TMP113]], i32 1 3234; CHECK-NEXT: [[TMP118:%.*]] = insertelement <4 x i32> [[TMP117]], i32 [[TMP114]], i32 2 3235; CHECK-NEXT: [[TMP119:%.*]] = insertelement <4 x i32> [[TMP118]], i32 [[TMP115]], i32 3 3236; CHECK-NEXT: [[TMP120:%.*]] = load i32, ptr [[TMP92]], align 4 3237; CHECK-NEXT: [[TMP121:%.*]] = load i32, ptr [[TMP93]], align 4 3238; CHECK-NEXT: [[TMP122:%.*]] = load i32, ptr [[TMP94]], align 4 3239; CHECK-NEXT: [[TMP123:%.*]] = load i32, ptr [[TMP95]], align 4 3240; CHECK-NEXT: [[TMP124:%.*]] = insertelement <4 x i32> poison, i32 [[TMP120]], i32 0 3241; CHECK-NEXT: [[TMP125:%.*]] = insertelement <4 x i32> [[TMP124]], i32 [[TMP121]], i32 1 3242; CHECK-NEXT: [[TMP126:%.*]] = insertelement <4 x i32> [[TMP125]], i32 [[TMP122]], i32 2 3243; CHECK-NEXT: [[TMP127:%.*]] = insertelement <4 x i32> [[TMP126]], i32 [[TMP123]], i32 3 3244; CHECK-NEXT: [[PREDPHI:%.*]] = select <4 x i1> [[TMP55]], <4 x i32> [[TMP103]], <4 x i32> zeroinitializer 3245; CHECK-NEXT: [[PREDPHI4:%.*]] = select <4 x i1> [[TMP63]], <4 x i32> [[TMP111]], <4 x i32> zeroinitializer 3246; CHECK-NEXT: [[PREDPHI5:%.*]] = select <4 x i1> [[TMP71]], <4 x i32> [[TMP119]], <4 x i32> zeroinitializer 3247; CHECK-NEXT: [[PREDPHI6:%.*]] = select <4 x i1> [[TMP79]], <4 x i32> [[TMP127]], <4 x i32> zeroinitializer 3248; CHECK-NEXT: [[TMP128]] = add <4 x i32> [[VEC_PHI]], [[PREDPHI]] 3249; CHECK-NEXT: [[TMP129]] = add <4 x i32> [[VEC_PHI1]], [[PREDPHI4]] 3250; CHECK-NEXT: [[TMP130]] = add <4 x i32> [[VEC_PHI2]], [[PREDPHI5]] 3251; CHECK-NEXT: [[TMP131]] = add <4 x i32> [[VEC_PHI3]], [[PREDPHI6]] 3252; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16 3253; CHECK-NEXT: [[TMP132:%.*]] = icmp eq i64 [[INDEX_NEXT]], 144 3254; CHECK-NEXT: br i1 [[TMP132]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP38:![0-9]+]] 3255; CHECK: middle.block: 3256; CHECK-NEXT: [[BIN_RDX:%.*]] = add <4 x i32> [[TMP129]], [[TMP128]] 3257; CHECK-NEXT: [[BIN_RDX7:%.*]] = add <4 x i32> [[TMP130]], [[BIN_RDX]] 3258; CHECK-NEXT: [[BIN_RDX8:%.*]] = add <4 x i32> [[TMP131]], [[BIN_RDX7]] 3259; CHECK-NEXT: [[TMP133:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[BIN_RDX8]]) 3260; CHECK-NEXT: br i1 false, label [[LOOP_EXIT:%.*]], label [[SCALAR_PH]] 3261; CHECK: scalar.ph: 3262; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ 288, [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ] 3263; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP133]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY]] ] 3264; CHECK-NEXT: br label [[LOOP:%.*]] 3265; CHECK: loop: 3266; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LATCH:%.*]] ] 3267; CHECK-NEXT: [[ACCUM:%.*]] = phi i32 [ [[BC_MERGE_RDX]], [[SCALAR_PH]] ], [ [[ACCUM_NEXT:%.*]], [[LATCH]] ] 3268; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 2 3269; CHECK-NEXT: [[TEST_ADDR:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i64 [[IV]] 3270; CHECK-NEXT: [[EARLYCND:%.*]] = load i1, ptr [[TEST_ADDR]], align 1 3271; CHECK-NEXT: br i1 [[EARLYCND]], label [[PRED:%.*]], label [[LATCH]] 3272; CHECK: pred: 3273; CHECK-NEXT: [[ADDR:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 [[IV_NEXT]] 3274; CHECK-NEXT: [[VAL:%.*]] = load i32, ptr [[ADDR]], align 4 3275; CHECK-NEXT: br label [[LATCH]] 3276; CHECK: latch: 3277; CHECK-NEXT: [[VAL_PHI:%.*]] = phi i32 [ 0, [[LOOP]] ], [ [[VAL]], [[PRED]] ] 3278; CHECK-NEXT: [[ACCUM_NEXT]] = add i32 [[ACCUM]], [[VAL_PHI]] 3279; CHECK-NEXT: [[EXIT:%.*]] = icmp ugt i64 [[IV]], 300 3280; CHECK-NEXT: br i1 [[EXIT]], label [[LOOP_EXIT]], label [[LOOP]], !llvm.loop [[LOOP39:![0-9]+]] 3281; CHECK: loop_exit: 3282; CHECK-NEXT: [[ACCUM_NEXT_LCSSA:%.*]] = phi i32 [ [[ACCUM_NEXT]], [[LATCH]] ], [ [[TMP133]], [[MIDDLE_BLOCK]] ] 3283; CHECK-NEXT: ret i32 [[ACCUM_NEXT_LCSSA]] 3284; 3285entry: 3286 %alloca = alloca [4096 x i32] 3287 call void @init(ptr %alloca) 3288 br label %loop 3289loop: 3290 %iv = phi i64 [ 0, %entry ], [ %iv.next, %latch ] 3291 %accum = phi i32 [ 0, %entry ], [ %accum.next, %latch ] 3292 %iv.next = add i64 %iv, 2 3293 %test_addr = getelementptr inbounds i1, ptr %test_base, i64 %iv 3294 %earlycnd = load i1, ptr %test_addr 3295 br i1 %earlycnd, label %pred, label %latch 3296pred: 3297 %addr = getelementptr inbounds i32, ptr %alloca, i64 %iv.next 3298 %val = load i32, ptr %addr 3299 br label %latch 3300latch: 3301 %val.phi = phi i32 [0, %loop], [%val, %pred] 3302 %accum.next = add i32 %accum, %val.phi 3303 %exit = icmp ugt i64 %iv,300 3304 br i1 %exit, label %loop_exit, label %loop 3305 3306loop_exit: 3307 ret i32 %accum.next 3308} 3309