1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5 2; RUN: opt -p loop-vectorize -mcpu=skylake-avx512 -S %s | FileCheck %s 3 4target triple = "x86_64-unknown-linux-gnu" 5 6define i64 @test_pr98660(ptr %dst, i64 %N) { 7; CHECK-LABEL: define i64 @test_pr98660( 8; CHECK-SAME: ptr [[DST:%.*]], i64 [[N:%.*]]) #[[ATTR0:[0-9]+]] { 9; CHECK-NEXT: [[ENTRY:.*]]: 10; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[N]], 1 11; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP0]], 32 12; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] 13; CHECK: [[VECTOR_PH]]: 14; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP0]], 32 15; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP0]], [[N_MOD_VF]] 16; CHECK-NEXT: br label %[[VECTOR_BODY:.*]] 17; CHECK: [[VECTOR_BODY]]: 18; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] 19; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[INDEX]], 0 20; CHECK-NEXT: [[TMP5:%.*]] = add i64 [[TMP1]], 1 21; CHECK-NEXT: [[TMP9:%.*]] = getelementptr i32, ptr [[DST]], i64 [[TMP5]] 22; CHECK-NEXT: [[TMP13:%.*]] = getelementptr i32, ptr [[TMP9]], i32 0 23; CHECK-NEXT: [[TMP14:%.*]] = getelementptr i32, ptr [[TMP9]], i32 8 24; CHECK-NEXT: [[TMP15:%.*]] = getelementptr i32, ptr [[TMP9]], i32 16 25; CHECK-NEXT: [[TMP16:%.*]] = getelementptr i32, ptr [[TMP9]], i32 24 26; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <8 x i32>, ptr [[TMP13]], align 4 27; CHECK-NEXT: [[WIDE_LOAD1:%.*]] = load <8 x i32>, ptr [[TMP14]], align 4 28; CHECK-NEXT: [[WIDE_LOAD2:%.*]] = load <8 x i32>, ptr [[TMP15]], align 4 29; CHECK-NEXT: [[WIDE_LOAD3:%.*]] = load <8 x i32>, ptr [[TMP16]], align 4 30; CHECK-NEXT: [[TMP17:%.*]] = icmp eq <8 x i32> [[WIDE_LOAD]], zeroinitializer 31; CHECK-NEXT: [[TMP18:%.*]] = icmp eq <8 x i32> [[WIDE_LOAD1]], zeroinitializer 32; CHECK-NEXT: [[TMP19:%.*]] = icmp eq <8 x i32> [[WIDE_LOAD2]], zeroinitializer 33; CHECK-NEXT: [[TMP20:%.*]] = icmp eq <8 x i32> [[WIDE_LOAD3]], zeroinitializer 34; CHECK-NEXT: call void @llvm.masked.store.v8i32.p0(<8 x i32> zeroinitializer, ptr [[TMP13]], i32 4, <8 x i1> [[TMP17]]) 35; CHECK-NEXT: call void @llvm.masked.store.v8i32.p0(<8 x i32> zeroinitializer, ptr [[TMP14]], i32 4, <8 x i1> [[TMP18]]) 36; CHECK-NEXT: call void @llvm.masked.store.v8i32.p0(<8 x i32> zeroinitializer, ptr [[TMP15]], i32 4, <8 x i1> [[TMP19]]) 37; CHECK-NEXT: call void @llvm.masked.store.v8i32.p0(<8 x i32> zeroinitializer, ptr [[TMP16]], i32 4, <8 x i1> [[TMP20]]) 38; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 32 39; CHECK-NEXT: [[TMP21:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] 40; CHECK-NEXT: br i1 [[TMP21]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] 41; CHECK: [[MIDDLE_BLOCK]]: 42; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP0]], [[N_VEC]] 43; CHECK-NEXT: [[IND_ESCAPE:%.*]] = sub i64 [[N_VEC]], 1 44; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]] 45; CHECK: [[SCALAR_PH]]: 46; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ] 47; CHECK-NEXT: br label %[[LOOP_HEADER:.*]] 48; CHECK: [[LOOP_HEADER]]: 49; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP_LATCH:.*]] ] 50; CHECK-NEXT: [[OR:%.*]] = or disjoint i64 [[IV]], 1 51; CHECK-NEXT: [[GEP:%.*]] = getelementptr i32, ptr [[DST]], i64 [[OR]] 52; CHECK-NEXT: [[L:%.*]] = load i32, ptr [[GEP]], align 4 53; CHECK-NEXT: [[C:%.*]] = icmp eq i32 [[L]], 0 54; CHECK-NEXT: br i1 [[C]], label %[[THEN:.*]], label %[[LOOP_LATCH]] 55; CHECK: [[THEN]]: 56; CHECK-NEXT: store i32 0, ptr [[GEP]], align 4 57; CHECK-NEXT: br label %[[LOOP_LATCH]] 58; CHECK: [[LOOP_LATCH]]: 59; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1 60; CHECK-NEXT: [[EC:%.*]] = icmp ult i64 [[IV]], [[N]] 61; CHECK-NEXT: br i1 [[EC]], label %[[LOOP_HEADER]], label %[[EXIT]], !llvm.loop [[LOOP3:![0-9]+]] 62; CHECK: [[EXIT]]: 63; CHECK-NEXT: [[RET:%.*]] = phi i64 [ [[IV]], %[[LOOP_LATCH]] ], [ [[IND_ESCAPE]], %[[MIDDLE_BLOCK]] ] 64; CHECK-NEXT: ret i64 [[RET]] 65; 66entry: 67 br label %loop.header 68 69loop.header: 70 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop.latch ] 71 %or = or disjoint i64 %iv, 1 72 %gep = getelementptr i32, ptr %dst, i64 %or 73 %l = load i32, ptr %gep 74 %c = icmp eq i32 %l, 0 75 br i1 %c, label %then, label %loop.latch 76 77then: 78 store i32 0, ptr %gep, align 4 79 br label %loop.latch 80 81loop.latch: 82 %iv.next = add i64 %iv, 1 83 %ec = icmp ult i64 %iv, %N 84 br i1 %ec, label %loop.header, label %exit 85 86exit: 87 %ret = phi i64 [ %iv, %loop.latch ] 88 ret i64 %ret 89} 90;. 91; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]} 92; CHECK: [[META1]] = !{!"llvm.loop.isvectorized", i32 1} 93; CHECK: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"} 94; CHECK: [[LOOP3]] = distinct !{[[LOOP3]], [[META2]], [[META1]]} 95;. 96