xref: /llvm-project/llvm/test/Transforms/LoopVectorize/X86/cost-model.ll (revision 1de3dc7d23dd6b856efad3a3a04f2396328726d7) 
1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2; RUN: opt < %s -passes=loop-vectorize -mtriple=x86_64-apple-macosx10.8.0 -mcpu=corei7-avx -S | FileCheck %s
3
4target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
5target triple = "x86_64-apple-macosx10.8.0"
6
7@c = common global [2048 x i32] zeroinitializer, align 16
8@b = common global [2048 x i32] zeroinitializer, align 16
9@d = common global [2048 x i32] zeroinitializer, align 16
10@a = common global [2048 x i32] zeroinitializer, align 16
11
12; The program below gathers and scatters data. We better not vectorize it.
13define void @cost_model_1() nounwind uwtable noinline ssp {
14; CHECK-LABEL: @cost_model_1(
15; CHECK-NEXT:  entry:
16; CHECK-NEXT:    br label [[FOR_BODY:%.*]]
17; CHECK:       for.body:
18; CHECK-NEXT:    [[INDVARS_IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INDVARS_IV_NEXT:%.*]], [[FOR_BODY]] ]
19; CHECK-NEXT:    [[TMP0:%.*]] = shl nsw i64 [[INDVARS_IV]], 1
20; CHECK-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2048 x i32], ptr @c, i64 0, i64 [[TMP0]]
21; CHECK-NEXT:    [[TMP1:%.*]] = load i32, ptr [[ARRAYIDX]], align 8
22; CHECK-NEXT:    [[IDXPROM1:%.*]] = sext i32 [[TMP1]] to i64
23; CHECK-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds [2048 x i32], ptr @b, i64 0, i64 [[IDXPROM1]]
24; CHECK-NEXT:    [[TMP2:%.*]] = load i32, ptr [[ARRAYIDX2]], align 4
25; CHECK-NEXT:    [[ARRAYIDX4:%.*]] = getelementptr inbounds [2048 x i32], ptr @d, i64 0, i64 [[INDVARS_IV]]
26; CHECK-NEXT:    [[TMP3:%.*]] = load i32, ptr [[ARRAYIDX4]], align 4
27; CHECK-NEXT:    [[IDXPROM5:%.*]] = sext i32 [[TMP3]] to i64
28; CHECK-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds [2048 x i32], ptr @a, i64 0, i64 [[IDXPROM5]]
29; CHECK-NEXT:    store i32 [[TMP2]], ptr [[ARRAYIDX6]], align 4
30; CHECK-NEXT:    [[INDVARS_IV_NEXT]] = add i64 [[INDVARS_IV]], 1
31; CHECK-NEXT:    [[LFTR_WIDEIV:%.*]] = trunc i64 [[INDVARS_IV_NEXT]] to i32
32; CHECK-NEXT:    [[EXITCOND:%.*]] = icmp eq i32 [[LFTR_WIDEIV]], 256
33; CHECK-NEXT:    br i1 [[EXITCOND]], label [[FOR_END:%.*]], label [[FOR_BODY]]
34; CHECK:       for.end:
35; CHECK-NEXT:    ret void
36;
37entry:
38  br label %for.body
39
40for.body:                                         ; preds = %for.body, %entry
41  %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
42  %0 = shl nsw i64 %indvars.iv, 1
43  %arrayidx = getelementptr inbounds [2048 x i32], ptr @c, i64 0, i64 %0
44  %1 = load i32, ptr %arrayidx, align 8
45  %idxprom1 = sext i32 %1 to i64
46  %arrayidx2 = getelementptr inbounds [2048 x i32], ptr @b, i64 0, i64 %idxprom1
47  %2 = load i32, ptr %arrayidx2, align 4
48  %arrayidx4 = getelementptr inbounds [2048 x i32], ptr @d, i64 0, i64 %indvars.iv
49  %3 = load i32, ptr %arrayidx4, align 4
50  %idxprom5 = sext i32 %3 to i64
51  %arrayidx6 = getelementptr inbounds [2048 x i32], ptr @a, i64 0, i64 %idxprom5
52  store i32 %2, ptr %arrayidx6, align 4
53  %indvars.iv.next = add i64 %indvars.iv, 1
54  %lftr.wideiv = trunc i64 %indvars.iv.next to i32
55  %exitcond = icmp eq i32 %lftr.wideiv, 256
56  br i1 %exitcond, label %for.end, label %for.body
57
58for.end:                                          ; preds = %for.body
59  ret void
60}
61
62; This function uses a stride that is generally too big to benefit from vectorization without
63; really good support for a gather load. But if we don't vectorize the pointer induction,
64; then we don't need to extract the pointers out of vector of pointers,
65; and the vectorization becomes profitable.
66
67define float @PR27826(ptr nocapture readonly %a, ptr nocapture readonly %b, i32 %n) {
68; CHECK-LABEL: @PR27826(
69; CHECK-NEXT:  entry:
70; CHECK-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[N:%.*]], 0
71; CHECK-NEXT:    br i1 [[CMP]], label [[ITER_CHECK:%.*]], label [[FOR_END:%.*]]
72; CHECK:       iter.check:
73; CHECK-NEXT:    [[T0:%.*]] = sext i32 [[N]] to i64
74; CHECK-NEXT:    [[TMP0:%.*]] = add nsw i64 [[T0]], -1
75; CHECK-NEXT:    [[TMP1:%.*]] = lshr i64 [[TMP0]], 5
76; CHECK-NEXT:    [[TMP2:%.*]] = add nuw nsw i64 [[TMP1]], 1
77; CHECK-NEXT:    [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP2]], 4
78; CHECK-NEXT:    br i1 [[MIN_ITERS_CHECK]], label [[VEC_EPILOG_SCALAR_PH:%.*]], label [[VECTOR_MAIN_LOOP_ITER_CHECK:%.*]]
79; CHECK:       vector.main.loop.iter.check:
80; CHECK-NEXT:    [[MIN_ITERS_CHECK1:%.*]] = icmp ult i64 [[TMP2]], 16
81; CHECK-NEXT:    br i1 [[MIN_ITERS_CHECK1]], label [[VEC_EPILOG_PH:%.*]], label [[VECTOR_PH:%.*]]
82; CHECK:       vector.ph:
83; CHECK-NEXT:    [[N_MOD_VF:%.*]] = urem i64 [[TMP2]], 16
84; CHECK-NEXT:    [[N_VEC:%.*]] = sub i64 [[TMP2]], [[N_MOD_VF]]
85; CHECK-NEXT:    br label [[VECTOR_BODY:%.*]]
86; CHECK:       vector.body:
87; CHECK-NEXT:    [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
88; CHECK-NEXT:    [[VEC_PHI:%.*]] = phi <4 x float> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP119:%.*]], [[VECTOR_BODY]] ]
89; CHECK-NEXT:    [[VEC_PHI2:%.*]] = phi <4 x float> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP120:%.*]], [[VECTOR_BODY]] ]
90; CHECK-NEXT:    [[VEC_PHI3:%.*]] = phi <4 x float> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP121:%.*]], [[VECTOR_BODY]] ]
91; CHECK-NEXT:    [[VEC_PHI4:%.*]] = phi <4 x float> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP122:%.*]], [[VECTOR_BODY]] ]
92; CHECK-NEXT:    [[OFFSET_IDX:%.*]] = mul i64 [[INDEX]], 32
93; CHECK-NEXT:    [[TMP3:%.*]] = add i64 [[OFFSET_IDX]], 0
94; CHECK-NEXT:    [[TMP4:%.*]] = add i64 [[OFFSET_IDX]], 32
95; CHECK-NEXT:    [[TMP5:%.*]] = add i64 [[OFFSET_IDX]], 64
96; CHECK-NEXT:    [[TMP6:%.*]] = add i64 [[OFFSET_IDX]], 96
97; CHECK-NEXT:    [[TMP7:%.*]] = add i64 [[OFFSET_IDX]], 128
98; CHECK-NEXT:    [[TMP8:%.*]] = add i64 [[OFFSET_IDX]], 160
99; CHECK-NEXT:    [[TMP9:%.*]] = add i64 [[OFFSET_IDX]], 192
100; CHECK-NEXT:    [[TMP10:%.*]] = add i64 [[OFFSET_IDX]], 224
101; CHECK-NEXT:    [[TMP11:%.*]] = add i64 [[OFFSET_IDX]], 256
102; CHECK-NEXT:    [[TMP12:%.*]] = add i64 [[OFFSET_IDX]], 288
103; CHECK-NEXT:    [[TMP13:%.*]] = add i64 [[OFFSET_IDX]], 320
104; CHECK-NEXT:    [[TMP14:%.*]] = add i64 [[OFFSET_IDX]], 352
105; CHECK-NEXT:    [[TMP15:%.*]] = add i64 [[OFFSET_IDX]], 384
106; CHECK-NEXT:    [[TMP16:%.*]] = add i64 [[OFFSET_IDX]], 416
107; CHECK-NEXT:    [[TMP17:%.*]] = add i64 [[OFFSET_IDX]], 448
108; CHECK-NEXT:    [[TMP18:%.*]] = add i64 [[OFFSET_IDX]], 480
109; CHECK-NEXT:    [[TMP19:%.*]] = getelementptr inbounds float, ptr [[A:%.*]], i64 [[TMP3]]
110; CHECK-NEXT:    [[TMP20:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[TMP4]]
111; CHECK-NEXT:    [[TMP21:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[TMP5]]
112; CHECK-NEXT:    [[TMP22:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[TMP6]]
113; CHECK-NEXT:    [[TMP23:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[TMP7]]
114; CHECK-NEXT:    [[TMP24:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[TMP8]]
115; CHECK-NEXT:    [[TMP25:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[TMP9]]
116; CHECK-NEXT:    [[TMP26:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[TMP10]]
117; CHECK-NEXT:    [[TMP27:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[TMP11]]
118; CHECK-NEXT:    [[TMP28:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[TMP12]]
119; CHECK-NEXT:    [[TMP29:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[TMP13]]
120; CHECK-NEXT:    [[TMP30:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[TMP14]]
121; CHECK-NEXT:    [[TMP31:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[TMP15]]
122; CHECK-NEXT:    [[TMP32:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[TMP16]]
123; CHECK-NEXT:    [[TMP33:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[TMP17]]
124; CHECK-NEXT:    [[TMP34:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[TMP18]]
125; CHECK-NEXT:    [[TMP35:%.*]] = load float, ptr [[TMP19]], align 4
126; CHECK-NEXT:    [[TMP36:%.*]] = load float, ptr [[TMP20]], align 4
127; CHECK-NEXT:    [[TMP37:%.*]] = load float, ptr [[TMP21]], align 4
128; CHECK-NEXT:    [[TMP38:%.*]] = load float, ptr [[TMP22]], align 4
129; CHECK-NEXT:    [[TMP39:%.*]] = insertelement <4 x float> poison, float [[TMP35]], i32 0
130; CHECK-NEXT:    [[TMP40:%.*]] = insertelement <4 x float> [[TMP39]], float [[TMP36]], i32 1
131; CHECK-NEXT:    [[TMP41:%.*]] = insertelement <4 x float> [[TMP40]], float [[TMP37]], i32 2
132; CHECK-NEXT:    [[TMP42:%.*]] = insertelement <4 x float> [[TMP41]], float [[TMP38]], i32 3
133; CHECK-NEXT:    [[TMP43:%.*]] = load float, ptr [[TMP23]], align 4
134; CHECK-NEXT:    [[TMP44:%.*]] = load float, ptr [[TMP24]], align 4
135; CHECK-NEXT:    [[TMP45:%.*]] = load float, ptr [[TMP25]], align 4
136; CHECK-NEXT:    [[TMP46:%.*]] = load float, ptr [[TMP26]], align 4
137; CHECK-NEXT:    [[TMP47:%.*]] = insertelement <4 x float> poison, float [[TMP43]], i32 0
138; CHECK-NEXT:    [[TMP48:%.*]] = insertelement <4 x float> [[TMP47]], float [[TMP44]], i32 1
139; CHECK-NEXT:    [[TMP49:%.*]] = insertelement <4 x float> [[TMP48]], float [[TMP45]], i32 2
140; CHECK-NEXT:    [[TMP50:%.*]] = insertelement <4 x float> [[TMP49]], float [[TMP46]], i32 3
141; CHECK-NEXT:    [[TMP51:%.*]] = load float, ptr [[TMP27]], align 4
142; CHECK-NEXT:    [[TMP52:%.*]] = load float, ptr [[TMP28]], align 4
143; CHECK-NEXT:    [[TMP53:%.*]] = load float, ptr [[TMP29]], align 4
144; CHECK-NEXT:    [[TMP54:%.*]] = load float, ptr [[TMP30]], align 4
145; CHECK-NEXT:    [[TMP55:%.*]] = insertelement <4 x float> poison, float [[TMP51]], i32 0
146; CHECK-NEXT:    [[TMP56:%.*]] = insertelement <4 x float> [[TMP55]], float [[TMP52]], i32 1
147; CHECK-NEXT:    [[TMP57:%.*]] = insertelement <4 x float> [[TMP56]], float [[TMP53]], i32 2
148; CHECK-NEXT:    [[TMP58:%.*]] = insertelement <4 x float> [[TMP57]], float [[TMP54]], i32 3
149; CHECK-NEXT:    [[TMP59:%.*]] = load float, ptr [[TMP31]], align 4
150; CHECK-NEXT:    [[TMP60:%.*]] = load float, ptr [[TMP32]], align 4
151; CHECK-NEXT:    [[TMP61:%.*]] = load float, ptr [[TMP33]], align 4
152; CHECK-NEXT:    [[TMP62:%.*]] = load float, ptr [[TMP34]], align 4
153; CHECK-NEXT:    [[TMP63:%.*]] = insertelement <4 x float> poison, float [[TMP59]], i32 0
154; CHECK-NEXT:    [[TMP64:%.*]] = insertelement <4 x float> [[TMP63]], float [[TMP60]], i32 1
155; CHECK-NEXT:    [[TMP65:%.*]] = insertelement <4 x float> [[TMP64]], float [[TMP61]], i32 2
156; CHECK-NEXT:    [[TMP66:%.*]] = insertelement <4 x float> [[TMP65]], float [[TMP62]], i32 3
157; CHECK-NEXT:    [[TMP67:%.*]] = getelementptr inbounds float, ptr [[B:%.*]], i64 [[TMP3]]
158; CHECK-NEXT:    [[TMP68:%.*]] = getelementptr inbounds float, ptr [[B]], i64 [[TMP4]]
159; CHECK-NEXT:    [[TMP69:%.*]] = getelementptr inbounds float, ptr [[B]], i64 [[TMP5]]
160; CHECK-NEXT:    [[TMP70:%.*]] = getelementptr inbounds float, ptr [[B]], i64 [[TMP6]]
161; CHECK-NEXT:    [[TMP71:%.*]] = getelementptr inbounds float, ptr [[B]], i64 [[TMP7]]
162; CHECK-NEXT:    [[TMP72:%.*]] = getelementptr inbounds float, ptr [[B]], i64 [[TMP8]]
163; CHECK-NEXT:    [[TMP73:%.*]] = getelementptr inbounds float, ptr [[B]], i64 [[TMP9]]
164; CHECK-NEXT:    [[TMP74:%.*]] = getelementptr inbounds float, ptr [[B]], i64 [[TMP10]]
165; CHECK-NEXT:    [[TMP75:%.*]] = getelementptr inbounds float, ptr [[B]], i64 [[TMP11]]
166; CHECK-NEXT:    [[TMP76:%.*]] = getelementptr inbounds float, ptr [[B]], i64 [[TMP12]]
167; CHECK-NEXT:    [[TMP77:%.*]] = getelementptr inbounds float, ptr [[B]], i64 [[TMP13]]
168; CHECK-NEXT:    [[TMP78:%.*]] = getelementptr inbounds float, ptr [[B]], i64 [[TMP14]]
169; CHECK-NEXT:    [[TMP79:%.*]] = getelementptr inbounds float, ptr [[B]], i64 [[TMP15]]
170; CHECK-NEXT:    [[TMP80:%.*]] = getelementptr inbounds float, ptr [[B]], i64 [[TMP16]]
171; CHECK-NEXT:    [[TMP81:%.*]] = getelementptr inbounds float, ptr [[B]], i64 [[TMP17]]
172; CHECK-NEXT:    [[TMP82:%.*]] = getelementptr inbounds float, ptr [[B]], i64 [[TMP18]]
173; CHECK-NEXT:    [[TMP83:%.*]] = load float, ptr [[TMP67]], align 4
174; CHECK-NEXT:    [[TMP84:%.*]] = load float, ptr [[TMP68]], align 4
175; CHECK-NEXT:    [[TMP85:%.*]] = load float, ptr [[TMP69]], align 4
176; CHECK-NEXT:    [[TMP86:%.*]] = load float, ptr [[TMP70]], align 4
177; CHECK-NEXT:    [[TMP87:%.*]] = insertelement <4 x float> poison, float [[TMP83]], i32 0
178; CHECK-NEXT:    [[TMP88:%.*]] = insertelement <4 x float> [[TMP87]], float [[TMP84]], i32 1
179; CHECK-NEXT:    [[TMP89:%.*]] = insertelement <4 x float> [[TMP88]], float [[TMP85]], i32 2
180; CHECK-NEXT:    [[TMP90:%.*]] = insertelement <4 x float> [[TMP89]], float [[TMP86]], i32 3
181; CHECK-NEXT:    [[TMP91:%.*]] = load float, ptr [[TMP71]], align 4
182; CHECK-NEXT:    [[TMP92:%.*]] = load float, ptr [[TMP72]], align 4
183; CHECK-NEXT:    [[TMP93:%.*]] = load float, ptr [[TMP73]], align 4
184; CHECK-NEXT:    [[TMP94:%.*]] = load float, ptr [[TMP74]], align 4
185; CHECK-NEXT:    [[TMP95:%.*]] = insertelement <4 x float> poison, float [[TMP91]], i32 0
186; CHECK-NEXT:    [[TMP96:%.*]] = insertelement <4 x float> [[TMP95]], float [[TMP92]], i32 1
187; CHECK-NEXT:    [[TMP97:%.*]] = insertelement <4 x float> [[TMP96]], float [[TMP93]], i32 2
188; CHECK-NEXT:    [[TMP98:%.*]] = insertelement <4 x float> [[TMP97]], float [[TMP94]], i32 3
189; CHECK-NEXT:    [[TMP99:%.*]] = load float, ptr [[TMP75]], align 4
190; CHECK-NEXT:    [[TMP100:%.*]] = load float, ptr [[TMP76]], align 4
191; CHECK-NEXT:    [[TMP101:%.*]] = load float, ptr [[TMP77]], align 4
192; CHECK-NEXT:    [[TMP102:%.*]] = load float, ptr [[TMP78]], align 4
193; CHECK-NEXT:    [[TMP103:%.*]] = insertelement <4 x float> poison, float [[TMP99]], i32 0
194; CHECK-NEXT:    [[TMP104:%.*]] = insertelement <4 x float> [[TMP103]], float [[TMP100]], i32 1
195; CHECK-NEXT:    [[TMP105:%.*]] = insertelement <4 x float> [[TMP104]], float [[TMP101]], i32 2
196; CHECK-NEXT:    [[TMP106:%.*]] = insertelement <4 x float> [[TMP105]], float [[TMP102]], i32 3
197; CHECK-NEXT:    [[TMP107:%.*]] = load float, ptr [[TMP79]], align 4
198; CHECK-NEXT:    [[TMP108:%.*]] = load float, ptr [[TMP80]], align 4
199; CHECK-NEXT:    [[TMP109:%.*]] = load float, ptr [[TMP81]], align 4
200; CHECK-NEXT:    [[TMP110:%.*]] = load float, ptr [[TMP82]], align 4
201; CHECK-NEXT:    [[TMP111:%.*]] = insertelement <4 x float> poison, float [[TMP107]], i32 0
202; CHECK-NEXT:    [[TMP112:%.*]] = insertelement <4 x float> [[TMP111]], float [[TMP108]], i32 1
203; CHECK-NEXT:    [[TMP113:%.*]] = insertelement <4 x float> [[TMP112]], float [[TMP109]], i32 2
204; CHECK-NEXT:    [[TMP114:%.*]] = insertelement <4 x float> [[TMP113]], float [[TMP110]], i32 3
205; CHECK-NEXT:    [[TMP115:%.*]] = fadd fast <4 x float> [[TMP42]], [[VEC_PHI]]
206; CHECK-NEXT:    [[TMP116:%.*]] = fadd fast <4 x float> [[TMP50]], [[VEC_PHI2]]
207; CHECK-NEXT:    [[TMP117:%.*]] = fadd fast <4 x float> [[TMP58]], [[VEC_PHI3]]
208; CHECK-NEXT:    [[TMP118:%.*]] = fadd fast <4 x float> [[TMP66]], [[VEC_PHI4]]
209; CHECK-NEXT:    [[TMP119]] = fadd fast <4 x float> [[TMP115]], [[TMP90]]
210; CHECK-NEXT:    [[TMP120]] = fadd fast <4 x float> [[TMP116]], [[TMP98]]
211; CHECK-NEXT:    [[TMP121]] = fadd fast <4 x float> [[TMP117]], [[TMP106]]
212; CHECK-NEXT:    [[TMP122]] = fadd fast <4 x float> [[TMP118]], [[TMP114]]
213; CHECK-NEXT:    [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16
214; CHECK-NEXT:    [[TMP123:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
215; CHECK-NEXT:    br i1 [[TMP123]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
216; CHECK:       middle.block:
217; CHECK-NEXT:    [[BIN_RDX:%.*]] = fadd fast <4 x float> [[TMP120]], [[TMP119]]
218; CHECK-NEXT:    [[BIN_RDX5:%.*]] = fadd fast <4 x float> [[TMP121]], [[BIN_RDX]]
219; CHECK-NEXT:    [[BIN_RDX6:%.*]] = fadd fast <4 x float> [[TMP122]], [[BIN_RDX5]]
220; CHECK-NEXT:    [[TMP124:%.*]] = call fast float @llvm.vector.reduce.fadd.v4f32(float 0.000000e+00, <4 x float> [[BIN_RDX6]])
221; CHECK-NEXT:    [[CMP_N:%.*]] = icmp eq i64 [[TMP2]], [[N_VEC]]
222; CHECK-NEXT:    br i1 [[CMP_N]], label [[LOOPEXIT:%.*]], label [[VEC_EPILOG_ITER_CHECK:%.*]]
223; CHECK:       vec.epilog.iter.check:
224; CHECK-NEXT:    [[IND_END9:%.*]] = mul i64 [[N_VEC]], 32
225; CHECK-NEXT:    [[N_VEC_REMAINING:%.*]] = sub i64 [[TMP2]], [[N_VEC]]
226; CHECK-NEXT:    [[MIN_EPILOG_ITERS_CHECK:%.*]] = icmp ult i64 [[N_VEC_REMAINING]], 4
227; CHECK-NEXT:    br i1 [[MIN_EPILOG_ITERS_CHECK]], label [[VEC_EPILOG_SCALAR_PH]], label [[VEC_EPILOG_PH]]
228; CHECK:       vec.epilog.ph:
229; CHECK-NEXT:    [[VEC_EPILOG_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], [[VEC_EPILOG_ITER_CHECK]] ], [ 0, [[VECTOR_MAIN_LOOP_ITER_CHECK]] ]
230; CHECK-NEXT:    [[BC_MERGE_RDX:%.*]] = phi float [ [[TMP124]], [[VEC_EPILOG_ITER_CHECK]] ], [ 0.000000e+00, [[VECTOR_MAIN_LOOP_ITER_CHECK]] ]
231; CHECK-NEXT:    [[N_MOD_VF7:%.*]] = urem i64 [[TMP2]], 4
232; CHECK-NEXT:    [[N_VEC8:%.*]] = sub i64 [[TMP2]], [[N_MOD_VF7]]
233; CHECK-NEXT:    [[IND_END:%.*]] = mul i64 [[N_VEC8]], 32
234; CHECK-NEXT:    [[TMP125:%.*]] = insertelement <4 x float> zeroinitializer, float [[BC_MERGE_RDX]], i32 0
235; CHECK-NEXT:    br label [[VEC_EPILOG_VECTOR_BODY:%.*]]
236; CHECK:       vec.epilog.vector.body:
237; CHECK-NEXT:    [[INDEX10:%.*]] = phi i64 [ [[VEC_EPILOG_RESUME_VAL]], [[VEC_EPILOG_PH]] ], [ [[INDEX_NEXT13:%.*]], [[VEC_EPILOG_VECTOR_BODY]] ]
238; CHECK-NEXT:    [[VEC_PHI11:%.*]] = phi <4 x float> [ [[TMP125]], [[VEC_EPILOG_PH]] ], [ [[TMP155:%.*]], [[VEC_EPILOG_VECTOR_BODY]] ]
239; CHECK-NEXT:    [[OFFSET_IDX12:%.*]] = mul i64 [[INDEX10]], 32
240; CHECK-NEXT:    [[TMP126:%.*]] = add i64 [[OFFSET_IDX12]], 0
241; CHECK-NEXT:    [[TMP127:%.*]] = add i64 [[OFFSET_IDX12]], 32
242; CHECK-NEXT:    [[TMP128:%.*]] = add i64 [[OFFSET_IDX12]], 64
243; CHECK-NEXT:    [[TMP129:%.*]] = add i64 [[OFFSET_IDX12]], 96
244; CHECK-NEXT:    [[TMP130:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[TMP126]]
245; CHECK-NEXT:    [[TMP131:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[TMP127]]
246; CHECK-NEXT:    [[TMP132:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[TMP128]]
247; CHECK-NEXT:    [[TMP133:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[TMP129]]
248; CHECK-NEXT:    [[TMP134:%.*]] = load float, ptr [[TMP130]], align 4
249; CHECK-NEXT:    [[TMP135:%.*]] = load float, ptr [[TMP131]], align 4
250; CHECK-NEXT:    [[TMP136:%.*]] = load float, ptr [[TMP132]], align 4
251; CHECK-NEXT:    [[TMP137:%.*]] = load float, ptr [[TMP133]], align 4
252; CHECK-NEXT:    [[TMP138:%.*]] = insertelement <4 x float> poison, float [[TMP134]], i32 0
253; CHECK-NEXT:    [[TMP139:%.*]] = insertelement <4 x float> [[TMP138]], float [[TMP135]], i32 1
254; CHECK-NEXT:    [[TMP140:%.*]] = insertelement <4 x float> [[TMP139]], float [[TMP136]], i32 2
255; CHECK-NEXT:    [[TMP141:%.*]] = insertelement <4 x float> [[TMP140]], float [[TMP137]], i32 3
256; CHECK-NEXT:    [[TMP142:%.*]] = getelementptr inbounds float, ptr [[B]], i64 [[TMP126]]
257; CHECK-NEXT:    [[TMP143:%.*]] = getelementptr inbounds float, ptr [[B]], i64 [[TMP127]]
258; CHECK-NEXT:    [[TMP144:%.*]] = getelementptr inbounds float, ptr [[B]], i64 [[TMP128]]
259; CHECK-NEXT:    [[TMP145:%.*]] = getelementptr inbounds float, ptr [[B]], i64 [[TMP129]]
260; CHECK-NEXT:    [[TMP146:%.*]] = load float, ptr [[TMP142]], align 4
261; CHECK-NEXT:    [[TMP147:%.*]] = load float, ptr [[TMP143]], align 4
262; CHECK-NEXT:    [[TMP148:%.*]] = load float, ptr [[TMP144]], align 4
263; CHECK-NEXT:    [[TMP149:%.*]] = load float, ptr [[TMP145]], align 4
264; CHECK-NEXT:    [[TMP150:%.*]] = insertelement <4 x float> poison, float [[TMP146]], i32 0
265; CHECK-NEXT:    [[TMP151:%.*]] = insertelement <4 x float> [[TMP150]], float [[TMP147]], i32 1
266; CHECK-NEXT:    [[TMP152:%.*]] = insertelement <4 x float> [[TMP151]], float [[TMP148]], i32 2
267; CHECK-NEXT:    [[TMP153:%.*]] = insertelement <4 x float> [[TMP152]], float [[TMP149]], i32 3
268; CHECK-NEXT:    [[TMP154:%.*]] = fadd fast <4 x float> [[TMP141]], [[VEC_PHI11]]
269; CHECK-NEXT:    [[TMP155]] = fadd fast <4 x float> [[TMP154]], [[TMP153]]
270; CHECK-NEXT:    [[INDEX_NEXT13]] = add nuw i64 [[INDEX10]], 4
271; CHECK-NEXT:    [[TMP156:%.*]] = icmp eq i64 [[INDEX_NEXT13]], [[N_VEC8]]
272; CHECK-NEXT:    br i1 [[TMP156]], label [[VEC_EPILOG_MIDDLE_BLOCK:%.*]], label [[VEC_EPILOG_VECTOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]
273; CHECK:       vec.epilog.middle.block:
274; CHECK-NEXT:    [[TMP157:%.*]] = call fast float @llvm.vector.reduce.fadd.v4f32(float 0.000000e+00, <4 x float> [[TMP155]])
275; CHECK-NEXT:    [[CMP_N14:%.*]] = icmp eq i64 [[TMP2]], [[N_VEC8]]
276; CHECK-NEXT:    br i1 [[CMP_N14]], label [[LOOPEXIT]], label [[VEC_EPILOG_SCALAR_PH]]
277; CHECK:       vec.epilog.scalar.ph:
278; CHECK-NEXT:    [[BC_RESUME_VAL:%.*]] = phi i64 [ [[IND_END]], [[VEC_EPILOG_MIDDLE_BLOCK]] ], [ 0, [[ITER_CHECK]] ], [ [[IND_END9]], [[VEC_EPILOG_ITER_CHECK]] ]
279; CHECK-NEXT:    [[BC_MERGE_RDX15:%.*]] = phi float [ [[TMP157]], [[VEC_EPILOG_MIDDLE_BLOCK]] ], [ 0.000000e+00, [[ITER_CHECK]] ], [ [[TMP124]], [[VEC_EPILOG_ITER_CHECK]] ]
280; CHECK-NEXT:    br label [[FOR:%.*]]
281; CHECK:       for:
282; CHECK-NEXT:    [[INDVARS_IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[VEC_EPILOG_SCALAR_PH]] ], [ [[INDVARS_IV_NEXT:%.*]], [[FOR]] ]
283; CHECK-NEXT:    [[S_02:%.*]] = phi float [ [[BC_MERGE_RDX15]], [[VEC_EPILOG_SCALAR_PH]] ], [ [[ADD4:%.*]], [[FOR]] ]
284; CHECK-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[INDVARS_IV]]
285; CHECK-NEXT:    [[T1:%.*]] = load float, ptr [[ARRAYIDX]], align 4
286; CHECK-NEXT:    [[ARRAYIDX3:%.*]] = getelementptr inbounds float, ptr [[B]], i64 [[INDVARS_IV]]
287; CHECK-NEXT:    [[T2:%.*]] = load float, ptr [[ARRAYIDX3]], align 4
288; CHECK-NEXT:    [[ADD:%.*]] = fadd fast float [[T1]], [[S_02]]
289; CHECK-NEXT:    [[ADD4]] = fadd fast float [[ADD]], [[T2]]
290; CHECK-NEXT:    [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 32
291; CHECK-NEXT:    [[CMP1:%.*]] = icmp slt i64 [[INDVARS_IV_NEXT]], [[T0]]
292; CHECK-NEXT:    br i1 [[CMP1]], label [[FOR]], label [[LOOPEXIT]], !llvm.loop [[LOOP4:![0-9]+]]
293; CHECK:       loopexit:
294; CHECK-NEXT:    [[ADD4_LCSSA:%.*]] = phi float [ [[ADD4]], [[FOR]] ], [ [[TMP124]], [[MIDDLE_BLOCK]] ], [ [[TMP157]], [[VEC_EPILOG_MIDDLE_BLOCK]] ]
295; CHECK-NEXT:    br label [[FOR_END]]
296; CHECK:       for.end:
297; CHECK-NEXT:    [[S_0_LCSSA:%.*]] = phi float [ 0.000000e+00, [[ENTRY:%.*]] ], [ [[ADD4_LCSSA]], [[LOOPEXIT]] ]
298; CHECK-NEXT:    ret float [[S_0_LCSSA]]
299;
300entry:
301  %cmp = icmp sgt i32 %n, 0
302  br i1 %cmp, label %preheader, label %for.end
303
304preheader:
305  %t0 = sext i32 %n to i64
306  br label %for
307
308for:
309  %indvars.iv = phi i64 [ 0, %preheader ], [ %indvars.iv.next, %for ]
310  %s.02 = phi float [ 0.0, %preheader ], [ %add4, %for ]
311  %arrayidx = getelementptr inbounds float, ptr %a, i64 %indvars.iv
312  %t1 = load float, ptr %arrayidx, align 4
313  %arrayidx3 = getelementptr inbounds float, ptr %b, i64 %indvars.iv
314  %t2 = load float, ptr %arrayidx3, align 4
315  %add = fadd fast float %t1, %s.02
316  %add4 = fadd fast float %add, %t2
317  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 32
318  %cmp1 = icmp slt i64 %indvars.iv.next, %t0
319  br i1 %cmp1, label %for, label %loopexit
320
321loopexit:
322  %add4.lcssa = phi float [ %add4, %for ]
323  br label %for.end
324
325for.end:
326  %s.0.lcssa = phi float [ 0.0, %entry ], [ %add4.lcssa, %loopexit ]
327  ret float %s.0.lcssa
328}
329
330define void @multi_exit(ptr %dst, ptr %src.1, ptr %src.2, i64 %A, i64 %B) #0 {
331; CHECK-LABEL: @multi_exit(
332; CHECK-NEXT:  entry:
333; CHECK-NEXT:    [[UMAX6:%.*]] = call i64 @llvm.umax.i64(i64 [[B:%.*]], i64 1)
334; CHECK-NEXT:    [[TMP0:%.*]] = add i64 [[UMAX6]], -1
335; CHECK-NEXT:    [[TMP1:%.*]] = freeze i64 [[TMP0]]
336; CHECK-NEXT:    [[UMIN7:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP1]], i64 [[A:%.*]])
337; CHECK-NEXT:    [[TMP2:%.*]] = add nuw i64 [[UMIN7]], 1
338; CHECK-NEXT:    [[MIN_ITERS_CHECK:%.*]] = icmp ule i64 [[TMP2]], 28
339; CHECK-NEXT:    br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_SCEVCHECK:%.*]]
340; CHECK:       vector.scevcheck:
341; CHECK-NEXT:    [[UMAX:%.*]] = call i64 @llvm.umax.i64(i64 [[B]], i64 1)
342; CHECK-NEXT:    [[TMP3:%.*]] = add i64 [[UMAX]], -1
343; CHECK-NEXT:    [[TMP4:%.*]] = freeze i64 [[TMP3]]
344; CHECK-NEXT:    [[UMIN:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP4]], i64 [[A]])
345; CHECK-NEXT:    [[TMP6:%.*]] = trunc i64 [[UMIN]] to i32
346; CHECK-NEXT:    [[TMP7:%.*]] = add i32 1, [[TMP6]]
347; CHECK-NEXT:    [[TMP8:%.*]] = icmp ult i32 [[TMP7]], 1
348; CHECK-NEXT:    [[TMP9:%.*]] = icmp ugt i64 [[UMIN]], 4294967295
349; CHECK-NEXT:    [[TMP10:%.*]] = or i1 [[TMP8]], [[TMP9]]
350; CHECK-NEXT:    br i1 [[TMP10]], label [[SCALAR_PH]], label [[VECTOR_MEMCHECK:%.*]]
351; CHECK:       vector.memcheck:
352; CHECK-NEXT:    [[SCEVGEP:%.*]] = getelementptr i8, ptr [[DST:%.*]], i64 1
353; CHECK-NEXT:    [[SCEVGEP1:%.*]] = getelementptr i8, ptr [[SRC_1:%.*]], i64 8
354; CHECK-NEXT:    [[SCEVGEP2:%.*]] = getelementptr i8, ptr [[SRC_2:%.*]], i64 8
355; CHECK-NEXT:    [[BOUND0:%.*]] = icmp ult ptr [[DST]], [[SCEVGEP1]]
356; CHECK-NEXT:    [[BOUND1:%.*]] = icmp ult ptr [[SRC_1]], [[SCEVGEP]]
357; CHECK-NEXT:    [[FOUND_CONFLICT:%.*]] = and i1 [[BOUND0]], [[BOUND1]]
358; CHECK-NEXT:    [[BOUND03:%.*]] = icmp ult ptr [[DST]], [[SCEVGEP2]]
359; CHECK-NEXT:    [[BOUND14:%.*]] = icmp ult ptr [[SRC_2]], [[SCEVGEP]]
360; CHECK-NEXT:    [[FOUND_CONFLICT5:%.*]] = and i1 [[BOUND03]], [[BOUND14]]
361; CHECK-NEXT:    [[CONFLICT_RDX:%.*]] = or i1 [[FOUND_CONFLICT]], [[FOUND_CONFLICT5]]
362; CHECK-NEXT:    br i1 [[CONFLICT_RDX]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]]
363; CHECK:       vector.ph:
364; CHECK-NEXT:    [[N_MOD_VF:%.*]] = urem i64 [[TMP2]], 4
365; CHECK-NEXT:    [[TMP11:%.*]] = icmp eq i64 [[N_MOD_VF]], 0
366; CHECK-NEXT:    [[TMP12:%.*]] = select i1 [[TMP11]], i64 4, i64 [[N_MOD_VF]]
367; CHECK-NEXT:    [[N_VEC:%.*]] = sub i64 [[TMP2]], [[TMP12]]
368; CHECK-NEXT:    [[IND_END:%.*]] = trunc i64 [[N_VEC]] to i32
369; CHECK-NEXT:    br label [[VECTOR_BODY:%.*]]
370; CHECK:       vector.body:
371; CHECK-NEXT:    [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
372; CHECK-NEXT:    [[TMP13:%.*]] = load i64, ptr [[SRC_1]], align 8, !alias.scope [[META5:![0-9]+]]
373; CHECK-NEXT:    [[BROADCAST_SPLATINSERT:%.*]] = insertelement <2 x i64> poison, i64 [[TMP13]], i64 0
374; CHECK-NEXT:    [[BROADCAST_SPLAT:%.*]] = shufflevector <2 x i64> [[BROADCAST_SPLATINSERT]], <2 x i64> poison, <2 x i32> zeroinitializer
375; CHECK-NEXT:    [[TMP14:%.*]] = load i64, ptr [[SRC_2]], align 8, !alias.scope [[META8:![0-9]+]]
376; CHECK-NEXT:    [[BROADCAST_SPLATINSERT9:%.*]] = insertelement <2 x i64> poison, i64 [[TMP14]], i64 0
377; CHECK-NEXT:    [[BROADCAST_SPLAT10:%.*]] = shufflevector <2 x i64> [[BROADCAST_SPLATINSERT9]], <2 x i64> poison, <2 x i32> zeroinitializer
378; CHECK-NEXT:    [[TMP15:%.*]] = icmp eq <2 x i64> [[BROADCAST_SPLAT]], zeroinitializer
379; CHECK-NEXT:    [[TMP16:%.*]] = icmp ne <2 x i64> [[BROADCAST_SPLAT10]], zeroinitializer
380; CHECK-NEXT:    [[TMP17:%.*]] = and <2 x i1> [[TMP16]], [[TMP15]]
381; CHECK-NEXT:    [[TMP18:%.*]] = zext <2 x i1> [[TMP17]] to <2 x i8>
382; CHECK-NEXT:    [[TMP19:%.*]] = extractelement <2 x i8> [[TMP18]], i32 1
383; CHECK-NEXT:    store i8 [[TMP19]], ptr [[DST]], align 1, !alias.scope [[META10:![0-9]+]], !noalias [[META12:![0-9]+]]
384; CHECK-NEXT:    [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
385; CHECK-NEXT:    [[TMP20:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
386; CHECK-NEXT:    br i1 [[TMP20]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP13:![0-9]+]]
387; CHECK:       middle.block:
388; CHECK-NEXT:    br label [[SCALAR_PH]]
389; CHECK:       scalar.ph:
390; CHECK-NEXT:    [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], [[MIDDLE_BLOCK]] ], [ 0, [[VECTOR_MEMCHECK]] ], [ 0, [[VECTOR_SCEVCHECK]] ], [ 0, [[ENTRY:%.*]] ]
391; CHECK-NEXT:    [[BC_RESUME_VAL8:%.*]] = phi i32 [ [[IND_END]], [[MIDDLE_BLOCK]] ], [ 0, [[VECTOR_MEMCHECK]] ], [ 0, [[VECTOR_SCEVCHECK]] ], [ 0, [[ENTRY]] ]
392; CHECK-NEXT:    br label [[LOOP:%.*]]
393; CHECK:       loop:
394; CHECK-NEXT:    [[IV_1_WIDE:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_1_NEXT_WIDE:%.*]], [[LOOP_LATCH:%.*]] ]
395; CHECK-NEXT:    [[IV_1:%.*]] = phi i32 [ [[BC_RESUME_VAL8]], [[SCALAR_PH]] ], [ [[IV_1_NEXT:%.*]], [[LOOP_LATCH]] ]
396; CHECK-NEXT:    [[EC_1:%.*]] = icmp ult i64 [[IV_1_WIDE]], [[A]]
397; CHECK-NEXT:    br i1 [[EC_1]], label [[LOOP_LATCH]], label [[EXIT:%.*]]
398; CHECK:       loop.latch:
399; CHECK-NEXT:    [[L_1:%.*]] = load i64, ptr [[SRC_1]], align 8
400; CHECK-NEXT:    [[L_2:%.*]] = load i64, ptr [[SRC_2]], align 8
401; CHECK-NEXT:    [[CMP55_US:%.*]] = icmp eq i64 [[L_1]], 0
402; CHECK-NEXT:    [[CMP_I_US:%.*]] = icmp ne i64 [[L_2]], 0
403; CHECK-NEXT:    [[AND:%.*]] = and i1 [[CMP_I_US]], [[CMP55_US]]
404; CHECK-NEXT:    [[EXT:%.*]] = zext i1 [[AND]] to i8
405; CHECK-NEXT:    store i8 [[EXT]], ptr [[DST]], align 1
406; CHECK-NEXT:    [[IV_1_NEXT]] = add i32 [[IV_1]], 1
407; CHECK-NEXT:    [[IV_1_NEXT_WIDE]] = zext i32 [[IV_1_NEXT]] to i64
408; CHECK-NEXT:    [[EC_2:%.*]] = icmp ult i64 [[IV_1_NEXT_WIDE]], [[B]]
409; CHECK-NEXT:    br i1 [[EC_2]], label [[LOOP]], label [[EXIT]], !llvm.loop [[LOOP14:![0-9]+]]
410; CHECK:       exit:
411; CHECK-NEXT:    ret void
412;
413entry:
414  br label %loop
415
416loop:
417  %iv.1.wide = phi i64 [ 0, %entry ], [ %iv.1.next.wide, %loop.latch ]
418  %iv.1 = phi i32 [ 0, %entry ], [ %iv.1.next, %loop.latch ]
419  %ec.1 = icmp ult i64 %iv.1.wide, %A
420  br i1 %ec.1, label %loop.latch, label %exit
421
422loop.latch:
423  %l.1 = load i64, ptr %src.1, align 8
424  %l.2 = load i64, ptr %src.2, align 8
425  %cmp55.us = icmp eq i64 %l.1, 0
426  %cmp.i.us = icmp ne i64 %l.2, 0
427  %and = and i1 %cmp.i.us, %cmp55.us
428  %ext = zext i1 %and to i8
429  store i8 %ext, ptr %dst, align 1
430  %iv.1.next = add i32 %iv.1, 1
431  %iv.1.next.wide = zext i32 %iv.1.next to i64
432  %ec.2 = icmp ult i64 %iv.1.next.wide, %B
433  br i1 %ec.2, label %loop, label %exit
434
435exit:
436  ret void
437}
438
439define i1 @any_of_cost(ptr %start, ptr %end) #0 {
440; CHECK-LABEL: @any_of_cost(
441; CHECK-NEXT:  entry:
442; CHECK-NEXT:    [[START2:%.*]] = ptrtoint ptr [[START:%.*]] to i64
443; CHECK-NEXT:    [[END1:%.*]] = ptrtoint ptr [[END:%.*]] to i64
444; CHECK-NEXT:    [[TMP0:%.*]] = sub i64 [[END1]], [[START2]]
445; CHECK-NEXT:    [[TMP1:%.*]] = udiv i64 [[TMP0]], 40
446; CHECK-NEXT:    [[TMP2:%.*]] = add nuw nsw i64 [[TMP1]], 1
447; CHECK-NEXT:    [[MIN_ITERS_CHECK:%.*]] = icmp ule i64 [[TMP2]], 4
448; CHECK-NEXT:    br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
449; CHECK:       vector.ph:
450; CHECK-NEXT:    [[N_MOD_VF:%.*]] = urem i64 [[TMP2]], 4
451; CHECK-NEXT:    [[TMP3:%.*]] = icmp eq i64 [[N_MOD_VF]], 0
452; CHECK-NEXT:    [[TMP4:%.*]] = select i1 [[TMP3]], i64 4, i64 [[N_MOD_VF]]
453; CHECK-NEXT:    [[N_VEC:%.*]] = sub i64 [[TMP2]], [[TMP4]]
454; CHECK-NEXT:    [[TMP5:%.*]] = mul i64 [[N_VEC]], 40
455; CHECK-NEXT:    [[IND_END:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP5]]
456; CHECK-NEXT:    br label [[VECTOR_BODY:%.*]]
457; CHECK:       vector.body:
458; CHECK-NEXT:    [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
459; CHECK-NEXT:    [[VEC_PHI:%.*]] = phi <2 x i1> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP26:%.*]], [[VECTOR_BODY]] ]
460; CHECK-NEXT:    [[VEC_PHI3:%.*]] = phi <2 x i1> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP27:%.*]], [[VECTOR_BODY]] ]
461; CHECK-NEXT:    [[OFFSET_IDX:%.*]] = mul i64 [[INDEX]], 40
462; CHECK-NEXT:    [[TMP6:%.*]] = add i64 [[OFFSET_IDX]], 0
463; CHECK-NEXT:    [[TMP7:%.*]] = add i64 [[OFFSET_IDX]], 40
464; CHECK-NEXT:    [[TMP8:%.*]] = add i64 [[OFFSET_IDX]], 80
465; CHECK-NEXT:    [[TMP9:%.*]] = add i64 [[OFFSET_IDX]], 120
466; CHECK-NEXT:    [[NEXT_GEP:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP6]]
467; CHECK-NEXT:    [[NEXT_GEP4:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP7]]
468; CHECK-NEXT:    [[NEXT_GEP5:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP8]]
469; CHECK-NEXT:    [[NEXT_GEP6:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP9]]
470; CHECK-NEXT:    [[TMP10:%.*]] = getelementptr i8, ptr [[NEXT_GEP]], i64 8
471; CHECK-NEXT:    [[TMP11:%.*]] = getelementptr i8, ptr [[NEXT_GEP4]], i64 8
472; CHECK-NEXT:    [[TMP12:%.*]] = getelementptr i8, ptr [[NEXT_GEP5]], i64 8
473; CHECK-NEXT:    [[TMP13:%.*]] = getelementptr i8, ptr [[NEXT_GEP6]], i64 8
474; CHECK-NEXT:    [[TMP14:%.*]] = load ptr, ptr [[TMP10]], align 8
475; CHECK-NEXT:    [[TMP15:%.*]] = load ptr, ptr [[TMP11]], align 8
476; CHECK-NEXT:    [[TMP16:%.*]] = insertelement <2 x ptr> poison, ptr [[TMP14]], i32 0
477; CHECK-NEXT:    [[TMP17:%.*]] = insertelement <2 x ptr> [[TMP16]], ptr [[TMP15]], i32 1
478; CHECK-NEXT:    [[TMP18:%.*]] = load ptr, ptr [[TMP12]], align 8
479; CHECK-NEXT:    [[TMP19:%.*]] = load ptr, ptr [[TMP13]], align 8
480; CHECK-NEXT:    [[TMP20:%.*]] = insertelement <2 x ptr> poison, ptr [[TMP18]], i32 0
481; CHECK-NEXT:    [[TMP21:%.*]] = insertelement <2 x ptr> [[TMP20]], ptr [[TMP19]], i32 1
482; CHECK-NEXT:    [[TMP22:%.*]] = icmp eq <2 x ptr> [[TMP17]], zeroinitializer
483; CHECK-NEXT:    [[TMP23:%.*]] = icmp eq <2 x ptr> [[TMP21]], zeroinitializer
484; CHECK-NEXT:    [[TMP24:%.*]] = xor <2 x i1> [[TMP22]], splat (i1 true)
485; CHECK-NEXT:    [[TMP25:%.*]] = xor <2 x i1> [[TMP23]], splat (i1 true)
486; CHECK-NEXT:    [[TMP26]] = or <2 x i1> [[VEC_PHI]], [[TMP24]]
487; CHECK-NEXT:    [[TMP27]] = or <2 x i1> [[VEC_PHI3]], [[TMP25]]
488; CHECK-NEXT:    [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
489; CHECK-NEXT:    [[TMP28:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
490; CHECK-NEXT:    br i1 [[TMP28]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP15:![0-9]+]]
491; CHECK:       middle.block:
492; CHECK-NEXT:    [[BIN_RDX:%.*]] = or <2 x i1> [[TMP27]], [[TMP26]]
493; CHECK-NEXT:    [[TMP29:%.*]] = call i1 @llvm.vector.reduce.or.v2i1(<2 x i1> [[BIN_RDX]])
494; CHECK-NEXT:    [[TMP30:%.*]] = freeze i1 [[TMP29]]
495; CHECK-NEXT:    [[RDX_SELECT:%.*]] = select i1 [[TMP30]], i1 false, i1 false
496; CHECK-NEXT:    br label [[SCALAR_PH]]
497; CHECK:       scalar.ph:
498; CHECK-NEXT:    [[BC_MERGE_RDX:%.*]] = phi i1 [ [[RDX_SELECT]], [[MIDDLE_BLOCK]] ], [ false, [[ENTRY:%.*]] ]
499; CHECK-NEXT:    [[BC_RESUME_VAL:%.*]] = phi ptr [ [[IND_END]], [[MIDDLE_BLOCK]] ], [ [[START]], [[ENTRY]] ]
500; CHECK-NEXT:    br label [[LOOP:%.*]]
501; CHECK:       loop:
502; CHECK-NEXT:    [[ANY_OF:%.*]] = phi i1 [ [[BC_MERGE_RDX]], [[SCALAR_PH]] ], [ [[ANY_OF_NEXT:%.*]], [[LOOP]] ]
503; CHECK-NEXT:    [[PTR_IV:%.*]] = phi ptr [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[PTR_IV_NEXT:%.*]], [[LOOP]] ]
504; CHECK-NEXT:    [[GEP:%.*]] = getelementptr i8, ptr [[PTR_IV]], i64 8
505; CHECK-NEXT:    [[L:%.*]] = load ptr, ptr [[GEP]], align 8
506; CHECK-NEXT:    [[CMP13_NOT_NOT:%.*]] = icmp eq ptr [[L]], null
507; CHECK-NEXT:    [[ANY_OF_NEXT]] = select i1 [[CMP13_NOT_NOT]], i1 [[ANY_OF]], i1 false
508; CHECK-NEXT:    [[PTR_IV_NEXT]] = getelementptr inbounds i8, ptr [[PTR_IV]], i64 40
509; CHECK-NEXT:    [[CMP_NOT:%.*]] = icmp eq ptr [[PTR_IV]], [[END]]
510; CHECK-NEXT:    br i1 [[CMP_NOT]], label [[EXIT:%.*]], label [[LOOP]], !llvm.loop [[LOOP16:![0-9]+]]
511; CHECK:       exit:
512; CHECK-NEXT:    [[ANY_OF_NEXT_LCSSA:%.*]] = phi i1 [ [[ANY_OF_NEXT]], [[LOOP]] ]
513; CHECK-NEXT:    ret i1 [[ANY_OF_NEXT_LCSSA]]
514;
515entry:
516  br label %loop
517
518loop:
519  %any.of = phi i1 [ false, %entry ], [ %any.of.next, %loop ]
520  %ptr.iv = phi ptr [ %start, %entry ], [ %ptr.iv.next, %loop ]
521  %gep = getelementptr i8, ptr %ptr.iv, i64 8
522  %l = load ptr, ptr %gep, align 8
523  %cmp13.not.not = icmp eq ptr %l, null
524  %any.of.next = select i1 %cmp13.not.not, i1 %any.of, i1 false
525  %ptr.iv.next = getelementptr inbounds i8, ptr %ptr.iv, i64 40
526  %cmp.not = icmp eq ptr %ptr.iv, %end
527  br i1 %cmp.not, label %exit, label %loop
528
529exit:
530  ret i1 %any.of.next
531}
532
533define i64 @avx512_cond_load_cost(ptr %src, i32 %a, i64 %b, i32 %c, i32 %d) #1 {
534; CHECK-LABEL: @avx512_cond_load_cost(
535; CHECK-NEXT:  entry:
536; CHECK-NEXT:    br label [[LOOP_HEADER:%.*]]
537; CHECK:       loop.header:
538; CHECK-NEXT:    [[IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP_LATCH:%.*]] ]
539; CHECK-NEXT:    [[C_1:%.*]] = icmp slt i32 [[IV]], 0
540; CHECK-NEXT:    br i1 [[C_1]], label [[IF_THEN:%.*]], label [[LOOP_LATCH]]
541; CHECK:       if.then:
542; CHECK-NEXT:    [[TMP0:%.*]] = urem i32 [[A:%.*]], [[C:%.*]]
543; CHECK-NEXT:    [[MUL:%.*]] = sub i32 0, [[TMP0]]
544; CHECK-NEXT:    [[DIV:%.*]] = udiv i32 [[C]], [[D:%.*]]
545; CHECK-NEXT:    [[OR:%.*]] = or i32 [[DIV]], [[MUL]]
546; CHECK-NEXT:    [[EXT:%.*]] = sext i32 [[OR]] to i64
547; CHECK-NEXT:    [[GEP:%.*]] = getelementptr { i64, i64, i64 }, ptr [[SRC:%.*]], i64 [[EXT]], i32 2
548; CHECK-NEXT:    [[L:%.*]] = load i64, ptr [[GEP]], align 8
549; CHECK-NEXT:    [[OR_2:%.*]] = or i64 [[L]], [[B:%.*]]
550; CHECK-NEXT:    br label [[LOOP_LATCH]]
551; CHECK:       loop.latch:
552; CHECK-NEXT:    [[RES:%.*]] = phi i64 [ 0, [[LOOP_HEADER]] ], [ [[OR_2]], [[IF_THEN]] ]
553; CHECK-NEXT:    [[IV_NEXT]] = add i32 [[IV]], 1
554; CHECK-NEXT:    [[EC:%.*]] = icmp ult i32 [[IV]], [[C]]
555; CHECK-NEXT:    br i1 [[EC]], label [[LOOP_HEADER]], label [[EXIT:%.*]]
556; CHECK:       exit:
557; CHECK-NEXT:    [[RES_LCSSA:%.*]] = phi i64 [ [[RES]], [[LOOP_LATCH]] ]
558; CHECK-NEXT:    ret i64 [[RES_LCSSA]]
559;
560entry:
561  br label %loop.header
562
563loop.header:
564  %iv = phi i32 [ 0, %entry ], [ %iv.next, %loop.latch ]
565  %c.1 = icmp slt i32 %iv, 0
566  br i1 %c.1, label %if.then, label %loop.latch
567
568if.then:
569  %1 = urem i32 %a, %c
570  %mul = sub i32 0, %1
571  %div = udiv i32 %c, %d
572  %or = or i32 %div, %mul
573  %ext = sext i32 %or to i64
574  %gep = getelementptr { i64, i64, i64 }, ptr %src, i64 %ext, i32 2
575  %l = load i64, ptr %gep, align 8
576  %or.2 = or i64 %l, %b
577  br label %loop.latch
578
579loop.latch:
580  %res = phi i64 [ 0, %loop.header ], [ %or.2, %if.then ]
581  %iv.next = add i32 %iv, 1
582  %ec = icmp ult i32 %iv, %c
583  br i1 %ec, label %loop.header, label %exit
584
585exit:
586  ret i64 %res
587}
588
589define void @cost_duplicate_recipe_for_sinking(ptr %A, i64 %N) #2 {
590; CHECK-LABEL: @cost_duplicate_recipe_for_sinking(
591; CHECK-NEXT:  iter.check:
592; CHECK-NEXT:    [[TMP0:%.*]] = add i64 [[N:%.*]], 1
593; CHECK-NEXT:    [[MIN_ITERS_CHECK:%.*]] = icmp ule i64 [[TMP0]], 4
594; CHECK-NEXT:    br i1 [[MIN_ITERS_CHECK]], label [[VEC_EPILOG_SCALAR_PH:%.*]], label [[VECTOR_MAIN_LOOP_ITER_CHECK:%.*]]
595; CHECK:       vector.main.loop.iter.check:
596; CHECK-NEXT:    [[MIN_ITERS_CHECK1:%.*]] = icmp ule i64 [[TMP0]], 16
597; CHECK-NEXT:    br i1 [[MIN_ITERS_CHECK1]], label [[VEC_EPILOG_PH:%.*]], label [[VECTOR_PH:%.*]]
598; CHECK:       vector.ph:
599; CHECK-NEXT:    [[N_MOD_VF:%.*]] = urem i64 [[TMP0]], 16
600; CHECK-NEXT:    [[TMP1:%.*]] = icmp eq i64 [[N_MOD_VF]], 0
601; CHECK-NEXT:    [[TMP2:%.*]] = select i1 [[TMP1]], i64 16, i64 [[N_MOD_VF]]
602; CHECK-NEXT:    [[N_VEC:%.*]] = sub i64 [[TMP0]], [[TMP2]]
603; CHECK-NEXT:    br label [[VECTOR_BODY:%.*]]
604; CHECK:       vector.body:
605; CHECK-NEXT:    [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[PRED_STORE_CONTINUE37:%.*]] ]
606; CHECK-NEXT:    [[TMP3:%.*]] = add i64 [[INDEX]], 0
607; CHECK-NEXT:    [[TMP4:%.*]] = add i64 [[INDEX]], 4
608; CHECK-NEXT:    [[TMP5:%.*]] = add i64 [[INDEX]], 8
609; CHECK-NEXT:    [[TMP6:%.*]] = add i64 [[INDEX]], 12
610; CHECK-NEXT:    [[TMP7:%.*]] = shl nsw i64 [[TMP3]], 2
611; CHECK-NEXT:    [[TMP8:%.*]] = shl nsw i64 [[TMP4]], 2
612; CHECK-NEXT:    [[TMP9:%.*]] = shl nsw i64 [[TMP5]], 2
613; CHECK-NEXT:    [[TMP10:%.*]] = shl nsw i64 [[TMP6]], 2
614; CHECK-NEXT:    [[TMP11:%.*]] = getelementptr nusw double, ptr [[A:%.*]], i64 [[TMP7]]
615; CHECK-NEXT:    [[TMP12:%.*]] = getelementptr nusw double, ptr [[A]], i64 [[TMP8]]
616; CHECK-NEXT:    [[TMP13:%.*]] = getelementptr nusw double, ptr [[A]], i64 [[TMP9]]
617; CHECK-NEXT:    [[TMP14:%.*]] = getelementptr nusw double, ptr [[A]], i64 [[TMP10]]
618; CHECK-NEXT:    [[WIDE_VEC:%.*]] = load <16 x double>, ptr [[TMP11]], align 8
619; CHECK-NEXT:    [[STRIDED_VEC:%.*]] = shufflevector <16 x double> [[WIDE_VEC]], <16 x double> poison, <4 x i32> <i32 0, i32 4, i32 8, i32 12>
620; CHECK-NEXT:    [[WIDE_VEC1:%.*]] = load <16 x double>, ptr [[TMP12]], align 8
621; CHECK-NEXT:    [[STRIDED_VEC4:%.*]] = shufflevector <16 x double> [[WIDE_VEC1]], <16 x double> poison, <4 x i32> <i32 0, i32 4, i32 8, i32 12>
622; CHECK-NEXT:    [[WIDE_VEC2:%.*]] = load <16 x double>, ptr [[TMP13]], align 8
623; CHECK-NEXT:    [[STRIDED_VEC5:%.*]] = shufflevector <16 x double> [[WIDE_VEC2]], <16 x double> poison, <4 x i32> <i32 0, i32 4, i32 8, i32 12>
624; CHECK-NEXT:    [[WIDE_VEC3:%.*]] = load <16 x double>, ptr [[TMP14]], align 8
625; CHECK-NEXT:    [[STRIDED_VEC6:%.*]] = shufflevector <16 x double> [[WIDE_VEC3]], <16 x double> poison, <4 x i32> <i32 0, i32 4, i32 8, i32 12>
626; CHECK-NEXT:    [[TMP19:%.*]] = fcmp oeq <4 x double> [[STRIDED_VEC]], zeroinitializer
627; CHECK-NEXT:    [[TMP20:%.*]] = fcmp oeq <4 x double> [[STRIDED_VEC4]], zeroinitializer
628; CHECK-NEXT:    [[TMP21:%.*]] = fcmp oeq <4 x double> [[STRIDED_VEC5]], zeroinitializer
629; CHECK-NEXT:    [[TMP22:%.*]] = fcmp oeq <4 x double> [[STRIDED_VEC6]], zeroinitializer
630; CHECK-NEXT:    [[TMP23:%.*]] = extractelement <4 x i1> [[TMP19]], i32 0
631; CHECK-NEXT:    br i1 [[TMP23]], label [[PRED_STORE_IF:%.*]], label [[PRED_STORE_CONTINUE:%.*]]
632; CHECK:       pred.store.if:
633; CHECK-NEXT:    [[TMP24:%.*]] = shl nsw i64 [[TMP3]], 2
634; CHECK-NEXT:    [[TMP25:%.*]] = getelementptr double, ptr [[A]], i64 [[TMP24]]
635; CHECK-NEXT:    store double 0.000000e+00, ptr [[TMP25]], align 8
636; CHECK-NEXT:    br label [[PRED_STORE_CONTINUE]]
637; CHECK:       pred.store.continue:
638; CHECK-NEXT:    [[TMP26:%.*]] = extractelement <4 x i1> [[TMP19]], i32 1
639; CHECK-NEXT:    br i1 [[TMP26]], label [[PRED_STORE_IF8:%.*]], label [[PRED_STORE_CONTINUE9:%.*]]
640; CHECK:       pred.store.if8:
641; CHECK-NEXT:    [[TMP27:%.*]] = add i64 [[INDEX]], 1
642; CHECK-NEXT:    [[TMP28:%.*]] = shl nsw i64 [[TMP27]], 2
643; CHECK-NEXT:    [[TMP29:%.*]] = getelementptr double, ptr [[A]], i64 [[TMP28]]
644; CHECK-NEXT:    store double 0.000000e+00, ptr [[TMP29]], align 8
645; CHECK-NEXT:    br label [[PRED_STORE_CONTINUE9]]
646; CHECK:       pred.store.continue9:
647; CHECK-NEXT:    [[TMP30:%.*]] = extractelement <4 x i1> [[TMP19]], i32 2
648; CHECK-NEXT:    br i1 [[TMP30]], label [[PRED_STORE_IF10:%.*]], label [[PRED_STORE_CONTINUE11:%.*]]
649; CHECK:       pred.store.if10:
650; CHECK-NEXT:    [[TMP31:%.*]] = add i64 [[INDEX]], 2
651; CHECK-NEXT:    [[TMP32:%.*]] = shl nsw i64 [[TMP31]], 2
652; CHECK-NEXT:    [[TMP33:%.*]] = getelementptr double, ptr [[A]], i64 [[TMP32]]
653; CHECK-NEXT:    store double 0.000000e+00, ptr [[TMP33]], align 8
654; CHECK-NEXT:    br label [[PRED_STORE_CONTINUE11]]
655; CHECK:       pred.store.continue11:
656; CHECK-NEXT:    [[TMP34:%.*]] = extractelement <4 x i1> [[TMP19]], i32 3
657; CHECK-NEXT:    br i1 [[TMP34]], label [[PRED_STORE_IF12:%.*]], label [[PRED_STORE_CONTINUE13:%.*]]
658; CHECK:       pred.store.if12:
659; CHECK-NEXT:    [[TMP35:%.*]] = add i64 [[INDEX]], 3
660; CHECK-NEXT:    [[TMP36:%.*]] = shl nsw i64 [[TMP35]], 2
661; CHECK-NEXT:    [[TMP37:%.*]] = getelementptr double, ptr [[A]], i64 [[TMP36]]
662; CHECK-NEXT:    store double 0.000000e+00, ptr [[TMP37]], align 8
663; CHECK-NEXT:    br label [[PRED_STORE_CONTINUE13]]
664; CHECK:       pred.store.continue13:
665; CHECK-NEXT:    [[TMP38:%.*]] = extractelement <4 x i1> [[TMP20]], i32 0
666; CHECK-NEXT:    br i1 [[TMP38]], label [[PRED_STORE_IF14:%.*]], label [[PRED_STORE_CONTINUE15:%.*]]
667; CHECK:       pred.store.if14:
668; CHECK-NEXT:    [[TMP39:%.*]] = shl nsw i64 [[TMP4]], 2
669; CHECK-NEXT:    [[TMP40:%.*]] = getelementptr double, ptr [[A]], i64 [[TMP39]]
670; CHECK-NEXT:    store double 0.000000e+00, ptr [[TMP40]], align 8
671; CHECK-NEXT:    br label [[PRED_STORE_CONTINUE15]]
672; CHECK:       pred.store.continue15:
673; CHECK-NEXT:    [[TMP41:%.*]] = extractelement <4 x i1> [[TMP20]], i32 1
674; CHECK-NEXT:    br i1 [[TMP41]], label [[PRED_STORE_IF16:%.*]], label [[PRED_STORE_CONTINUE17:%.*]]
675; CHECK:       pred.store.if16:
676; CHECK-NEXT:    [[TMP42:%.*]] = add i64 [[INDEX]], 5
677; CHECK-NEXT:    [[TMP43:%.*]] = shl nsw i64 [[TMP42]], 2
678; CHECK-NEXT:    [[TMP44:%.*]] = getelementptr double, ptr [[A]], i64 [[TMP43]]
679; CHECK-NEXT:    store double 0.000000e+00, ptr [[TMP44]], align 8
680; CHECK-NEXT:    br label [[PRED_STORE_CONTINUE17]]
681; CHECK:       pred.store.continue17:
682; CHECK-NEXT:    [[TMP45:%.*]] = extractelement <4 x i1> [[TMP20]], i32 2
683; CHECK-NEXT:    br i1 [[TMP45]], label [[PRED_STORE_IF18:%.*]], label [[PRED_STORE_CONTINUE19:%.*]]
684; CHECK:       pred.store.if18:
685; CHECK-NEXT:    [[TMP46:%.*]] = add i64 [[INDEX]], 6
686; CHECK-NEXT:    [[TMP47:%.*]] = shl nsw i64 [[TMP46]], 2
687; CHECK-NEXT:    [[TMP48:%.*]] = getelementptr double, ptr [[A]], i64 [[TMP47]]
688; CHECK-NEXT:    store double 0.000000e+00, ptr [[TMP48]], align 8
689; CHECK-NEXT:    br label [[PRED_STORE_CONTINUE19]]
690; CHECK:       pred.store.continue19:
691; CHECK-NEXT:    [[TMP49:%.*]] = extractelement <4 x i1> [[TMP20]], i32 3
692; CHECK-NEXT:    br i1 [[TMP49]], label [[PRED_STORE_IF20:%.*]], label [[PRED_STORE_CONTINUE21:%.*]]
693; CHECK:       pred.store.if20:
694; CHECK-NEXT:    [[TMP50:%.*]] = add i64 [[INDEX]], 7
695; CHECK-NEXT:    [[TMP51:%.*]] = shl nsw i64 [[TMP50]], 2
696; CHECK-NEXT:    [[TMP52:%.*]] = getelementptr double, ptr [[A]], i64 [[TMP51]]
697; CHECK-NEXT:    store double 0.000000e+00, ptr [[TMP52]], align 8
698; CHECK-NEXT:    br label [[PRED_STORE_CONTINUE21]]
699; CHECK:       pred.store.continue21:
700; CHECK-NEXT:    [[TMP53:%.*]] = extractelement <4 x i1> [[TMP21]], i32 0
701; CHECK-NEXT:    br i1 [[TMP53]], label [[PRED_STORE_IF22:%.*]], label [[PRED_STORE_CONTINUE23:%.*]]
702; CHECK:       pred.store.if22:
703; CHECK-NEXT:    [[TMP54:%.*]] = shl nsw i64 [[TMP5]], 2
704; CHECK-NEXT:    [[TMP55:%.*]] = getelementptr double, ptr [[A]], i64 [[TMP54]]
705; CHECK-NEXT:    store double 0.000000e+00, ptr [[TMP55]], align 8
706; CHECK-NEXT:    br label [[PRED_STORE_CONTINUE23]]
707; CHECK:       pred.store.continue23:
708; CHECK-NEXT:    [[TMP56:%.*]] = extractelement <4 x i1> [[TMP21]], i32 1
709; CHECK-NEXT:    br i1 [[TMP56]], label [[PRED_STORE_IF24:%.*]], label [[PRED_STORE_CONTINUE25:%.*]]
710; CHECK:       pred.store.if24:
711; CHECK-NEXT:    [[TMP57:%.*]] = add i64 [[INDEX]], 9
712; CHECK-NEXT:    [[TMP58:%.*]] = shl nsw i64 [[TMP57]], 2
713; CHECK-NEXT:    [[TMP59:%.*]] = getelementptr double, ptr [[A]], i64 [[TMP58]]
714; CHECK-NEXT:    store double 0.000000e+00, ptr [[TMP59]], align 8
715; CHECK-NEXT:    br label [[PRED_STORE_CONTINUE25]]
716; CHECK:       pred.store.continue25:
717; CHECK-NEXT:    [[TMP60:%.*]] = extractelement <4 x i1> [[TMP21]], i32 2
718; CHECK-NEXT:    br i1 [[TMP60]], label [[PRED_STORE_IF26:%.*]], label [[PRED_STORE_CONTINUE27:%.*]]
719; CHECK:       pred.store.if26:
720; CHECK-NEXT:    [[TMP61:%.*]] = add i64 [[INDEX]], 10
721; CHECK-NEXT:    [[TMP62:%.*]] = shl nsw i64 [[TMP61]], 2
722; CHECK-NEXT:    [[TMP63:%.*]] = getelementptr double, ptr [[A]], i64 [[TMP62]]
723; CHECK-NEXT:    store double 0.000000e+00, ptr [[TMP63]], align 8
724; CHECK-NEXT:    br label [[PRED_STORE_CONTINUE27]]
725; CHECK:       pred.store.continue27:
726; CHECK-NEXT:    [[TMP64:%.*]] = extractelement <4 x i1> [[TMP21]], i32 3
727; CHECK-NEXT:    br i1 [[TMP64]], label [[PRED_STORE_IF28:%.*]], label [[PRED_STORE_CONTINUE29:%.*]]
728; CHECK:       pred.store.if28:
729; CHECK-NEXT:    [[TMP65:%.*]] = add i64 [[INDEX]], 11
730; CHECK-NEXT:    [[TMP66:%.*]] = shl nsw i64 [[TMP65]], 2
731; CHECK-NEXT:    [[TMP67:%.*]] = getelementptr double, ptr [[A]], i64 [[TMP66]]
732; CHECK-NEXT:    store double 0.000000e+00, ptr [[TMP67]], align 8
733; CHECK-NEXT:    br label [[PRED_STORE_CONTINUE29]]
734; CHECK:       pred.store.continue29:
735; CHECK-NEXT:    [[TMP68:%.*]] = extractelement <4 x i1> [[TMP22]], i32 0
736; CHECK-NEXT:    br i1 [[TMP68]], label [[PRED_STORE_IF30:%.*]], label [[PRED_STORE_CONTINUE31:%.*]]
737; CHECK:       pred.store.if30:
738; CHECK-NEXT:    [[TMP69:%.*]] = shl nsw i64 [[TMP6]], 2
739; CHECK-NEXT:    [[TMP70:%.*]] = getelementptr double, ptr [[A]], i64 [[TMP69]]
740; CHECK-NEXT:    store double 0.000000e+00, ptr [[TMP70]], align 8
741; CHECK-NEXT:    br label [[PRED_STORE_CONTINUE31]]
742; CHECK:       pred.store.continue31:
743; CHECK-NEXT:    [[TMP71:%.*]] = extractelement <4 x i1> [[TMP22]], i32 1
744; CHECK-NEXT:    br i1 [[TMP71]], label [[PRED_STORE_IF32:%.*]], label [[PRED_STORE_CONTINUE33:%.*]]
745; CHECK:       pred.store.if32:
746; CHECK-NEXT:    [[TMP72:%.*]] = add i64 [[INDEX]], 13
747; CHECK-NEXT:    [[TMP73:%.*]] = shl nsw i64 [[TMP72]], 2
748; CHECK-NEXT:    [[TMP74:%.*]] = getelementptr double, ptr [[A]], i64 [[TMP73]]
749; CHECK-NEXT:    store double 0.000000e+00, ptr [[TMP74]], align 8
750; CHECK-NEXT:    br label [[PRED_STORE_CONTINUE33]]
751; CHECK:       pred.store.continue33:
752; CHECK-NEXT:    [[TMP75:%.*]] = extractelement <4 x i1> [[TMP22]], i32 2
753; CHECK-NEXT:    br i1 [[TMP75]], label [[PRED_STORE_IF34:%.*]], label [[PRED_STORE_CONTINUE35:%.*]]
754; CHECK:       pred.store.if34:
755; CHECK-NEXT:    [[TMP76:%.*]] = add i64 [[INDEX]], 14
756; CHECK-NEXT:    [[TMP77:%.*]] = shl nsw i64 [[TMP76]], 2
757; CHECK-NEXT:    [[TMP78:%.*]] = getelementptr double, ptr [[A]], i64 [[TMP77]]
758; CHECK-NEXT:    store double 0.000000e+00, ptr [[TMP78]], align 8
759; CHECK-NEXT:    br label [[PRED_STORE_CONTINUE35]]
760; CHECK:       pred.store.continue35:
761; CHECK-NEXT:    [[TMP79:%.*]] = extractelement <4 x i1> [[TMP22]], i32 3
762; CHECK-NEXT:    br i1 [[TMP79]], label [[PRED_STORE_IF36:%.*]], label [[PRED_STORE_CONTINUE37]]
763; CHECK:       pred.store.if36:
764; CHECK-NEXT:    [[TMP80:%.*]] = add i64 [[INDEX]], 15
765; CHECK-NEXT:    [[TMP81:%.*]] = shl nsw i64 [[TMP80]], 2
766; CHECK-NEXT:    [[TMP82:%.*]] = getelementptr double, ptr [[A]], i64 [[TMP81]]
767; CHECK-NEXT:    store double 0.000000e+00, ptr [[TMP82]], align 8
768; CHECK-NEXT:    br label [[PRED_STORE_CONTINUE37]]
769; CHECK:       pred.store.continue37:
770; CHECK-NEXT:    [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16
771; CHECK-NEXT:    [[TMP83:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
772; CHECK-NEXT:    br i1 [[TMP83]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP17:![0-9]+]]
773; CHECK:       middle.block:
774; CHECK-NEXT:    br label [[VEC_EPILOG_ITER_CHECK:%.*]]
775; CHECK:       vec.epilog.iter.check:
776; CHECK-NEXT:    [[N_VEC_REMAINING:%.*]] = sub i64 [[TMP0]], [[N_VEC]]
777; CHECK-NEXT:    [[MIN_EPILOG_ITERS_CHECK:%.*]] = icmp ule i64 [[N_VEC_REMAINING]], 4
778; CHECK-NEXT:    br i1 [[MIN_EPILOG_ITERS_CHECK]], label [[VEC_EPILOG_SCALAR_PH]], label [[VEC_EPILOG_PH]]
779; CHECK:       vec.epilog.ph:
780; CHECK-NEXT:    [[VEC_EPILOG_RESUME_VAL1:%.*]] = phi i64 [ [[N_VEC]], [[VEC_EPILOG_ITER_CHECK]] ], [ 0, [[VECTOR_MAIN_LOOP_ITER_CHECK]] ]
781; CHECK-NEXT:    [[N_MOD_VF38:%.*]] = urem i64 [[TMP0]], 4
782; CHECK-NEXT:    [[TMP84:%.*]] = icmp eq i64 [[N_MOD_VF38]], 0
783; CHECK-NEXT:    [[TMP85:%.*]] = select i1 [[TMP84]], i64 4, i64 [[N_MOD_VF38]]
784; CHECK-NEXT:    [[N_VEC39:%.*]] = sub i64 [[TMP0]], [[TMP85]]
785; CHECK-NEXT:    br label [[VEC_EPILOG_VECTOR_BODY:%.*]]
786; CHECK:       vec.epilog.vector.body:
787; CHECK-NEXT:    [[INDEX40:%.*]] = phi i64 [ [[VEC_EPILOG_RESUME_VAL1]], [[VEC_EPILOG_PH]] ], [ [[INDEX_NEXT51:%.*]], [[PRED_STORE_CONTINUE50:%.*]] ]
788; CHECK-NEXT:    [[TMP86:%.*]] = add i64 [[INDEX40]], 0
789; CHECK-NEXT:    [[TMP87:%.*]] = shl nsw i64 [[TMP86]], 2
790; CHECK-NEXT:    [[TMP89:%.*]] = getelementptr nusw double, ptr [[A]], i64 [[TMP87]]
791; CHECK-NEXT:    [[WIDE_VEC41:%.*]] = load <16 x double>, ptr [[TMP89]], align 8
792; CHECK-NEXT:    [[STRIDED_VEC42:%.*]] = shufflevector <16 x double> [[WIDE_VEC41]], <16 x double> poison, <4 x i32> <i32 0, i32 4, i32 8, i32 12>
793; CHECK-NEXT:    [[TMP90:%.*]] = fcmp oeq <4 x double> [[STRIDED_VEC42]], zeroinitializer
794; CHECK-NEXT:    [[TMP91:%.*]] = extractelement <4 x i1> [[TMP90]], i32 0
795; CHECK-NEXT:    br i1 [[TMP91]], label [[PRED_STORE_IF43:%.*]], label [[PRED_STORE_CONTINUE44:%.*]]
796; CHECK:       pred.store.if43:
797; CHECK-NEXT:    [[TMP92:%.*]] = shl nsw i64 [[TMP86]], 2
798; CHECK-NEXT:    [[TMP93:%.*]] = getelementptr double, ptr [[A]], i64 [[TMP92]]
799; CHECK-NEXT:    store double 0.000000e+00, ptr [[TMP93]], align 8
800; CHECK-NEXT:    br label [[PRED_STORE_CONTINUE44]]
801; CHECK:       pred.store.continue44:
802; CHECK-NEXT:    [[TMP94:%.*]] = extractelement <4 x i1> [[TMP90]], i32 1
803; CHECK-NEXT:    br i1 [[TMP94]], label [[PRED_STORE_IF45:%.*]], label [[PRED_STORE_CONTINUE46:%.*]]
804; CHECK:       pred.store.if45:
805; CHECK-NEXT:    [[TMP95:%.*]] = add i64 [[INDEX40]], 1
806; CHECK-NEXT:    [[TMP96:%.*]] = shl nsw i64 [[TMP95]], 2
807; CHECK-NEXT:    [[TMP97:%.*]] = getelementptr double, ptr [[A]], i64 [[TMP96]]
808; CHECK-NEXT:    store double 0.000000e+00, ptr [[TMP97]], align 8
809; CHECK-NEXT:    br label [[PRED_STORE_CONTINUE46]]
810; CHECK:       pred.store.continue46:
811; CHECK-NEXT:    [[TMP98:%.*]] = extractelement <4 x i1> [[TMP90]], i32 2
812; CHECK-NEXT:    br i1 [[TMP98]], label [[PRED_STORE_IF47:%.*]], label [[PRED_STORE_CONTINUE48:%.*]]
813; CHECK:       pred.store.if47:
814; CHECK-NEXT:    [[TMP99:%.*]] = add i64 [[INDEX40]], 2
815; CHECK-NEXT:    [[TMP100:%.*]] = shl nsw i64 [[TMP99]], 2
816; CHECK-NEXT:    [[TMP101:%.*]] = getelementptr double, ptr [[A]], i64 [[TMP100]]
817; CHECK-NEXT:    store double 0.000000e+00, ptr [[TMP101]], align 8
818; CHECK-NEXT:    br label [[PRED_STORE_CONTINUE48]]
819; CHECK:       pred.store.continue48:
820; CHECK-NEXT:    [[TMP102:%.*]] = extractelement <4 x i1> [[TMP90]], i32 3
821; CHECK-NEXT:    br i1 [[TMP102]], label [[PRED_STORE_IF49:%.*]], label [[PRED_STORE_CONTINUE50]]
822; CHECK:       pred.store.if49:
823; CHECK-NEXT:    [[TMP103:%.*]] = add i64 [[INDEX40]], 3
824; CHECK-NEXT:    [[TMP104:%.*]] = shl nsw i64 [[TMP103]], 2
825; CHECK-NEXT:    [[TMP105:%.*]] = getelementptr double, ptr [[A]], i64 [[TMP104]]
826; CHECK-NEXT:    store double 0.000000e+00, ptr [[TMP105]], align 8
827; CHECK-NEXT:    br label [[PRED_STORE_CONTINUE50]]
828; CHECK:       pred.store.continue50:
829; CHECK-NEXT:    [[INDEX_NEXT51]] = add nuw i64 [[INDEX40]], 4
830; CHECK-NEXT:    [[TMP106:%.*]] = icmp eq i64 [[INDEX_NEXT51]], [[N_VEC39]]
831; CHECK-NEXT:    br i1 [[TMP106]], label [[VEC_EPILOG_MIDDLE_BLOCK:%.*]], label [[VEC_EPILOG_VECTOR_BODY]], !llvm.loop [[LOOP18:![0-9]+]]
832; CHECK:       vec.epilog.middle.block:
833; CHECK-NEXT:    br label [[VEC_EPILOG_SCALAR_PH]]
834; CHECK:       vec.epilog.scalar.ph:
835; CHECK-NEXT:    [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC39]], [[VEC_EPILOG_MIDDLE_BLOCK]] ], [ 0, [[ITER_CHECK:%.*]] ], [ [[N_VEC]], [[VEC_EPILOG_ITER_CHECK]] ]
836; CHECK-NEXT:    br label [[LOOP_HEADER:%.*]]
837; CHECK:       loop.header:
838; CHECK-NEXT:    [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[VEC_EPILOG_SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LOOP_LATCH:%.*]] ]
839; CHECK-NEXT:    [[IV_SHL:%.*]] = shl nsw i64 [[IV]], 2
840; CHECK-NEXT:    [[GEP_0:%.*]] = getelementptr nusw double, ptr [[A]], i64 [[IV_SHL]]
841; CHECK-NEXT:    [[L:%.*]] = load double, ptr [[GEP_0]], align 8
842; CHECK-NEXT:    [[C:%.*]] = fcmp oeq double [[L]], 0.000000e+00
843; CHECK-NEXT:    br i1 [[C]], label [[IF_THEN:%.*]], label [[LOOP_LATCH]]
844; CHECK:       if.then:
845; CHECK-NEXT:    [[GEP_1:%.*]] = getelementptr double, ptr [[A]], i64 [[IV_SHL]]
846; CHECK-NEXT:    store double 0.000000e+00, ptr [[GEP_1]], align 8
847; CHECK-NEXT:    br label [[LOOP_LATCH]]
848; CHECK:       loop.latch:
849; CHECK-NEXT:    [[IV_NEXT]] = add nsw i64 [[IV]], 1
850; CHECK-NEXT:    [[EC:%.*]] = icmp eq i64 [[IV]], [[N]]
851; CHECK-NEXT:    br i1 [[EC]], label [[EXIT:%.*]], label [[LOOP_HEADER]], !llvm.loop [[LOOP19:![0-9]+]]
852; CHECK:       exit:
853; CHECK-NEXT:    ret void
854;
855entry:
856  br label %loop.header
857
858loop.header:
859  %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop.latch ]
860  %iv.shl = shl nsw i64 %iv, 2
861  %gep.0 = getelementptr nusw double, ptr %A, i64 %iv.shl
862  %l = load double, ptr %gep.0, align 8
863  %c = fcmp oeq double %l, 0.000000e+00
864  br i1 %c, label %if.then, label %loop.latch
865
866if.then:
867  %gep.1 = getelementptr double, ptr %A, i64 %iv.shl
868  store double 0.000000e+00, ptr %gep.1, align 8
869  br label %loop.latch
870
871loop.latch:
872  %iv.next = add nsw i64 %iv, 1
873  %ec = icmp eq i64 %iv, %N
874  br i1 %ec, label %exit, label %loop.header
875
876exit:
877  ret void
878}
879
880define i64 @cost_assume(ptr %end, i64 %N) {
881; CHECK-LABEL: @cost_assume(
882; CHECK-NEXT:  entry:
883; CHECK-NEXT:    [[END1:%.*]] = ptrtoint ptr [[END:%.*]] to i64
884; CHECK-NEXT:    [[TMP0:%.*]] = add i64 [[END1]], -9
885; CHECK-NEXT:    [[TMP1:%.*]] = udiv i64 [[TMP0]], 9
886; CHECK-NEXT:    [[TMP2:%.*]] = add nuw nsw i64 [[TMP1]], 1
887; CHECK-NEXT:    [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP2]], 8
888; CHECK-NEXT:    br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
889; CHECK:       vector.ph:
890; CHECK-NEXT:    [[N_MOD_VF:%.*]] = urem i64 [[TMP2]], 8
891; CHECK-NEXT:    [[N_VEC:%.*]] = sub i64 [[TMP2]], [[N_MOD_VF]]
892; CHECK-NEXT:    [[BROADCAST_SPLATINSERT:%.*]] = insertelement <2 x i64> poison, i64 [[N:%.*]], i64 0
893; CHECK-NEXT:    [[BROADCAST_SPLAT:%.*]] = shufflevector <2 x i64> [[BROADCAST_SPLATINSERT]], <2 x i64> poison, <2 x i32> zeroinitializer
894; CHECK-NEXT:    [[TMP3:%.*]] = icmp ne <2 x i64> [[BROADCAST_SPLAT]], zeroinitializer
895; CHECK-NEXT:    br label [[VECTOR_BODY:%.*]]
896; CHECK:       vector.body:
897; CHECK-NEXT:    [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
898; CHECK-NEXT:    [[VEC_PHI:%.*]] = phi <2 x i64> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP7:%.*]], [[VECTOR_BODY]] ]
899; CHECK-NEXT:    [[VEC_PHI2:%.*]] = phi <2 x i64> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP8:%.*]], [[VECTOR_BODY]] ]
900; CHECK-NEXT:    [[VEC_PHI3:%.*]] = phi <2 x i64> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP9:%.*]], [[VECTOR_BODY]] ]
901; CHECK-NEXT:    [[VEC_PHI4:%.*]] = phi <2 x i64> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP10:%.*]], [[VECTOR_BODY]] ]
902; CHECK-NEXT:    [[TMP7]] = add <2 x i64> [[VEC_PHI]], splat (i64 1)
903; CHECK-NEXT:    [[TMP8]] = add <2 x i64> [[VEC_PHI2]], splat (i64 1)
904; CHECK-NEXT:    [[TMP9]] = add <2 x i64> [[VEC_PHI3]], splat (i64 1)
905; CHECK-NEXT:    [[TMP10]] = add <2 x i64> [[VEC_PHI4]], splat (i64 1)
906; CHECK-NEXT:    [[TMP11:%.*]] = extractelement <2 x i1> [[TMP3]], i32 0
907; CHECK-NEXT:    tail call void @llvm.assume(i1 [[TMP11]])
908; CHECK-NEXT:    tail call void @llvm.assume(i1 [[TMP11]])
909; CHECK-NEXT:    tail call void @llvm.assume(i1 [[TMP11]])
910; CHECK-NEXT:    tail call void @llvm.assume(i1 [[TMP11]])
911; CHECK-NEXT:    tail call void @llvm.assume(i1 [[TMP11]])
912; CHECK-NEXT:    tail call void @llvm.assume(i1 [[TMP11]])
913; CHECK-NEXT:    tail call void @llvm.assume(i1 [[TMP11]])
914; CHECK-NEXT:    tail call void @llvm.assume(i1 [[TMP11]])
915; CHECK-NEXT:    [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8
916; CHECK-NEXT:    [[TMP13:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
917; CHECK-NEXT:    br i1 [[TMP13]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP20:![0-9]+]]
918; CHECK:       middle.block:
919; CHECK-NEXT:    [[BIN_RDX:%.*]] = add <2 x i64> [[TMP8]], [[TMP7]]
920; CHECK-NEXT:    [[BIN_RDX5:%.*]] = add <2 x i64> [[TMP9]], [[BIN_RDX]]
921; CHECK-NEXT:    [[BIN_RDX6:%.*]] = add <2 x i64> [[TMP10]], [[BIN_RDX5]]
922; CHECK-NEXT:    [[TMP14:%.*]] = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> [[BIN_RDX6]])
923; CHECK-NEXT:    [[CMP_N:%.*]] = icmp eq i64 [[TMP2]], [[N_VEC]]
924; CHECK-NEXT:    br i1 [[CMP_N]], label [[EXIT:%.*]], label [[SCALAR_PH]]
925; CHECK:       scalar.ph:
926; CHECK-NEXT:    [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ]
927; CHECK-NEXT:    [[BC_MERGE_RDX:%.*]] = phi i64 [ [[TMP14]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY]] ]
928; CHECK-NEXT:    br label [[LOOP:%.*]]
929; CHECK:       loop:
930; CHECK-NEXT:    [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
931; CHECK-NEXT:    [[TMP15:%.*]] = phi i64 [ [[BC_MERGE_RDX]], [[SCALAR_PH]] ], [ [[TMP12:%.*]], [[LOOP]] ]
932; CHECK-NEXT:    [[TMP12]] = add i64 [[TMP15]], 1
933; CHECK-NEXT:    [[IV_NEXT]] = add nsw i64 [[IV]], 1
934; CHECK-NEXT:    [[C:%.*]] = icmp ne i64 [[N]], 0
935; CHECK-NEXT:    tail call void @llvm.assume(i1 [[C]])
936; CHECK-NEXT:    [[GEP:%.*]] = getelementptr nusw [9 x i8], ptr null, i64 [[IV_NEXT]]
937; CHECK-NEXT:    [[EC:%.*]] = icmp eq ptr [[GEP]], [[END]]
938; CHECK-NEXT:    br i1 [[EC]], label [[EXIT]], label [[LOOP]], !llvm.loop [[LOOP21:![0-9]+]]
939; CHECK:       exit:
940; CHECK-NEXT:    [[DOTLCSSA:%.*]] = phi i64 [ [[TMP12]], [[LOOP]] ], [ [[TMP14]], [[MIDDLE_BLOCK]] ]
941; CHECK-NEXT:    ret i64 [[DOTLCSSA]]
942;
943entry:
944  br label %loop
945
946loop:
947  %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
948  %0 = phi i64 [ 0, %entry ], [ %1, %loop ]
949  %1 = add i64 %0, 1
950  %iv.next = add nsw i64 %iv, 1
951  %c = icmp ne i64 %N, 0
952  tail call void @llvm.assume(i1 %c)
953  %gep = getelementptr nusw [ 9 x i8 ], ptr null, i64 %iv.next
954  %ec = icmp eq ptr %gep, %end
955  br i1 %ec, label %exit, label %loop
956
957exit:
958  ret i64 %1
959}
960
961; Test case for https://github.com/llvm/llvm-project/issues/96294 with a stored
962; reduction which overwrites an earlier store.
963define void @reduction_store(ptr noalias %src, ptr %dst, i1 %x) #2 {
964; CHECK-LABEL: @reduction_store(
965; CHECK-NEXT:  entry:
966; CHECK-NEXT:    br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
967; CHECK:       vector.ph:
968; CHECK-NEXT:    [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i1> poison, i1 [[X:%.*]], i64 0
969; CHECK-NEXT:    [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i1> [[BROADCAST_SPLATINSERT]], <4 x i1> poison, <4 x i32> zeroinitializer
970; CHECK-NEXT:    [[TMP0:%.*]] = zext <4 x i1> [[BROADCAST_SPLAT]] to <4 x i64>
971; CHECK-NEXT:    [[TMP1:%.*]] = lshr <4 x i64> [[TMP0]], splat (i64 12)
972; CHECK-NEXT:    [[TMP2:%.*]] = trunc <4 x i64> [[TMP1]] to <4 x i32>
973; CHECK-NEXT:    br label [[VECTOR_BODY:%.*]]
974; CHECK:       vector.body:
975; CHECK-NEXT:    [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
976; CHECK-NEXT:    [[VEC_PHI:%.*]] = phi <4 x i32> [ <i32 0, i32 -1, i32 -1, i32 -1>, [[VECTOR_PH]] ], [ [[TMP11:%.*]], [[VECTOR_BODY]] ]
977; CHECK-NEXT:    [[VEC_PHI1:%.*]] = phi <4 x i32> [ splat (i32 -1), [[VECTOR_PH]] ], [ [[TMP12:%.*]], [[VECTOR_BODY]] ]
978; CHECK-NEXT:    [[TMP11]] = and <4 x i32> [[VEC_PHI]], [[TMP2]]
979; CHECK-NEXT:    [[TMP12]] = and <4 x i32> [[VEC_PHI1]], [[TMP2]]
980; CHECK-NEXT:    [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 8
981; CHECK-NEXT:    [[TMP9:%.*]] = icmp eq i32 [[INDEX_NEXT]], 24
982; CHECK-NEXT:    br i1 [[TMP9]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP22:![0-9]+]]
983; CHECK:       middle.block:
984; CHECK-NEXT:    [[BIN_RDX:%.*]] = and <4 x i32> [[TMP12]], [[TMP11]]
985; CHECK-NEXT:    [[TMP10:%.*]] = call i32 @llvm.vector.reduce.and.v4i32(<4 x i32> [[BIN_RDX]])
986; CHECK-NEXT:    store i32 [[TMP10]], ptr [[DST:%.*]], align 4
987; CHECK-NEXT:    br i1 false, label [[EXIT:%.*]], label [[SCALAR_PH]]
988; CHECK:       scalar.ph:
989; CHECK-NEXT:    [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP10]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ]
990; CHECK-NEXT:    [[BC_RESUME_VAL:%.*]] = phi i32 [ 24, [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY]] ]
991; CHECK-NEXT:    br label [[LOOP:%.*]]
992; CHECK:       loop:
993; CHECK-NEXT:    [[RED:%.*]] = phi i32 [ [[BC_MERGE_RDX]], [[SCALAR_PH]] ], [ [[RED_NEXT:%.*]], [[LOOP]] ]
994; CHECK-NEXT:    [[IV:%.*]] = phi i32 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
995; CHECK-NEXT:    [[GEP_SRC:%.*]] = getelementptr inbounds i32, ptr [[SRC:%.*]], i32 [[IV]]
996; CHECK-NEXT:    [[L:%.*]] = load i32, ptr [[GEP_SRC]], align 4
997; CHECK-NEXT:    [[L_AND:%.*]] = and i32 [[L]], 3
998; CHECK-NEXT:    store i32 [[L_AND]], ptr [[DST]], align 4
999; CHECK-NEXT:    [[X_EXT:%.*]] = zext i1 [[X]] to i64
1000; CHECK-NEXT:    [[LSHR:%.*]] = lshr i64 [[X_EXT]], 12
1001; CHECK-NEXT:    [[T:%.*]] = trunc i64 [[LSHR]] to i32
1002; CHECK-NEXT:    [[RED_NEXT]] = and i32 [[RED]], [[T]]
1003; CHECK-NEXT:    store i32 [[RED_NEXT]], ptr [[DST]], align 4
1004; CHECK-NEXT:    [[IV_NEXT]] = add i32 [[IV]], 1
1005; CHECK-NEXT:    [[EC:%.*]] = icmp eq i32 [[IV]], 29
1006; CHECK-NEXT:    br i1 [[EC]], label [[EXIT]], label [[LOOP]], !llvm.loop [[LOOP23:![0-9]+]]
1007; CHECK:       exit:
1008; CHECK-NEXT:    ret void
1009;
1010entry:
1011  br label %loop
1012
1013loop:
1014  %red = phi i32 [ 0, %entry ], [ %red.next, %loop ]
1015  %iv = phi i32 [ 0, %entry ], [ %iv.next, %loop ]
1016  %gep.src = getelementptr inbounds i32, ptr %src, i32 %iv
1017  %l = load i32, ptr %gep.src
1018  %l.and = and i32 %l, 3
1019  store i32 %l.and, ptr %dst, align 4
1020  %x.ext = zext i1 %x to i64
1021  %lshr = lshr i64 %x.ext, 12
1022  %t = trunc i64 %lshr to i32
1023  %red.next = and i32 %red, %t
1024  store i32 %red.next, ptr %dst, align 4
1025  %iv.next = add i32 %iv, 1
1026  %ec = icmp eq i32 %iv, 29
1027  br i1 %ec, label %exit, label %loop
1028
1029exit:
1030  ret void
1031}
1032
1033; Test case for https://github.com/llvm/llvm-project/issues/105722.
1034define i64 @live_in_known_1_via_scev() {
1035; CHECK-LABEL: @live_in_known_1_via_scev(
1036; CHECK-NEXT:  entry:
1037; CHECK-NEXT:    [[SEL:%.*]] = select i1 false, i32 3, i32 0
1038; CHECK-NEXT:    br label [[PH:%.*]]
1039; CHECK:       ph:
1040; CHECK-NEXT:    [[P:%.*]] = phi i32 [ 1, [[ENTRY:%.*]] ]
1041; CHECK-NEXT:    [[N:%.*]] = add nuw nsw i32 [[SEL]], 6
1042; CHECK-NEXT:    [[P_EXT:%.*]] = zext nneg i32 [[P]] to i64
1043; CHECK-NEXT:    br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
1044; CHECK:       vector.ph:
1045; CHECK-NEXT:    br label [[VECTOR_BODY:%.*]]
1046; CHECK:       vector.body:
1047; CHECK-NEXT:    [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
1048; CHECK-NEXT:    [[VEC_PHI:%.*]] = phi <4 x i64> [ <i64 3, i64 1, i64 1, i64 1>, [[VECTOR_PH]] ], [ [[VEC_PHI]], [[VECTOR_BODY]] ]
1049; CHECK-NEXT:    [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i32> poison, i32 [[INDEX]], i64 0
1050; CHECK-NEXT:    [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i32> [[BROADCAST_SPLATINSERT]], <4 x i32> poison, <4 x i32> zeroinitializer
1051; CHECK-NEXT:    [[VEC_IV:%.*]] = add <4 x i32> [[BROADCAST_SPLAT]], <i32 0, i32 1, i32 2, i32 3>
1052; CHECK-NEXT:    [[TMP0:%.*]] = icmp ule <4 x i32> [[VEC_IV]], splat (i32 5)
1053; CHECK-NEXT:    [[TMP1:%.*]] = select <4 x i1> [[TMP0]], <4 x i64> [[VEC_PHI]], <4 x i64> [[VEC_PHI]]
1054; CHECK-NEXT:    [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4
1055; CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i32 [[INDEX_NEXT]], 8
1056; CHECK-NEXT:    br i1 [[TMP2]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP24:![0-9]+]]
1057; CHECK:       middle.block:
1058; CHECK-NEXT:    [[TMP3:%.*]] = call i64 @llvm.vector.reduce.mul.v4i64(<4 x i64> [[TMP1]])
1059; CHECK-NEXT:    br i1 true, label [[EXIT:%.*]], label [[SCALAR_PH]]
1060; CHECK:       scalar.ph:
1061; CHECK-NEXT:    [[BC_RESUME_VAL:%.*]] = phi i32 [ 8, [[MIDDLE_BLOCK]] ], [ 0, [[PH]] ]
1062; CHECK-NEXT:    [[BC_MERGE_RDX:%.*]] = phi i64 [ [[TMP3]], [[MIDDLE_BLOCK]] ], [ 3, [[PH]] ]
1063; CHECK-NEXT:    br label [[LOOP:%.*]]
1064; CHECK:       loop:
1065; CHECK-NEXT:    [[IV:%.*]] = phi i32 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
1066; CHECK-NEXT:    [[RED:%.*]] = phi i64 [ [[BC_MERGE_RDX]], [[SCALAR_PH]] ], [ [[RED_MUL:%.*]], [[LOOP]] ]
1067; CHECK-NEXT:    [[RED_MUL]] = mul nsw i64 [[RED]], [[P_EXT]]
1068; CHECK-NEXT:    [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1
1069; CHECK-NEXT:    [[EC:%.*]] = icmp eq i32 [[IV_NEXT]], [[N]]
1070; CHECK-NEXT:    br i1 [[EC]], label [[EXIT]], label [[LOOP]], !llvm.loop [[LOOP25:![0-9]+]]
1071; CHECK:       exit:
1072; CHECK-NEXT:    [[RES:%.*]] = phi i64 [ [[RED_MUL]], [[LOOP]] ], [ [[TMP3]], [[MIDDLE_BLOCK]] ]
1073; CHECK-NEXT:    ret i64 [[RES]]
1074;
1075entry:
1076  %sel = select i1 false, i32 3, i32 0
1077  br label %ph
1078
1079ph:
1080  %p = phi i32 [ 1, %entry ]
1081  %N = add nuw nsw i32 %sel, 6
1082  %p.ext = zext nneg i32 %p to i64
1083  br label %loop
1084
1085loop:
1086  %iv = phi i32 [ 0, %ph ], [ %iv.next, %loop ]
1087  %red = phi i64 [ 3, %ph ], [ %red.mul,  %loop ]
1088  %red.mul = mul nsw i64 %red, %p.ext
1089  %iv.next = add nuw nsw i32 %iv, 1
1090  %ec = icmp eq i32 %iv.next, %N
1091  br i1 %ec, label %exit, label %loop
1092
1093exit:
1094  %res = phi i64 [ %red.mul, %loop ]
1095  ret i64 %res
1096}
1097
1098; Test case for https://github.com/llvm/llvm-project/issues/107501.
1099define i64 @cost_loop_invariant_recipes(i1 %x, i64 %y) {
1100; CHECK-LABEL: @cost_loop_invariant_recipes(
1101; CHECK-NEXT:  entry:
1102; CHECK-NEXT:    br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
1103; CHECK:       vector.ph:
1104; CHECK-NEXT:    [[BROADCAST_SPLATINSERT:%.*]] = insertelement <2 x i1> poison, i1 [[X:%.*]], i64 0
1105; CHECK-NEXT:    [[BROADCAST_SPLAT:%.*]] = shufflevector <2 x i1> [[BROADCAST_SPLATINSERT]], <2 x i1> poison, <2 x i32> zeroinitializer
1106; CHECK-NEXT:    [[TMP0:%.*]] = xor <2 x i1> [[BROADCAST_SPLAT]], splat (i1 true)
1107; CHECK-NEXT:    [[TMP1:%.*]] = zext <2 x i1> [[TMP0]] to <2 x i64>
1108; CHECK-NEXT:    [[BROADCAST_SPLATINSERT1:%.*]] = insertelement <2 x i64> poison, i64 [[Y:%.*]], i64 0
1109; CHECK-NEXT:    [[BROADCAST_SPLAT2:%.*]] = shufflevector <2 x i64> [[BROADCAST_SPLATINSERT1]], <2 x i64> poison, <2 x i32> zeroinitializer
1110; CHECK-NEXT:    [[TMP2:%.*]] = shl <2 x i64> [[BROADCAST_SPLAT2]], [[TMP1]]
1111; CHECK-NEXT:    br label [[VECTOR_BODY:%.*]]
1112; CHECK:       vector.body:
1113; CHECK-NEXT:    [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
1114; CHECK-NEXT:    [[VEC_PHI:%.*]] = phi <2 x i64> [ splat (i64 1), [[VECTOR_PH]] ], [ [[TMP3:%.*]], [[VECTOR_BODY]] ]
1115; CHECK-NEXT:    [[TMP3]] = mul <2 x i64> [[TMP2]], [[VEC_PHI]]
1116; CHECK-NEXT:    [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2
1117; CHECK-NEXT:    br i1 true, label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP26:![0-9]+]]
1118; CHECK:       middle.block:
1119; CHECK-NEXT:    [[TMP4:%.*]] = call i64 @llvm.vector.reduce.mul.v2i64(<2 x i64> [[TMP3]])
1120; CHECK-NEXT:    br i1 true, label [[EXIT:%.*]], label [[SCALAR_PH]]
1121; CHECK:       scalar.ph:
1122; CHECK-NEXT:    [[BC_RESUME_VAL:%.*]] = phi i64 [ 2, [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ]
1123; CHECK-NEXT:    [[BC_MERGE_RDX:%.*]] = phi i64 [ [[TMP4]], [[MIDDLE_BLOCK]] ], [ 1, [[ENTRY]] ]
1124; CHECK-NEXT:    br label [[LOOP:%.*]]
1125; CHECK:       loop:
1126; CHECK-NEXT:    [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT_I_I_I:%.*]], [[LOOP]] ]
1127; CHECK-NEXT:    [[RED:%.*]] = phi i64 [ [[BC_MERGE_RDX]], [[SCALAR_PH]] ], [ [[RED_MUL:%.*]], [[LOOP]] ]
1128; CHECK-NEXT:    [[NOT_X:%.*]] = xor i1 [[X]], true
1129; CHECK-NEXT:    [[EXT:%.*]] = zext i1 [[NOT_X]] to i64
1130; CHECK-NEXT:    [[SHL:%.*]] = shl i64 [[Y]], [[EXT]]
1131; CHECK-NEXT:    [[RED_MUL]] = mul i64 [[SHL]], [[RED]]
1132; CHECK-NEXT:    [[IV_NEXT_I_I_I]] = add i64 [[IV]], 1
1133; CHECK-NEXT:    [[EC:%.*]] = icmp eq i64 [[IV]], 1
1134; CHECK-NEXT:    br i1 [[EC]], label [[EXIT]], label [[LOOP]], !llvm.loop [[LOOP27:![0-9]+]]
1135; CHECK:       exit:
1136; CHECK-NEXT:    [[RED_MUL_LCSSA:%.*]] = phi i64 [ [[RED_MUL]], [[LOOP]] ], [ [[TMP4]], [[MIDDLE_BLOCK]] ]
1137; CHECK-NEXT:    ret i64 [[RED_MUL_LCSSA]]
1138;
1139entry:
1140  br label %loop
1141
1142loop:
1143  %iv = phi i64 [ 0, %entry ], [ %iv.next.i.i.i, %loop ]
1144  %red = phi i64 [ 1, %entry ], [ %red.mul, %loop ]
1145  %not.x = xor i1 %x, true
1146  %ext = zext i1 %not.x to i64
1147  %shl = shl i64 %y, %ext
1148  %red.mul = mul i64 %shl, %red
1149  %iv.next.i.i.i = add i64 %iv, 1
1150  %ec = icmp eq i64 %iv, 1
1151  br i1 %ec, label %exit, label %loop
1152
1153exit:
1154  ret i64 %red.mul
1155}
1156
1157; Test case for https://github.com/llvm/llvm-project/issues/113526.
1158define i32 @narrowed_reduction(ptr %a, i1 %cmp) #0 {
1159; CHECK-LABEL: @narrowed_reduction(
1160; CHECK-NEXT:  entry:
1161; CHECK-NEXT:    [[CONV:%.*]] = zext i1 [[CMP:%.*]] to i32
1162; CHECK-NEXT:    br i1 false, label [[VEC_EPILOG_PH:%.*]], label [[VECTOR_PH1:%.*]]
1163; CHECK:       vector.ph:
1164; CHECK-NEXT:    [[BROADCAST_SPLATINSERT:%.*]] = insertelement <16 x i32> poison, i32 [[CONV]], i64 0
1165; CHECK-NEXT:    [[BROADCAST_SPLAT:%.*]] = shufflevector <16 x i32> [[BROADCAST_SPLATINSERT]], <16 x i32> poison, <16 x i32> zeroinitializer
1166; CHECK-NEXT:    br label [[VECTOR_BODY:%.*]]
1167; CHECK:       vector.body:
1168; CHECK-NEXT:    [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH1]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
1169; CHECK-NEXT:    [[VEC_PHI1:%.*]] = phi <16 x i32> [ zeroinitializer, [[VECTOR_PH1]] ], [ [[TMP7:%.*]], [[VECTOR_BODY]] ]
1170; CHECK-NEXT:    [[TMP1:%.*]] = and <16 x i32> [[VEC_PHI1]], splat (i32 1)
1171; CHECK-NEXT:    [[TMP3:%.*]] = or <16 x i32> [[TMP1]], [[BROADCAST_SPLAT]]
1172; CHECK-NEXT:    [[TMP5:%.*]] = trunc <16 x i32> [[TMP3]] to <16 x i1>
1173; CHECK-NEXT:    [[TMP7]] = zext <16 x i1> [[TMP5]] to <16 x i32>
1174; CHECK-NEXT:    [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 16
1175; CHECK-NEXT:    br i1 true, label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP28:![0-9]+]]
1176; CHECK:       middle.block:
1177; CHECK-NEXT:    [[TMP10:%.*]] = trunc <16 x i32> [[TMP7]] to <16 x i1>
1178; CHECK-NEXT:    [[TMP20:%.*]] = call i1 @llvm.vector.reduce.or.v16i1(<16 x i1> [[TMP10]])
1179; CHECK-NEXT:    [[TMP21:%.*]] = zext i1 [[TMP20]] to i32
1180; CHECK-NEXT:    br i1 true, label [[EXIT:%.*]], label [[VEC_EPILOG_PH]]
1181; CHECK:       scalar.ph:
1182; CHECK-NEXT:    [[BC_RESUME_VAL:%.*]] = phi i32 [ 17, [[MIDDLE_BLOCK]] ], [ 1, [[ENTRY:%.*]] ]
1183; CHECK-NEXT:    [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP21]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY]] ]
1184; CHECK-NEXT:    br label [[LOOP1:%.*]]
1185; CHECK:       loop:
1186; CHECK-NEXT:    [[IV:%.*]] = phi i32 [ [[BC_RESUME_VAL]], [[VEC_EPILOG_PH]] ], [ [[INC:%.*]], [[LOOP1]] ]
1187; CHECK-NEXT:    [[OR13:%.*]] = phi i32 [ [[BC_MERGE_RDX]], [[VEC_EPILOG_PH]] ], [ [[OR:%.*]], [[LOOP1]] ]
1188; CHECK-NEXT:    [[AND:%.*]] = and i32 [[OR13]], 1
1189; CHECK-NEXT:    [[OR]] = or i32 [[AND]], [[CONV]]
1190; CHECK-NEXT:    [[INC]] = add i32 [[IV]], 1
1191; CHECK-NEXT:    [[EC:%.*]] = icmp eq i32 [[IV]], 16
1192; CHECK-NEXT:    br i1 [[EC]], label [[EXIT]], label [[LOOP1]], !llvm.loop [[LOOP29:![0-9]+]]
1193; CHECK:       exit:
1194; CHECK-NEXT:    [[OR_LCSSA:%.*]] = phi i32 [ [[OR]], [[LOOP1]] ], [ [[TMP21]], [[MIDDLE_BLOCK]] ]
1195; CHECK-NEXT:    ret i32 [[OR_LCSSA]]
1196;
1197entry:
1198  %conv = zext i1 %cmp to i32
1199  br label %loop
1200
1201loop:
1202  %iv = phi i32 [ 1, %entry ], [ %inc, %loop ]
1203  %or13 = phi i32 [ 0, %entry ], [ %or, %loop ]
1204  %and = and i32 %or13, 1
1205  %or = or i32 %and, %conv
1206  %inc = add i32 %iv, 1
1207  %ec = icmp eq i32 %iv, 16
1208  br i1 %ec, label %exit, label %loop
1209
1210exit:
1211  ret i32 %or
1212}
1213
1214declare void @llvm.assume(i1 noundef) #0
1215
1216attributes #0 = { "target-cpu"="penryn" }
1217attributes #1 = { "target-features"="+avx512bw,+avx512cd,+avx512dq,+avx512f,+avx512vl" }
1218attributes #2 = { "target-cpu"="znver3" }
1219