1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 2; RUN: opt < %s -passes=loop-vectorize -S | FileCheck %s 3 4; This is a bugpoint reduction of a test from PR43582: 5; https://bugs.llvm.org/show_bug.cgi?id=43582 6 7; ...but it's over-simplifying the underlying question: 8; TODO: Should this be vectorized rather than allowing the backend to load combine? 9; The original code is a bswap pattern. 10 11target datalayout = "e-m:w-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" 12target triple = "x86_64-w64-windows-gnu" 13 14define void @cff_index_load_offsets(i1 %cond, i8 %x, ptr %p) #0 { 15; CHECK-LABEL: @cff_index_load_offsets( 16; CHECK-NEXT: entry: 17; CHECK-NEXT: br i1 [[COND:%.*]], label [[IF_THEN:%.*]], label [[EXIT:%.*]] 18; CHECK: if.then: 19; CHECK-NEXT: br label [[FOR_BODY68:%.*]] 20; CHECK: for.body68: 21; CHECK-NEXT: [[P_359:%.*]] = phi ptr [ [[ADD_PTR86:%.*]], [[FOR_BODY68]] ], [ null, [[IF_THEN]] ] 22; CHECK-NEXT: [[CONV70:%.*]] = zext i8 [[X:%.*]] to i32 23; CHECK-NEXT: [[SHL71:%.*]] = shl nuw i32 [[CONV70]], 24 24; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[P:%.*]], align 1, !tbaa [[TBAA1:![0-9]+]] 25; CHECK-NEXT: [[CONV73:%.*]] = zext i8 [[TMP0]] to i32 26; CHECK-NEXT: [[SHL74:%.*]] = shl nuw nsw i32 [[CONV73]], 16 27; CHECK-NEXT: [[OR75:%.*]] = or i32 [[SHL74]], [[SHL71]] 28; CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr undef, align 1, !tbaa [[TBAA1]] 29; CHECK-NEXT: [[SHL78:%.*]] = shl nuw nsw i32 undef, 8 30; CHECK-NEXT: [[OR79:%.*]] = or i32 [[OR75]], [[SHL78]] 31; CHECK-NEXT: [[CONV81:%.*]] = zext i8 [[TMP1]] to i32 32; CHECK-NEXT: [[OR83:%.*]] = or i32 [[OR79]], [[CONV81]] 33; CHECK-NEXT: store i32 [[OR83]], ptr undef, align 4, !tbaa [[TBAA4:![0-9]+]] 34; CHECK-NEXT: [[ADD_PTR86]] = getelementptr inbounds i8, ptr [[P_359]], i64 4 35; CHECK-NEXT: [[CMP66:%.*]] = icmp ult ptr [[ADD_PTR86]], undef 36; CHECK-NEXT: br i1 [[CMP66]], label [[FOR_BODY68]], label [[SW_EPILOG:%.*]] 37; CHECK: sw.epilog: 38; CHECK-NEXT: unreachable 39; CHECK: Exit: 40; CHECK-NEXT: ret void 41; 42entry: 43 br i1 %cond, label %if.then, label %Exit 44 45if.then: ; preds = %entry 46 br label %for.body68 47 48for.body68: ; preds = %for.body68, %if.then 49 %p.359 = phi ptr [ %add.ptr86, %for.body68 ], [ null, %if.then ] 50 %conv70 = zext i8 %x to i32 51 %shl71 = shl nuw i32 %conv70, 24 52 %0 = load i8, ptr %p, align 1, !tbaa !1 53 %conv73 = zext i8 %0 to i32 54 %shl74 = shl nuw nsw i32 %conv73, 16 55 %or75 = or i32 %shl74, %shl71 56 %1 = load i8, ptr undef, align 1, !tbaa !1 57 %shl78 = shl nuw nsw i32 undef, 8 58 %or79 = or i32 %or75, %shl78 59 %conv81 = zext i8 %1 to i32 60 %or83 = or i32 %or79, %conv81 61 store i32 %or83, ptr undef, align 4, !tbaa !4 62 %add.ptr86 = getelementptr inbounds i8, ptr %p.359, i64 4 63 %cmp66 = icmp ult ptr %add.ptr86, undef 64 br i1 %cmp66, label %for.body68, label %sw.epilog 65 66sw.epilog: ; preds = %for.body68 67 unreachable 68 69Exit: ; preds = %entry 70 ret void 71} 72 73attributes #0 = { "use-soft-float"="false" } 74 75!llvm.ident = !{!0} 76 77!0 = !{!"clang version 10.0.0 (https://github.com/llvm/llvm-project.git 0fedc26a0dc0066f3968b9fea6a4e1f746c8d5a4)"} 78!1 = !{!2, !2, i64 0} 79!2 = !{!"omnipotent char", !3, i64 0} 80!3 = !{!"Simple C/C++ TBAA"} 81!4 = !{!5, !5, i64 0} 82!5 = !{!"long", !2, i64 0} 83