1; REQUIRES: asserts 2; RUN: opt < %s -aa-pipeline=basic-aa -passes=loop-vectorize,instcombine -S -debug-only=loop-vectorize -disable-output -print-after=instcombine 2>&1 | FileCheck %s 3; RUN: opt < %s -passes=loop-vectorize -force-vector-width=2 -S | FileCheck %s -check-prefix=FORCE 4 5target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" 6target triple = "x86_64-unknown-linux-gnu" 7 8; CHECK-LABEL: PR31671 9; 10; Check a pointer in which one of its uses is consecutive-like and another of 11; its uses is non-consecutive-like. In the test case below, %tmp3 is the 12; pointer operand of an interleaved load, making it consecutive-like. However, 13; it is also the pointer operand of a non-interleaved store that will become a 14; scatter operation. %tmp3 (and the induction variable) should not be marked 15; uniform-after-vectorization. 16; 17; CHECK: LV: Found uniform instruction: %tmp0 = getelementptr inbounds %data, ptr %d, i64 0, i32 3, i64 %i 18; CHECK-NOT: LV: Found uniform instruction: %tmp3 = getelementptr inbounds %data, ptr %d, i64 0, i32 0, i64 %i 19; CHECK-NOT: LV: Found uniform instruction: %i = phi i64 [ %i.next, %for.body ], [ 0, %entry ] 20; CHECK-NOT: LV: Found uniform instruction: %i.next = add nuw nsw i64 %i, 5 21; CHECK: define void @PR31671( 22; CHECK: vector.ph: 23; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <16 x float> poison, float %x, i64 0 24; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <16 x float> [[BROADCAST_SPLATINSERT]], <16 x float> poison, <16 x i32> zeroinitializer 25; CHECK-NEXT: br label %vector.body 26; CHECK: vector.body: 27; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %vector.ph ], [ [[INDEX_NEXT:%.*]], %vector.body ] 28; CHECK-NEXT: [[VEC_IND:%.*]] = phi <16 x i64> [ <i64 0, i64 5, i64 10, i64 15, i64 20, i64 25, i64 30, i64 35, i64 40, i64 45, i64 50, i64 55, i64 60, i64 65, i64 70, i64 75>, %vector.ph ], [ [[VEC_IND_NEXT:%.*]], %vector.body ] 29; CHECK-NEXT: [[OFFSET_IDX:%.*]] = mul i64 [[INDEX]], 5 30; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds %data, ptr %d, i64 0, i32 3, i64 [[OFFSET_IDX]] 31; CHECK-NEXT: [[WIDE_VEC:%.*]] = load <80 x float>, ptr [[TMP0]], align 4 32; CHECK-NEXT: [[STRIDED_VEC:%.*]] = shufflevector <80 x float> [[WIDE_VEC]], <80 x float> poison, <16 x i32> <i32 0, i32 5, i32 10, i32 15, i32 20, i32 25, i32 30, i32 35, i32 40, i32 45, i32 50, i32 55, i32 60, i32 65, i32 70, i32 75> 33; CHECK-NEXT: [[TMP2:%.*]] = fmul <16 x float> [[BROADCAST_SPLAT]], [[STRIDED_VEC]] 34; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds %data, ptr %d, i64 0, i32 0, <16 x i64> [[VEC_IND]] 35; CHECK-NEXT: [[TMP4:%.*]] = extractelement <16 x ptr> [[TMP3]], i64 0 36; CHECK-NEXT: [[WIDE_VEC1:%.*]] = load <80 x float>, ptr [[TMP4]], align 4 37; CHECK-NEXT: [[STRIDED_VEC2:%.*]] = shufflevector <80 x float> [[WIDE_VEC1]], <80 x float> poison, <16 x i32> <i32 0, i32 5, i32 10, i32 15, i32 20, i32 25, i32 30, i32 35, i32 40, i32 45, i32 50, i32 55, i32 60, i32 65, i32 70, i32 75> 38; CHECK-NEXT: [[TMP5:%.*]] = fadd <16 x float> [[STRIDED_VEC2]], [[TMP2]] 39; CHECK-NEXT: call void @llvm.masked.scatter.v16f32.v16p0(<16 x float> [[TMP5]], <16 x ptr> [[TMP3]], i32 4, <16 x i1> splat (i1 true)) 40; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16 41; CHECK-NEXT: [[VEC_IND_NEXT]] = add <16 x i64> [[VEC_IND]], splat (i64 80) 42; CHECK: br i1 {{.*}}, label %middle.block, label %vector.body 43 44%data = type { [32000 x float], [3 x i32], [4 x i8], [32000 x float] } 45 46define void @PR31671(float %x, ptr %d) #0 { 47entry: 48 br label %for.body 49 50for.body: 51 %i = phi i64 [ %i.next, %for.body ], [ 0, %entry ] 52 %tmp0 = getelementptr inbounds %data, ptr %d, i64 0, i32 3, i64 %i 53 %tmp1 = load float, ptr %tmp0, align 4 54 %tmp2 = fmul float %x, %tmp1 55 %tmp3 = getelementptr inbounds %data, ptr %d, i64 0, i32 0, i64 %i 56 %tmp4 = load float, ptr %tmp3, align 4 57 %tmp5 = fadd float %tmp4, %tmp2 58 store float %tmp5, ptr %tmp3, align 4 59 %i.next = add nuw nsw i64 %i, 5 60 %cond = icmp slt i64 %i.next, 32000 61 br i1 %cond, label %for.body, label %for.end 62 63for.end: 64 ret void 65} 66 67attributes #0 = { "target-cpu"="knl" } 68 69; CHECK-LABEL: PR40816 70; 71; Check that scalar with predication instructions are not considered uniform 72; after vectorization, because that results in replicating a region instead of 73; having a single instance (out of VF). The predication stems from a tiny count 74; of 3 leading to folding the tail by masking using icmp ule <i, i+1> <= <2, 2>. 75; 76; CHECK: LV: Found trip count: 3 77; CHECK: LV: Found uniform instruction: {{%.*}} = icmp eq i32 {{%.*}}, 0 78; CHECK-NOT: LV: Found uniform instruction: {{%.*}} = load i32, ptr {{%.*}}, align 1 79; CHECK: LV: Found not uniform due to requiring predication: {{%.*}} = load i32, ptr {{%.*}}, align 1 80; CHECK: LV: Found scalar instruction: {{%.*}} = getelementptr inbounds [3 x i32], ptr @a, i32 0, i32 {{%.*}} 81; 82; FORCE-LABEL: @PR40816( 83; FORCE-NEXT: entry: 84; FORCE-NEXT: br i1 false, label {{%.*}}, label [[VECTOR_PH:%.*]] 85; FORCE: vector.ph: 86; FORCE-NEXT: br label [[VECTOR_BODY:%.*]] 87; FORCE: vector.body: 88; FORCE-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[PRED_STORE_CONTINUE4:%.*]] ] 89; FORCE-NEXT: [[VEC_IND:%.*]] = phi <2 x i32> [ <i32 0, i32 1>, [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[PRED_STORE_CONTINUE4]] ] 90; FORCE-NEXT: [[TMP2:%.*]] = icmp ule <2 x i32> [[VEC_IND]], splat (i32 2) 91; FORCE-NEXT: [[TMP3:%.*]] = extractelement <2 x i1> [[TMP2]], i32 0 92; FORCE-NEXT: br i1 [[TMP3]], label [[PRED_STORE_IF:%.*]], label [[PRED_STORE_CONTINUE:%.*]] 93; FORCE: pred.store.if: 94; FORCE-NEXT: [[TMP0:%.*]] = add i32 [[INDEX]], 0 95; FORCE-NEXT: store i32 [[TMP0]], ptr @b, align 1 96; FORCE-NEXT: br label [[PRED_STORE_CONTINUE]] 97; FORCE: pred.store.continue: 98; FORCE-NEXT: [[TMP10:%.*]] = extractelement <2 x i1> [[TMP2]], i32 1 99; FORCE-NEXT: br i1 [[TMP10]], label [[PRED_STORE_IF3:%.*]], label [[PRED_STORE_CONTINUE4]] 100; FORCE: pred.store.if1: 101; FORCE-NEXT: [[TMP1:%.*]] = add i32 [[INDEX]], 1 102; FORCE-NEXT: store i32 [[TMP1]], ptr @b, align 1 103; FORCE-NEXT: br label [[PRED_STORE_CONTINUE4]] 104; FORCE: pred.store.continue2: 105; FORCE-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 2 106; FORCE-NEXT: [[VEC_IND_NEXT]] = add <2 x i32> [[VEC_IND]], splat (i32 2) 107; FORCE-NEXT: [[TMP15:%.*]] = icmp eq i32 [[INDEX_NEXT]], 4 108; FORCE-NEXT: br i1 [[TMP15]], label {{%.*}}, label [[VECTOR_BODY]] 109; 110@a = internal constant [3 x i32] [i32 7, i32 7, i32 0], align 1 111@b = external global i32, align 1 112 113define void @PR40816() #1 { 114 115entry: 116 br label %for.body 117 118for.body: ; preds = %for.body, %entry 119 %0 = phi i32 [ 0, %entry ], [ %inc, %for.body ] 120 store i32 %0, ptr @b, align 1 121 %arrayidx1 = getelementptr inbounds [3 x i32], ptr @a, i32 0, i32 %0 122 %1 = load i32, ptr %arrayidx1, align 1 123 %cmp2 = icmp eq i32 %1, 0 124 %inc = add nuw nsw i32 %0, 1 125 br i1 %cmp2, label %return, label %for.body 126 127return: ; preds = %for.body 128 ret void 129} 130 131attributes #1 = { "target-cpu"="core2" } 132