1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 2; RUN: opt < %s -passes=loop-vectorize -mtriple riscv64-linux-gnu -mattr=+v,+f -S 2>%t | FileCheck %s 3 4; This is a collection of tests whose only purpose is to show changes in the 5; default configuration. Please keep these tests minimal - if you're testing 6; functionality of some specific configuration, please place that in a 7; separate test file with a hard coded configuration (even if that 8; configuration is the current default). 9 10target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n64-S128" 11target triple = "riscv64" 12 13define void @vector_add(ptr noalias nocapture %a, i64 %v) { 14; CHECK-LABEL: @vector_add( 15; CHECK-NEXT: entry: 16; CHECK-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64() 17; CHECK-NEXT: [[TMP1:%.*]] = mul i64 [[TMP0]], 2 18; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 1024, [[TMP1]] 19; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] 20; CHECK: vector.ph: 21; CHECK-NEXT: [[TMP2:%.*]] = call i64 @llvm.vscale.i64() 22; CHECK-NEXT: [[TMP3:%.*]] = mul i64 [[TMP2]], 2 23; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 1024, [[TMP3]] 24; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 1024, [[N_MOD_VF]] 25; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.vscale.i64() 26; CHECK-NEXT: [[TMP5:%.*]] = mul i64 [[TMP4]], 2 27; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 2 x i64> poison, i64 [[V:%.*]], i64 0 28; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <vscale x 2 x i64> [[BROADCAST_SPLATINSERT]], <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer 29; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] 30; CHECK: vector.body: 31; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] 32; CHECK-NEXT: [[TMP6:%.*]] = add i64 [[INDEX]], 0 33; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds i64, ptr [[A:%.*]], i64 [[TMP6]] 34; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds i64, ptr [[TMP7]], i32 0 35; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 2 x i64>, ptr [[TMP8]], align 8 36; CHECK-NEXT: [[TMP9:%.*]] = add <vscale x 2 x i64> [[WIDE_LOAD]], [[BROADCAST_SPLAT]] 37; CHECK-NEXT: store <vscale x 2 x i64> [[TMP9]], ptr [[TMP8]], align 8 38; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP5]] 39; CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] 40; CHECK-NEXT: br i1 [[TMP10]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] 41; CHECK: middle.block: 42; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 1024, [[N_VEC]] 43; CHECK-NEXT: br i1 [[CMP_N]], label [[FOR_END:%.*]], label [[SCALAR_PH]] 44; CHECK: scalar.ph: 45; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ] 46; CHECK-NEXT: br label [[FOR_BODY:%.*]] 47; CHECK: for.body: 48; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[FOR_BODY]] ] 49; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[IV]] 50; CHECK-NEXT: [[ELEM:%.*]] = load i64, ptr [[ARRAYIDX]], align 8 51; CHECK-NEXT: [[ADD:%.*]] = add i64 [[ELEM]], [[V]] 52; CHECK-NEXT: store i64 [[ADD]], ptr [[ARRAYIDX]], align 8 53; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1 54; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], 1024 55; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label [[FOR_END]], label [[FOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]] 56; CHECK: for.end: 57; CHECK-NEXT: ret void 58; 59entry: 60 br label %for.body 61 62for.body: 63 %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ] 64 %arrayidx = getelementptr inbounds i64, ptr %a, i64 %iv 65 %elem = load i64, ptr %arrayidx 66 %add = add i64 %elem, %v 67 store i64 %add, ptr %arrayidx 68 %iv.next = add nuw nsw i64 %iv, 1 69 %exitcond.not = icmp eq i64 %iv.next, 1024 70 br i1 %exitcond.not, label %for.end, label %for.body 71 72for.end: 73 ret void 74} 75 76define i64 @vector_add_reduce(ptr noalias nocapture %a) { 77; CHECK-LABEL: @vector_add_reduce( 78; CHECK-NEXT: entry: 79; CHECK-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64() 80; CHECK-NEXT: [[TMP1:%.*]] = mul i64 [[TMP0]], 2 81; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 1024, [[TMP1]] 82; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] 83; CHECK: vector.ph: 84; CHECK-NEXT: [[TMP2:%.*]] = call i64 @llvm.vscale.i64() 85; CHECK-NEXT: [[TMP3:%.*]] = mul i64 [[TMP2]], 2 86; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 1024, [[TMP3]] 87; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 1024, [[N_MOD_VF]] 88; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.vscale.i64() 89; CHECK-NEXT: [[TMP5:%.*]] = mul i64 [[TMP4]], 2 90; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] 91; CHECK: vector.body: 92; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] 93; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <vscale x 2 x i64> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP9:%.*]], [[VECTOR_BODY]] ] 94; CHECK-NEXT: [[TMP6:%.*]] = add i64 [[INDEX]], 0 95; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds i64, ptr [[A:%.*]], i64 [[TMP6]] 96; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds i64, ptr [[TMP7]], i32 0 97; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 2 x i64>, ptr [[TMP8]], align 8 98; CHECK-NEXT: [[TMP9]] = add <vscale x 2 x i64> [[VEC_PHI]], [[WIDE_LOAD]] 99; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP5]] 100; CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] 101; CHECK-NEXT: br i1 [[TMP10]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]] 102; CHECK: middle.block: 103; CHECK-NEXT: [[TMP11:%.*]] = call i64 @llvm.vector.reduce.add.nxv2i64(<vscale x 2 x i64> [[TMP9]]) 104; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 1024, [[N_VEC]] 105; CHECK-NEXT: br i1 [[CMP_N]], label [[FOR_END:%.*]], label [[SCALAR_PH]] 106; CHECK: scalar.ph: 107; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ] 108; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i64 [ [[TMP11]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY]] ] 109; CHECK-NEXT: br label [[FOR_BODY:%.*]] 110; CHECK: for.body: 111; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[FOR_BODY]] ] 112; CHECK-NEXT: [[SUM:%.*]] = phi i64 [ [[BC_MERGE_RDX]], [[SCALAR_PH]] ], [ [[SUM_NEXT:%.*]], [[FOR_BODY]] ] 113; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[IV]] 114; CHECK-NEXT: [[ELEM:%.*]] = load i64, ptr [[ARRAYIDX]], align 8 115; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1 116; CHECK-NEXT: [[SUM_NEXT]] = add i64 [[SUM]], [[ELEM]] 117; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], 1024 118; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label [[FOR_END]], label [[FOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]] 119; CHECK: for.end: 120; CHECK-NEXT: [[SUM_NEXT_LCSSA:%.*]] = phi i64 [ [[SUM_NEXT]], [[FOR_BODY]] ], [ [[TMP11]], [[MIDDLE_BLOCK]] ] 121; CHECK-NEXT: ret i64 [[SUM_NEXT_LCSSA]] 122; 123entry: 124 br label %for.body 125 126for.body: 127 %iv = phi i64 [0, %entry], [%iv.next, %for.body] 128 %sum = phi i64 [0, %entry], [%sum.next, %for.body] 129 %arrayidx = getelementptr inbounds i64, ptr %a, i64 %iv 130 %elem = load i64, ptr %arrayidx 131 %iv.next = add nuw nsw i64 %iv, 1 132 %sum.next = add i64 %sum, %elem 133 %exitcond.not = icmp eq i64 %iv.next, 1024 134 br i1 %exitcond.not, label %for.end, label %for.body 135 136for.end: 137 ret i64 %sum.next 138} 139 140