1; RUN: opt -passes=loop-vectorize,dce,instcombine -mtriple aarch64-linux-gnu -mattr=+sve \ 2; RUN: -prefer-predicate-over-epilogue=scalar-epilogue < %s -S | FileCheck %s 3 4 5target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" 6target triple = "aarch64-unknown-linux-gnu" 7 8define void @cmpsel_i32(ptr noalias nocapture %a, ptr noalias nocapture readonly %b, i64 %n) { 9; CHECK-LABEL: @cmpsel_i32( 10; CHECK-NEXT: entry: 11; CHECK: vector.body: 12; CHECK: [[WIDE_LOAD:%.*]] = load <vscale x 4 x i32>, ptr {{.*}}, align 4 13; CHECK-NEXT: [[TMP1:%.*]] = icmp eq <vscale x 4 x i32> [[WIDE_LOAD]], zeroinitializer 14; CHECK-NEXT: [[TMP2:%.*]] = select <vscale x 4 x i1> [[TMP1]], <vscale x 4 x i32> splat (i32 2), <vscale x 4 x i32> splat (i32 10) 15; CHECK: store <vscale x 4 x i32> [[TMP2]], ptr {{.*}}, align 4 16; 17entry: 18 br label %for.body 19 20for.body: ; preds = %entry, %for.body 21 %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ] 22 %arrayidx = getelementptr inbounds i32, ptr %b, i64 %indvars.iv 23 %0 = load i32, ptr %arrayidx, align 4 24 %tobool.not = icmp eq i32 %0, 0 25 %cond = select i1 %tobool.not, i32 2, i32 10 26 %arrayidx2 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv 27 store i32 %cond, ptr %arrayidx2, align 4 28 %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 29 %exitcond.not = icmp eq i64 %indvars.iv.next, %n 30 br i1 %exitcond.not, label %for.end.loopexit, label %for.body, !llvm.loop !0 31 32for.end.loopexit: ; preds = %for.body 33 br label %for.end 34 35for.end: ; preds = %for.end.loopexit, %entry 36 ret void 37} 38 39define void @cmpsel_f32(ptr noalias nocapture %a, ptr noalias nocapture readonly %b, i64 %n) { 40; CHECK-LABEL: @cmpsel_f32( 41; CHECK-NEXT: entry: 42; CHECK: vector.body: 43; CHECK: [[WIDE_LOAD:%.*]] = load <vscale x 4 x float>, ptr {{.*}}, align 4 44; CHECK-NEXT: [[TMP1:%.*]] = fcmp ogt <vscale x 4 x float> [[WIDE_LOAD]], splat (float 3.000000e+00) 45; CHECK-NEXT: [[TMP2:%.*]] = select <vscale x 4 x i1> [[TMP1]], <vscale x 4 x float> splat (float 1.000000e+01), <vscale x 4 x float> splat (float 2.000000e+00) 46; CHECK: store <vscale x 4 x float> [[TMP2]], ptr {{.*}}, align 4 47 48entry: 49 br label %for.body 50 51for.body: ; preds = %entry, %for.body 52 %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ] 53 %arrayidx = getelementptr inbounds float, ptr %b, i64 %indvars.iv 54 %0 = load float, ptr %arrayidx, align 4 55 %cmp1 = fcmp ogt float %0, 3.000000e+00 56 %conv = select i1 %cmp1, float 1.000000e+01, float 2.000000e+00 57 %arrayidx3 = getelementptr inbounds float, ptr %a, i64 %indvars.iv 58 store float %conv, ptr %arrayidx3, align 4 59 %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 60 %exitcond.not = icmp eq i64 %indvars.iv.next, %n 61 br i1 %exitcond.not, label %for.end, label %for.body, !llvm.loop !0 62 63for.end: ; preds = %for.body, %entry 64 ret void 65} 66 67define void @fneg_f32(ptr noalias nocapture %a, ptr noalias nocapture readonly %b, i64 %n) { 68; CHECK-LABEL: @fneg_f32( 69; CHECK-NEXT: entry: 70; CHECK: vector.body: 71; CHECK: [[WIDE_LOAD:%.*]] = load <vscale x 4 x float>, ptr {{.*}}, align 4 72; CHECK-NEXT: [[TMP1:%.*]] = fneg <vscale x 4 x float> [[WIDE_LOAD]] 73; CHECK: store <vscale x 4 x float> [[TMP1]], ptr {{.*}}, align 4 74 75entry: 76 br label %for.body 77 78for.body: ; preds = %entry, %for.body 79 %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ] 80 %arrayidx = getelementptr inbounds float, ptr %b, i64 %indvars.iv 81 %0 = load float, ptr %arrayidx, align 4 82 %fneg = fneg float %0 83 %arrayidx3 = getelementptr inbounds float, ptr %a, i64 %indvars.iv 84 store float %fneg, ptr %arrayidx3, align 4 85 %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 86 %exitcond.not = icmp eq i64 %indvars.iv.next, %n 87 br i1 %exitcond.not, label %for.end, label %for.body, !llvm.loop !0 88 89for.end: ; preds = %for.body, %entry 90 ret void 91} 92 93!0 = distinct !{!0, !1, !2, !3, !4, !5} 94!1 = !{!"llvm.loop.mustprogress"} 95!2 = !{!"llvm.loop.vectorize.width", i32 4} 96!3 = !{!"llvm.loop.vectorize.scalable.enable", i1 true} 97!4 = !{!"llvm.loop.interleave.count", i32 1} 98!5 = !{!"llvm.loop.vectorize.enable", i1 true} 99