xref: /llvm-project/llvm/test/Transforms/LoopVectorize/AArch64/i1-reg-usage.ll (revision be51fa4580b3274d35cc77bedb238a9ad5fb04bc)
1; RUN: opt -passes=loop-vectorize -debug-only=loop-vectorize -disable-output -prefer-predicate-over-epilogue=scalar-epilogue 2>&1 < %s | FileCheck %s
2; REQUIRES: asserts
3
4target triple = "aarch64"
5
6; Test that shows how many registers the loop vectorizer thinks an illegal <VF x i1> will consume.
7
8; CHECK-LABEL: LV: Checking a loop in 'or_reduction_neon' from <stdin>
9; CHECK: LV(REG): VF = 32
10; CHECK-NEXT: LV(REG): Found max usage: 2 item
11; CHECK-NEXT: LV(REG): RegisterClass: Generic::VectorRC, 72 registers
12; CHECK-NEXT: LV(REG): RegisterClass: Generic::ScalarRC, 1 registers
13
14define i1 @or_reduction_neon(i32 %arg, ptr %ptr) {
15entry:
16  br label %loop
17exit:
18  ret i1 %reduction_next
19loop:
20  %induction = phi i32 [ 0, %entry ], [ %induction_next, %loop ]
21  %reduction = phi i1 [ 0, %entry ], [ %reduction_next, %loop ]
22  %gep = getelementptr inbounds i32, ptr %ptr, i32 %induction
23  %loaded = load i32, ptr %gep
24  %i1 = icmp eq i32 %loaded, %induction
25  %reduction_next = or i1 %i1, %reduction
26  %induction_next = add nuw i32 %induction, 1
27  %cond = icmp eq i32 %induction_next, %arg
28  br i1 %cond, label %exit, label %loop, !llvm.loop !32
29}
30
31; CHECK-LABEL: LV: Checking a loop in 'or_reduction_sve'
32; CHECK: LV(REG): VF = 64
33; CHECK-NEXT: LV(REG): Found max usage: 2 item
34; CHECK-NEXT: LV(REG): RegisterClass: Generic::VectorRC, 136 registers
35; CHECK-NEXT: LV(REG): RegisterClass: Generic::ScalarRC, 1 registers
36
37define i1 @or_reduction_sve(i32 %arg, ptr %ptr) vscale_range(2,2) "target-features"="+sve" {
38entry:
39  br label %loop
40exit:
41  ret i1 %reduction_next
42loop:
43  %induction = phi i32 [ 0, %entry ], [ %induction_next, %loop ]
44  %reduction = phi i1 [ true, %entry ], [ %reduction_next, %loop ]
45  %gep = getelementptr inbounds i32, ptr %ptr, i32 %induction
46  %loaded = load i32, ptr %gep
47  %i1 = icmp eq i32 %loaded, %induction
48  %reduction_next = or i1 %i1, %reduction
49  %induction_next = add nuw i32 %induction, 1
50  %cond = icmp eq i32 %induction_next, %arg
51  br i1 %cond, label %exit, label %loop, !llvm.loop !64
52}
53
54!32 = distinct !{!32, !33}
55!33 = !{!"llvm.loop.vectorize.width", i32 32}
56!64 = distinct !{!64, !65}
57!65 = !{!"llvm.loop.vectorize.width", i32 64}
58