1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 2; RUN: opt -passes='loop-unroll<runtime;partial>' -S %s | FileCheck %s 3 4target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-ni:1-p2:32:8:8:32-ni:2" 5 6; Make sure SCEVs for phis are properly invalidated after phis are modified. 7 8declare void @llvm.experimental.deoptimize.isVoid(...) 9 10declare i32 @get() 11 12define void @pr56282() { 13; CHECK-LABEL: @pr56282( 14; CHECK-NEXT: entry: 15; CHECK-NEXT: br label [[OUTER_HEADER:%.*]] 16; CHECK: outer.header: 17; CHECK-NEXT: [[OUTER_IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[OUTER_IV_NEXT:%.*]], [[INNER_2:%.*]] ] 18; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[OUTER_IV]], 1 19; CHECK-NEXT: [[TMP1:%.*]] = freeze i64 [[TMP0]] 20; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[TMP1]], -1 21; CHECK-NEXT: [[XTRAITER:%.*]] = and i64 [[TMP1]], 7 22; CHECK-NEXT: [[TMP3:%.*]] = icmp ult i64 [[TMP2]], 7 23; CHECK-NEXT: br i1 [[TMP3]], label [[OUTER_MIDDLE_UNR_LCSSA:%.*]], label [[OUTER_HEADER_NEW:%.*]] 24; CHECK: outer.header.new: 25; CHECK-NEXT: [[UNROLL_ITER:%.*]] = sub i64 [[TMP1]], [[XTRAITER]] 26; CHECK-NEXT: br label [[INNER_1_HEADER:%.*]] 27; CHECK: inner.1.header: 28; CHECK-NEXT: [[INNER_1_IV:%.*]] = phi i64 [ 0, [[OUTER_HEADER_NEW]] ], [ [[INNER_1_IV_NEXT_7:%.*]], [[INNER_1_LATCH_7:%.*]] ] 29; CHECK-NEXT: [[NITER:%.*]] = phi i64 [ 0, [[OUTER_HEADER_NEW]] ], [ [[NITER_NEXT_7:%.*]], [[INNER_1_LATCH_7]] ] 30; CHECK-NEXT: [[V:%.*]] = call i32 @get() 31; CHECK-NEXT: [[C_1:%.*]] = icmp ugt i32 [[V]], 0 32; CHECK-NEXT: br i1 [[C_1]], label [[INNER_1_LATCH:%.*]], label [[EXIT_DEOPT_LOOPEXIT:%.*]] 33; CHECK: inner.1.latch: 34; CHECK-NEXT: [[V_1:%.*]] = call i32 @get() 35; CHECK-NEXT: [[C_1_1:%.*]] = icmp ugt i32 [[V_1]], 0 36; CHECK-NEXT: br i1 [[C_1_1]], label [[INNER_1_LATCH_1:%.*]], label [[EXIT_DEOPT_LOOPEXIT]] 37; CHECK: inner.1.latch.1: 38; CHECK-NEXT: [[V_2:%.*]] = call i32 @get() 39; CHECK-NEXT: [[C_1_2:%.*]] = icmp ugt i32 [[V_2]], 0 40; CHECK-NEXT: br i1 [[C_1_2]], label [[INNER_1_LATCH_2:%.*]], label [[EXIT_DEOPT_LOOPEXIT]] 41; CHECK: inner.1.latch.2: 42; CHECK-NEXT: [[V_3:%.*]] = call i32 @get() 43; CHECK-NEXT: [[C_1_3:%.*]] = icmp ugt i32 [[V_3]], 0 44; CHECK-NEXT: br i1 [[C_1_3]], label [[INNER_1_LATCH_3:%.*]], label [[EXIT_DEOPT_LOOPEXIT]] 45; CHECK: inner.1.latch.3: 46; CHECK-NEXT: [[V_4:%.*]] = call i32 @get() 47; CHECK-NEXT: [[C_1_4:%.*]] = icmp ugt i32 [[V_4]], 0 48; CHECK-NEXT: br i1 [[C_1_4]], label [[INNER_1_LATCH_4:%.*]], label [[EXIT_DEOPT_LOOPEXIT]] 49; CHECK: inner.1.latch.4: 50; CHECK-NEXT: [[V_5:%.*]] = call i32 @get() 51; CHECK-NEXT: [[C_1_5:%.*]] = icmp ugt i32 [[V_5]], 0 52; CHECK-NEXT: br i1 [[C_1_5]], label [[INNER_1_LATCH_5:%.*]], label [[EXIT_DEOPT_LOOPEXIT]] 53; CHECK: inner.1.latch.5: 54; CHECK-NEXT: [[V_6:%.*]] = call i32 @get() 55; CHECK-NEXT: [[C_1_6:%.*]] = icmp ugt i32 [[V_6]], 0 56; CHECK-NEXT: br i1 [[C_1_6]], label [[INNER_1_LATCH_6:%.*]], label [[EXIT_DEOPT_LOOPEXIT]] 57; CHECK: inner.1.latch.6: 58; CHECK-NEXT: [[INNER_1_IV_NEXT_7]] = add nuw nsw i64 [[INNER_1_IV]], 8 59; CHECK-NEXT: [[V_7:%.*]] = call i32 @get() 60; CHECK-NEXT: [[C_1_7:%.*]] = icmp ugt i32 [[V_7]], 0 61; CHECK-NEXT: br i1 [[C_1_7]], label [[INNER_1_LATCH_7]], label [[EXIT_DEOPT_LOOPEXIT]] 62; CHECK: inner.1.latch.7: 63; CHECK-NEXT: [[NITER_NEXT_7]] = add i64 [[NITER]], 8 64; CHECK-NEXT: [[NITER_NCMP_7:%.*]] = icmp ne i64 [[NITER_NEXT_7]], [[UNROLL_ITER]] 65; CHECK-NEXT: br i1 [[NITER_NCMP_7]], label [[INNER_1_HEADER]], label [[OUTER_MIDDLE_UNR_LCSSA_LOOPEXIT:%.*]] 66; CHECK: outer.middle.unr-lcssa.loopexit: 67; CHECK-NEXT: [[V_LCSSA1_PH_PH:%.*]] = phi i32 [ [[V_7]], [[INNER_1_LATCH_7]] ] 68; CHECK-NEXT: [[INNER_1_IV_UNR_PH:%.*]] = phi i64 [ [[INNER_1_IV_NEXT_7]], [[INNER_1_LATCH_7]] ] 69; CHECK-NEXT: br label [[OUTER_MIDDLE_UNR_LCSSA]] 70; CHECK: outer.middle.unr-lcssa: 71; CHECK-NEXT: [[V_LCSSA1_PH:%.*]] = phi i32 [ poison, [[OUTER_HEADER]] ], [ [[V_LCSSA1_PH_PH]], [[OUTER_MIDDLE_UNR_LCSSA_LOOPEXIT]] ] 72; CHECK-NEXT: [[INNER_1_IV_UNR:%.*]] = phi i64 [ 0, [[OUTER_HEADER]] ], [ [[INNER_1_IV_UNR_PH]], [[OUTER_MIDDLE_UNR_LCSSA_LOOPEXIT]] ] 73; CHECK-NEXT: [[LCMP_MOD:%.*]] = icmp ne i64 [[XTRAITER]], 0 74; CHECK-NEXT: br i1 [[LCMP_MOD]], label [[INNER_1_HEADER_EPIL_PREHEADER:%.*]], label [[OUTER_MIDDLE:%.*]] 75; CHECK: inner.1.header.epil.preheader: 76; CHECK-NEXT: br label [[INNER_1_HEADER_EPIL:%.*]] 77; CHECK: inner.1.header.epil: 78; CHECK-NEXT: [[INNER_1_IV_EPIL:%.*]] = phi i64 [ [[INNER_1_IV_UNR]], [[INNER_1_HEADER_EPIL_PREHEADER]] ], [ [[INNER_1_IV_NEXT_EPIL:%.*]], [[INNER_1_LATCH_EPIL:%.*]] ] 79; CHECK-NEXT: [[EPIL_ITER:%.*]] = phi i64 [ 0, [[INNER_1_HEADER_EPIL_PREHEADER]] ], [ [[EPIL_ITER_NEXT:%.*]], [[INNER_1_LATCH_EPIL]] ] 80; CHECK-NEXT: [[INNER_1_IV_NEXT_EPIL]] = add nuw nsw i64 [[INNER_1_IV_EPIL]], 1 81; CHECK-NEXT: [[V_EPIL:%.*]] = call i32 @get() 82; CHECK-NEXT: [[C_1_EPIL:%.*]] = icmp ugt i32 [[V_EPIL]], 0 83; CHECK-NEXT: br i1 [[C_1_EPIL]], label [[INNER_1_LATCH_EPIL]], label [[EXIT_DEOPT_LOOPEXIT3:%.*]] 84; CHECK: inner.1.latch.epil: 85; CHECK-NEXT: [[C_2_EPIL:%.*]] = icmp ult i64 [[INNER_1_IV_EPIL]], [[OUTER_IV]] 86; CHECK-NEXT: [[EPIL_ITER_NEXT]] = add i64 [[EPIL_ITER]], 1 87; CHECK-NEXT: [[EPIL_ITER_CMP:%.*]] = icmp ne i64 [[EPIL_ITER_NEXT]], [[XTRAITER]] 88; CHECK-NEXT: br i1 [[EPIL_ITER_CMP]], label [[INNER_1_HEADER_EPIL]], label [[OUTER_MIDDLE_EPILOG_LCSSA:%.*]], !llvm.loop [[LOOP0:![0-9]+]] 89; CHECK: outer.middle.epilog-lcssa: 90; CHECK-NEXT: [[V_LCSSA1_PH2:%.*]] = phi i32 [ [[V_EPIL]], [[INNER_1_LATCH_EPIL]] ] 91; CHECK-NEXT: br label [[OUTER_MIDDLE]] 92; CHECK: outer.middle: 93; CHECK-NEXT: [[V_LCSSA1:%.*]] = phi i32 [ [[V_LCSSA1_PH]], [[OUTER_MIDDLE_UNR_LCSSA]] ], [ [[V_LCSSA1_PH2]], [[OUTER_MIDDLE_EPILOG_LCSSA]] ] 94; CHECK-NEXT: [[C_3:%.*]] = icmp ugt i32 [[V_LCSSA1]], 0 95; CHECK-NEXT: br i1 [[C_3]], label [[INNER_2_PREHEADER:%.*]], label [[EXIT:%.*]] 96; CHECK: inner.2.preheader: 97; CHECK-NEXT: br label [[INNER_2]] 98; CHECK: inner.2: 99; CHECK-NEXT: [[OUTER_IV_NEXT]] = add nuw i64 [[OUTER_IV]], 1 100; CHECK-NEXT: br label [[OUTER_HEADER]] 101; CHECK: exit: 102; CHECK-NEXT: ret void 103; CHECK: exit.deopt.loopexit: 104; CHECK-NEXT: br label [[EXIT_DEOPT:%.*]] 105; CHECK: exit.deopt.loopexit3: 106; CHECK-NEXT: br label [[EXIT_DEOPT]] 107; CHECK: exit.deopt: 108; CHECK-NEXT: call void (...) @llvm.experimental.deoptimize.isVoid(i32 0) [ "deopt"() ] 109; CHECK-NEXT: ret void 110; 111entry: 112 br label %outer.header 113 114outer.header: 115 %outer.iv = phi i64 [ 0, %entry ], [ %outer.iv.next, %outer.latch ] 116 br label %inner.1.header 117 118inner.1.header: 119 %inner.1.iv = phi i64 [ 0, %outer.header ], [ %inner.1.iv.next, %inner.1.latch ] 120 %inner.1.iv.next = add nuw nsw i64 %inner.1.iv, 1 121 %v = call i32 @get() 122 %c.1 = icmp ugt i32 %v, 0 123 br i1 %c.1, label %inner.1.latch, label %exit.deopt 124 125inner.1.latch: ; preds = %inner.1.header 126 %c.2 = icmp ult i64 %inner.1.iv, %outer.iv 127 br i1 %c.2, label %inner.1.header, label %outer.middle 128 129outer.middle: 130 %c.3 = icmp ugt i32 %v, 0 131 br i1 %c.3, label %inner.2, label %exit 132 133inner.2: 134 %inner.2.iv = phi i64 [ 0, %outer.middle ], [ %inner.2.iv.next, %inner.2 ] 135 %inner.2.iv.next = add nsw i64 %inner.2.iv, -1 136 %iv.trunc = trunc i64 %inner.2.iv to i32 137 %c.4 = icmp ult i32 %v, %iv.trunc 138 br i1 %c.4, label %inner.2, label %outer.latch 139 140outer.latch: 141 %outer.iv.next = add nuw nsw i64 %outer.iv, 1 142 br label %outer.header 143 144exit: 145 ret void 146 147exit.deopt: 148 call void (...) @llvm.experimental.deoptimize.isVoid(i32 0) [ "deopt"() ] 149 ret void 150} 151 152declare void @bar() 153declare void @use.2(ptr, i32) 154 155define void @pr56286(i64 %x, ptr %src, ptr %dst, ptr %ptr.src) !prof !0 { 156; CHECK-LABEL: @pr56286( 157; CHECK-NEXT: bb: 158; CHECK-NEXT: [[SMAX:%.*]] = call i64 @llvm.smax.i64(i64 [[X:%.*]], i64 1) 159; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[SMAX]], 1 160; CHECK-NEXT: [[TMP1:%.*]] = sub i64 [[TMP0]], [[X]] 161; CHECK-NEXT: br label [[OUTER_HEADER:%.*]] 162; CHECK: outer.header: 163; CHECK-NEXT: [[OUTER_P:%.*]] = phi i32 [ 0, [[BB:%.*]] ], [ [[L_1_LCSSA:%.*]], [[OUTER_LATCH:%.*]] ] 164; CHECK-NEXT: [[TMP2:%.*]] = freeze i64 [[TMP1]] 165; CHECK-NEXT: [[TMP3:%.*]] = add i64 [[TMP2]], -1 166; CHECK-NEXT: [[XTRAITER:%.*]] = and i64 [[TMP2]], 7 167; CHECK-NEXT: [[LCMP_MOD:%.*]] = icmp ne i64 [[XTRAITER]], 0 168; CHECK-NEXT: br i1 [[LCMP_MOD]], label [[INNER_1_HEADER_PROL_PREHEADER:%.*]], label [[INNER_1_HEADER_PROL_LOOPEXIT:%.*]], !prof [[PROF3:![0-9]+]] 169; CHECK: inner.1.header.prol.preheader: 170; CHECK-NEXT: br label [[INNER_1_HEADER_PROL:%.*]] 171; CHECK: inner.1.header.prol: 172; CHECK-NEXT: [[INNER_1_IV_PROL:%.*]] = phi i64 [ [[X]], [[INNER_1_HEADER_PROL_PREHEADER]] ], [ [[INNER_1_IV_NEXT_PROL:%.*]], [[INNER_1_LATCH_PROL:%.*]] ] 173; CHECK-NEXT: [[PROL_ITER:%.*]] = phi i64 [ 0, [[INNER_1_HEADER_PROL_PREHEADER]] ], [ [[PROL_ITER_NEXT:%.*]], [[INNER_1_LATCH_PROL]] ] 174; CHECK-NEXT: [[CMP_1_PROL:%.*]] = icmp sgt i32 [[OUTER_P]], 0 175; CHECK-NEXT: br i1 [[CMP_1_PROL]], label [[EXIT_DEOPT_LOOPEXIT1:%.*]], label [[INNER_1_LATCH_PROL]] 176; CHECK: inner.1.latch.prol: 177; CHECK-NEXT: [[L_1_PROL:%.*]] = load i32, ptr [[SRC:%.*]], align 4 178; CHECK-NEXT: store i32 [[L_1_PROL]], ptr [[DST:%.*]], align 8 179; CHECK-NEXT: [[INNER_1_IV_NEXT_PROL]] = add i64 [[INNER_1_IV_PROL]], 1 180; CHECK-NEXT: [[CMP_2_PROL:%.*]] = icmp sgt i64 [[INNER_1_IV_PROL]], 0 181; CHECK-NEXT: [[PROL_ITER_NEXT]] = add i64 [[PROL_ITER]], 1 182; CHECK-NEXT: [[PROL_ITER_CMP:%.*]] = icmp ne i64 [[PROL_ITER_NEXT]], [[XTRAITER]] 183; CHECK-NEXT: br i1 [[PROL_ITER_CMP]], label [[INNER_1_HEADER_PROL]], label [[INNER_1_HEADER_PROL_LOOPEXIT_UNR_LCSSA:%.*]], !prof [[PROF4:![0-9]+]], !llvm.loop [[LOOP5:![0-9]+]] 184; CHECK: inner.1.header.prol.loopexit.unr-lcssa: 185; CHECK-NEXT: [[L_1_LCSSA_UNR_PH:%.*]] = phi i32 [ [[L_1_PROL]], [[INNER_1_LATCH_PROL]] ] 186; CHECK-NEXT: [[INNER_1_IV_UNR_PH:%.*]] = phi i64 [ [[INNER_1_IV_NEXT_PROL]], [[INNER_1_LATCH_PROL]] ] 187; CHECK-NEXT: br label [[INNER_1_HEADER_PROL_LOOPEXIT]] 188; CHECK: inner.1.header.prol.loopexit: 189; CHECK-NEXT: [[L_1_LCSSA_UNR:%.*]] = phi i32 [ poison, [[OUTER_HEADER]] ], [ [[L_1_LCSSA_UNR_PH]], [[INNER_1_HEADER_PROL_LOOPEXIT_UNR_LCSSA]] ] 190; CHECK-NEXT: [[INNER_1_IV_UNR:%.*]] = phi i64 [ [[X]], [[OUTER_HEADER]] ], [ [[INNER_1_IV_UNR_PH]], [[INNER_1_HEADER_PROL_LOOPEXIT_UNR_LCSSA]] ] 191; CHECK-NEXT: [[TMP4:%.*]] = icmp ult i64 [[TMP3]], 7 192; CHECK-NEXT: br i1 [[TMP4]], label [[OUTER_MIDDLE:%.*]], label [[OUTER_HEADER_NEW:%.*]], !prof [[PROF3]] 193; CHECK: outer.header.new: 194; CHECK-NEXT: br label [[INNER_1_HEADER:%.*]] 195; CHECK: inner.1.header: 196; CHECK-NEXT: [[INNER_1_IV:%.*]] = phi i64 [ [[INNER_1_IV_UNR]], [[OUTER_HEADER_NEW]] ], [ [[INNER_1_IV_NEXT_7:%.*]], [[INNER_1_LATCH_7:%.*]] ] 197; CHECK-NEXT: [[CMP_1:%.*]] = icmp sgt i32 [[OUTER_P]], 0 198; CHECK-NEXT: br i1 [[CMP_1]], label [[EXIT_DEOPT_LOOPEXIT:%.*]], label [[INNER_1_LATCH:%.*]] 199; CHECK: inner.1.latch: 200; CHECK-NEXT: [[L_1:%.*]] = load i32, ptr [[SRC]], align 4 201; CHECK-NEXT: store i32 [[L_1]], ptr [[DST]], align 8 202; CHECK-NEXT: br i1 false, label [[EXIT_DEOPT_LOOPEXIT]], label [[INNER_1_LATCH_1:%.*]] 203; CHECK: inner.1.latch.1: 204; CHECK-NEXT: [[L_1_1:%.*]] = load i32, ptr [[SRC]], align 4 205; CHECK-NEXT: store i32 [[L_1_1]], ptr [[DST]], align 8 206; CHECK-NEXT: [[CMP_1_2:%.*]] = icmp sgt i32 [[OUTER_P]], 0 207; CHECK-NEXT: br i1 [[CMP_1_2]], label [[EXIT_DEOPT_LOOPEXIT]], label [[INNER_1_LATCH_2:%.*]] 208; CHECK: inner.1.latch.2: 209; CHECK-NEXT: [[L_1_2:%.*]] = load i32, ptr [[SRC]], align 4 210; CHECK-NEXT: store i32 [[L_1_2]], ptr [[DST]], align 8 211; CHECK-NEXT: br i1 false, label [[EXIT_DEOPT_LOOPEXIT]], label [[INNER_1_LATCH_3:%.*]] 212; CHECK: inner.1.latch.3: 213; CHECK-NEXT: [[L_1_3:%.*]] = load i32, ptr [[SRC]], align 4 214; CHECK-NEXT: store i32 [[L_1_3]], ptr [[DST]], align 8 215; CHECK-NEXT: [[CMP_1_4:%.*]] = icmp sgt i32 [[OUTER_P]], 0 216; CHECK-NEXT: br i1 [[CMP_1_4]], label [[EXIT_DEOPT_LOOPEXIT]], label [[INNER_1_LATCH_4:%.*]] 217; CHECK: inner.1.latch.4: 218; CHECK-NEXT: [[L_1_4:%.*]] = load i32, ptr [[SRC]], align 4 219; CHECK-NEXT: store i32 [[L_1_4]], ptr [[DST]], align 8 220; CHECK-NEXT: br i1 false, label [[EXIT_DEOPT_LOOPEXIT]], label [[INNER_1_LATCH_5:%.*]] 221; CHECK: inner.1.latch.5: 222; CHECK-NEXT: [[L_1_5:%.*]] = load i32, ptr [[SRC]], align 4 223; CHECK-NEXT: store i32 [[L_1_5]], ptr [[DST]], align 8 224; CHECK-NEXT: [[CMP_1_6:%.*]] = icmp sgt i32 [[OUTER_P]], 0 225; CHECK-NEXT: br i1 [[CMP_1_6]], label [[EXIT_DEOPT_LOOPEXIT]], label [[INNER_1_LATCH_6:%.*]] 226; CHECK: inner.1.latch.6: 227; CHECK-NEXT: [[L_1_6:%.*]] = load i32, ptr [[SRC]], align 4 228; CHECK-NEXT: store i32 [[L_1_6]], ptr [[DST]], align 8 229; CHECK-NEXT: [[INNER_1_IV_NEXT_6:%.*]] = add i64 [[INNER_1_IV]], 7 230; CHECK-NEXT: br i1 false, label [[EXIT_DEOPT_LOOPEXIT]], label [[INNER_1_LATCH_7]] 231; CHECK: inner.1.latch.7: 232; CHECK-NEXT: [[L_1_7:%.*]] = load i32, ptr [[SRC]], align 4 233; CHECK-NEXT: store i32 [[L_1_7]], ptr [[DST]], align 8 234; CHECK-NEXT: [[INNER_1_IV_NEXT_7]] = add i64 [[INNER_1_IV]], 8 235; CHECK-NEXT: [[CMP_2_7:%.*]] = icmp sgt i64 [[INNER_1_IV_NEXT_6]], 0 236; CHECK-NEXT: br i1 [[CMP_2_7]], label [[OUTER_MIDDLE_UNR_LCSSA:%.*]], label [[INNER_1_HEADER]], !prof [[PROF6:![0-9]+]] 237; CHECK: outer.middle.unr-lcssa: 238; CHECK-NEXT: [[L_1_LCSSA_PH:%.*]] = phi i32 [ [[L_1_7]], [[INNER_1_LATCH_7]] ] 239; CHECK-NEXT: br label [[OUTER_MIDDLE]] 240; CHECK: outer.middle: 241; CHECK-NEXT: [[L_1_LCSSA]] = phi i32 [ [[L_1_LCSSA_UNR]], [[INNER_1_HEADER_PROL_LOOPEXIT]] ], [ [[L_1_LCSSA_PH]], [[OUTER_MIDDLE_UNR_LCSSA]] ] 242; CHECK-NEXT: br label [[INNER_2:%.*]] 243; CHECK: inner.2: 244; CHECK-NEXT: [[INNER_2_IV:%.*]] = phi i32 [ [[L_1_LCSSA]], [[OUTER_MIDDLE]] ], [ [[INNER_2_IV_NEXT_2:%.*]], [[INNER_2]] ] 245; CHECK-NEXT: [[TMP15:%.*]] = phi i32 [ 0, [[OUTER_MIDDLE]] ], [ [[TMP33_2:%.*]], [[INNER_2]] ] 246; CHECK-NEXT: [[L_2:%.*]] = load i32, ptr [[SRC]], align 8 247; CHECK-NEXT: [[INNER_2_IV_NEXT:%.*]] = add i32 [[INNER_2_IV]], 1 248; CHECK-NEXT: [[TMP27:%.*]] = load ptr, ptr [[PTR_SRC:%.*]], align 8 249; CHECK-NEXT: [[ADD_1:%.*]] = add i32 [[INNER_2_IV]], [[L_2]] 250; CHECK-NEXT: [[TMP281:%.*]] = call i32 @use.2(ptr [[TMP27]], i32 [[ADD_1]]) 251; CHECK-NEXT: [[TMP31:%.*]] = shl nuw nsw i32 [[TMP15]], 16 252; CHECK-NEXT: call void @bar() 253; CHECK-NEXT: call void @bar() 254; CHECK-NEXT: call void @bar() 255; CHECK-NEXT: call void @bar() 256; CHECK-NEXT: call void @bar() 257; CHECK-NEXT: call void @bar() 258; CHECK-NEXT: call void @bar() 259; CHECK-NEXT: call void @bar() 260; CHECK-NEXT: [[L_2_1:%.*]] = load i32, ptr [[SRC]], align 8 261; CHECK-NEXT: [[INNER_2_IV_NEXT_1:%.*]] = add i32 [[INNER_2_IV]], 2 262; CHECK-NEXT: [[TMP27_1:%.*]] = load ptr, ptr [[PTR_SRC]], align 8 263; CHECK-NEXT: [[ADD_1_1:%.*]] = add i32 [[INNER_2_IV_NEXT]], [[L_2_1]] 264; CHECK-NEXT: [[TMP281_1:%.*]] = call i32 @use.2(ptr [[TMP27_1]], i32 [[ADD_1_1]]) 265; CHECK-NEXT: [[TMP32_1:%.*]] = add nuw i32 [[TMP31]], 524288 266; CHECK-NEXT: call void @bar() 267; CHECK-NEXT: call void @bar() 268; CHECK-NEXT: call void @bar() 269; CHECK-NEXT: call void @bar() 270; CHECK-NEXT: call void @bar() 271; CHECK-NEXT: call void @bar() 272; CHECK-NEXT: call void @bar() 273; CHECK-NEXT: call void @bar() 274; CHECK-NEXT: [[L_2_2:%.*]] = load i32, ptr [[SRC]], align 8 275; CHECK-NEXT: [[INNER_2_IV_NEXT_2]] = add i32 [[INNER_2_IV]], 3 276; CHECK-NEXT: [[TMP27_2:%.*]] = load ptr, ptr [[PTR_SRC]], align 8 277; CHECK-NEXT: [[ADD_1_2:%.*]] = add i32 [[INNER_2_IV_NEXT_1]], [[L_2_2]] 278; CHECK-NEXT: [[TMP281_2:%.*]] = call i32 @use.2(ptr [[TMP27_2]], i32 [[ADD_1_2]]) 279; CHECK-NEXT: [[TMP32_2:%.*]] = add nuw i32 [[TMP31]], 786432 280; CHECK-NEXT: [[TMP33_2]] = ashr exact i32 [[TMP32_2]], 16 281; CHECK-NEXT: call void @bar() 282; CHECK-NEXT: call void @bar() 283; CHECK-NEXT: call void @bar() 284; CHECK-NEXT: call void @bar() 285; CHECK-NEXT: call void @bar() 286; CHECK-NEXT: call void @bar() 287; CHECK-NEXT: call void @bar() 288; CHECK-NEXT: call void @bar() 289; CHECK-NEXT: [[CMP_3_2:%.*]] = icmp sgt i32 [[TMP32_1]], 2031616 290; CHECK-NEXT: br i1 [[CMP_3_2]], label [[OUTER_LATCH]], label [[INNER_2]] 291; CHECK: outer.latch: 292; CHECK-NEXT: br label [[OUTER_HEADER]] 293; CHECK: exit.deopt.loopexit: 294; CHECK-NEXT: br label [[EXIT_DEOPT:%.*]] 295; CHECK: exit.deopt.loopexit1: 296; CHECK-NEXT: br label [[EXIT_DEOPT]] 297; CHECK: exit.deopt: 298; CHECK-NEXT: call void (...) @llvm.experimental.deoptimize.isVoid(i32 0) [ "deopt"() ] 299; CHECK-NEXT: ret void 300; 301bb: 302 br label %outer.header 303 304outer.header: 305 %outer.p = phi i32 [ 0, %bb ], [ %l.1, %outer.latch ] 306 br label %inner.1.header 307 308inner.1.header: 309 %inner.1.iv = phi i64 [ %x, %outer.header ], [ %inner.1.iv.next, %inner.1.latch ] 310 %cmp.1 = icmp sgt i32 %outer.p, 0 311 br i1 %cmp.1, label %exit.deopt, label %inner.1.latch 312 313inner.1.latch: 314 %l.1 = load i32, ptr %src, align 4 315 store i32 %l.1, ptr %dst, align 8 316 %inner.1.iv.next = add i64 %inner.1.iv, 1 317 %cmp.2 = icmp sgt i64 %inner.1.iv, 0 318 br i1 %cmp.2, label %outer.middle, label %inner.1.header, !prof !1 319 320outer.middle: 321 br label %inner.2 322 323inner.2: 324 %inner.2.iv = phi i32 [ %l.1, %outer.middle ], [ %inner.2.iv.next, %inner.2 ] 325 %tmp15 = phi i32 [ 0, %outer.middle ], [ %tmp33, %inner.2 ] 326 %l.2 = load i32, ptr %src , align 8 327 %l.3 = load i32, ptr %dst, align 4 328 %inner.2.iv.next = add i32 %inner.2.iv, 1 329 %tmp27 = load ptr, ptr %ptr.src 330 %add.1 = add i32 %inner.2.iv, %l.2 331 %add.2 = add i32 %add.1, %l.3 332 %tmp281 = call i32 @use.2(ptr %tmp27, i32 %add.1) 333 %tmp31 = shl nuw nsw i32 %tmp15, 16 334 %tmp32 = add nuw i32 %tmp31, 262144 335 %tmp33 = ashr exact i32 %tmp32, 16 336 call void @bar() 337 call void @bar() 338 call void @bar() 339 call void @bar() 340 call void @bar() 341 call void @bar() 342 call void @bar() 343 call void @bar() 344 %cmp.3 = icmp sgt i32 %tmp31, 2031616 345 br i1 %cmp.3, label %outer.latch, label %inner.2 346 347outer.latch: 348 br label %outer.header 349 350exit.deopt: 351 call void (...) @llvm.experimental.deoptimize.isVoid(i32 0) [ "deopt"() ] 352 ret void 353} 354 355!0 = !{!"function_entry_count", i64 32768} 356!1 = !{!"branch_weights", i32 1, i32 32} 357