1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2 2; RUN: opt -S -loop-reduce < %s | FileCheck %s 3 4; Address Space 10 is non-integral. The optimizer is not allowed to use 5; ptrtoint/inttoptr instructions. Make sure that this doesn't happen 6target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128-ni:10:11:12" 7target triple = "x86_64-unknown-linux-gnu" 8 9; How exactly SCEV chooses to materialize isn't all that important, as 10; long as it doesn't try to round-trip through integers. As of this writing, 11; it emits a byte-wise gep, which is fine. 12define void @japi1__unsafe_getindex_65028(ptr addrspace(10) %arg) { 13; CHECK-LABEL: define void @japi1__unsafe_getindex_65028 14; CHECK-SAME: (ptr addrspace(10) [[ARG:%.*]]) { 15; CHECK-NEXT: top: 16; CHECK-NEXT: br label [[L86:%.*]] 17; CHECK: L86: 18; CHECK-NEXT: [[LSR_IV4:%.*]] = phi i64 [ [[LSR_IV_NEXT5:%.*]], [[L86]] ], [ -2, [[TOP:%.*]] ] 19; CHECK-NEXT: [[LSR_IV_NEXT5]] = add nsw i64 [[LSR_IV4]], 2 20; CHECK-NEXT: br i1 false, label [[L86]], label [[IF29:%.*]] 21; CHECK: if29: 22; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr addrspace(10) [[ARG]], i64 -8 23; CHECK-NEXT: br label [[IF31:%.*]] 24; CHECK: if31: 25; CHECK-NEXT: %"#temp#1.sroa.0.022" = phi i64 [ 0, [[IF29]] ], [ [[TMP3_LCSSA:%.*]], [[IF38:%.*]] ] 26; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[LSR_IV_NEXT5]], %"#temp#1.sroa.0.022" 27; CHECK-NEXT: [[TMP1:%.*]] = shl i64 [[TMP0]], 3 28; CHECK-NEXT: [[SCEVGEP1:%.*]] = getelementptr i8, ptr addrspace(10) [[SCEVGEP]], i64 [[TMP1]] 29; CHECK-NEXT: br label [[L119:%.*]] 30; CHECK: L119: 31; CHECK-NEXT: [[LSR_IV2:%.*]] = phi ptr addrspace(10) [ [[SCEVGEP3:%.*]], [[L119]] ], [ [[SCEVGEP1]], [[IF31]] ] 32; CHECK-NEXT: [[I5_0:%.*]] = phi i64 [ %"#temp#1.sroa.0.022", [[IF31]] ], [ [[TMP3:%.*]], [[L119]] ] 33; CHECK-NEXT: [[TMP3]] = add i64 [[I5_0]], 1 34; CHECK-NEXT: [[SCEVGEP3]] = getelementptr i8, ptr addrspace(10) [[LSR_IV2]], i64 8 35; CHECK-NEXT: br i1 false, label [[L119]], label [[IF38]] 36; CHECK: if38: 37; CHECK-NEXT: [[TMP3_LCSSA]] = phi i64 [ [[TMP3]], [[L119]] ] 38; CHECK-NEXT: [[TMP6:%.*]] = load i64, ptr addrspace(10) [[SCEVGEP3]], align 8 39; CHECK-NEXT: br i1 true, label [[DONE:%.*]], label [[IF31]] 40; CHECK: done: 41; CHECK-NEXT: ret void 42; 43top: 44 br label %L86 45 46L86: ; preds = %L86, %top 47 %i.0 = phi i64 [ 0, %top ], [ %tmp, %L86 ] 48 %tmp = add i64 %i.0, 1 49 br i1 false, label %L86, label %if29 50 51if29: ; preds = %L86 52 %tmp1 = shl i64 %tmp, 1 53 %tmp2 = add i64 %tmp1, -2 54 br label %if31 55 56if31: ; preds = %if38, %if29 57 %"#temp#1.sroa.0.022" = phi i64 [ 0, %if29 ], [ %tmp3, %if38 ] 58 br label %L119 59 60L119: ; preds = %L119, %if31 61 %i5.0 = phi i64 [ %"#temp#1.sroa.0.022", %if31 ], [ %tmp3, %L119 ] 62 %tmp3 = add i64 %i5.0, 1 63 br i1 false, label %L119, label %if38 64 65if38: ; preds = %L119 66 %tmp4 = add i64 %tmp2, %i5.0 67 %tmp5 = getelementptr i64, ptr addrspace(10) %arg, i64 %tmp4 68 %tmp6 = load i64, ptr addrspace(10) %tmp5 69 br i1 true, label %done, label %if31 70 71done: ; preds = %if38 72 ret void 73} 74