1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2 2; REQUIRES: asserts 3; RUN: opt < %s -passes=loop-reduce,loop-term-fold -S -debug 2>&1 | FileCheck %s 4 5target datalayout = "e-p:64:64:64-n64" 6 7define i32 @loop_variant(ptr %ar, i32 %n, i32 %m) { 8; CHECK-LABEL: define i32 @loop_variant 9; CHECK-SAME: (ptr [[AR:%.*]], i32 [[N:%.*]], i32 [[M:%.*]]) { 10; CHECK-NEXT: entry: 11; CHECK-NEXT: br label [[FOR_COND:%.*]] 12; CHECK: for.cond: 13; CHECK-NEXT: [[N_ADDR_0:%.*]] = phi i32 [ [[N]], [[ENTRY:%.*]] ], [ [[MUL:%.*]], [[FOR_COND]] ] 14; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[N_ADDR_0]], [[M]] 15; CHECK-NEXT: [[MUL]] = shl nsw i32 [[N_ADDR_0]], 1 16; CHECK-NEXT: br i1 [[CMP]], label [[FOR_COND]], label [[FOR_END:%.*]] 17; CHECK: for.end: 18; CHECK-NEXT: [[N_ADDR_0_LCSSA:%.*]] = phi i32 [ [[N_ADDR_0]], [[FOR_COND]] ] 19; CHECK-NEXT: ret i32 [[N_ADDR_0_LCSSA]] 20; 21entry: 22 br label %for.cond 23 24for.cond: ; preds = %for.cond, %entry 25 %n.addr.0 = phi i32 [ %n, %entry ], [ %mul, %for.cond ] 26 %cmp = icmp slt i32 %n.addr.0, %m 27 %mul = shl nsw i32 %n.addr.0, 1 28 br i1 %cmp, label %for.cond, label %for.end 29 30for.end: ; preds = %for.cond 31 ret i32 %n.addr.0 32} 33 34define i32 @nested_loop(ptr %ar, i32 %n, i32 %m, i32 %o) { 35; CHECK-LABEL: define i32 @nested_loop 36; CHECK-SAME: (ptr [[AR:%.*]], i32 [[N:%.*]], i32 [[M:%.*]], i32 [[O:%.*]]) { 37; CHECK-NEXT: entry: 38; CHECK-NEXT: [[CMP15:%.*]] = icmp sgt i32 [[O]], 0 39; CHECK-NEXT: br i1 [[CMP15]], label [[FOR_BODY_PREHEADER:%.*]], label [[FOR_COND_CLEANUP:%.*]] 40; CHECK: for.body.preheader: 41; CHECK-NEXT: br label [[FOR_BODY:%.*]] 42; CHECK: for.cond.cleanup.loopexit: 43; CHECK-NEXT: [[CNT_1_LCSSA_LCSSA:%.*]] = phi i32 [ [[CNT_1_LCSSA:%.*]], [[FOR_COND_CLEANUP3:%.*]] ] 44; CHECK-NEXT: br label [[FOR_COND_CLEANUP]] 45; CHECK: for.cond.cleanup: 46; CHECK-NEXT: [[CNT_0_LCSSA:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[CNT_1_LCSSA_LCSSA]], [[FOR_COND_CLEANUP_LOOPEXIT:%.*]] ] 47; CHECK-NEXT: ret i32 [[CNT_0_LCSSA]] 48; CHECK: for.body: 49; CHECK-NEXT: [[I_017:%.*]] = phi i32 [ [[INC6:%.*]], [[FOR_COND_CLEANUP3]] ], [ 0, [[FOR_BODY_PREHEADER]] ] 50; CHECK-NEXT: [[CNT_016:%.*]] = phi i32 [ [[CNT_1_LCSSA]], [[FOR_COND_CLEANUP3]] ], [ 0, [[FOR_BODY_PREHEADER]] ] 51; CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 [[N]], [[I_017]] 52; CHECK-NEXT: [[CMP212:%.*]] = icmp slt i32 [[SUB]], [[M]] 53; CHECK-NEXT: br i1 [[CMP212]], label [[FOR_BODY4_PREHEADER:%.*]], label [[FOR_COND_CLEANUP3]] 54; CHECK: for.body4.preheader: 55; CHECK-NEXT: br label [[FOR_BODY4:%.*]] 56; CHECK: for.cond.cleanup3.loopexit: 57; CHECK-NEXT: [[INC_LCSSA:%.*]] = phi i32 [ [[INC:%.*]], [[FOR_BODY4]] ] 58; CHECK-NEXT: br label [[FOR_COND_CLEANUP3]] 59; CHECK: for.cond.cleanup3: 60; CHECK-NEXT: [[CNT_1_LCSSA]] = phi i32 [ [[CNT_016]], [[FOR_BODY]] ], [ [[INC_LCSSA]], [[FOR_COND_CLEANUP3_LOOPEXIT:%.*]] ] 61; CHECK-NEXT: [[INC6]] = add nuw nsw i32 [[I_017]], 1 62; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[INC6]], [[O]] 63; CHECK-NEXT: br i1 [[CMP]], label [[FOR_BODY]], label [[FOR_COND_CLEANUP_LOOPEXIT]] 64; CHECK: for.body4: 65; CHECK-NEXT: [[J_014:%.*]] = phi i32 [ [[MUL:%.*]], [[FOR_BODY4]] ], [ [[SUB]], [[FOR_BODY4_PREHEADER]] ] 66; CHECK-NEXT: [[CNT_113:%.*]] = phi i32 [ [[INC]], [[FOR_BODY4]] ], [ [[CNT_016]], [[FOR_BODY4_PREHEADER]] ] 67; CHECK-NEXT: [[INC]] = add nsw i32 [[CNT_113]], 1 68; CHECK-NEXT: [[MUL]] = shl nsw i32 [[J_014]], 1 69; CHECK-NEXT: [[CMP2:%.*]] = icmp slt i32 [[MUL]], [[M]] 70; CHECK-NEXT: br i1 [[CMP2]], label [[FOR_BODY4]], label [[FOR_COND_CLEANUP3_LOOPEXIT]] 71; 72entry: 73 %cmp15 = icmp sgt i32 %o, 0 74 br i1 %cmp15, label %for.body, label %for.cond.cleanup 75 76for.cond.cleanup: ; preds = %for.cond.cleanup3, %entry 77 %cnt.0.lcssa = phi i32 [ 0, %entry ], [ %cnt.1.lcssa, %for.cond.cleanup3 ] 78 ret i32 %cnt.0.lcssa 79 80for.body: ; preds = %entry, %for.cond.cleanup3 81 %i.017 = phi i32 [ %inc6, %for.cond.cleanup3 ], [ 0, %entry ] 82 %cnt.016 = phi i32 [ %cnt.1.lcssa, %for.cond.cleanup3 ], [ 0, %entry ] 83 %sub = sub nsw i32 %n, %i.017 84 %cmp212 = icmp slt i32 %sub, %m 85 br i1 %cmp212, label %for.body4, label %for.cond.cleanup3 86 87for.cond.cleanup3: ; preds = %for.body4, %for.body 88 %cnt.1.lcssa = phi i32 [ %cnt.016, %for.body ], [ %inc, %for.body4 ] 89 %inc6 = add nuw nsw i32 %i.017, 1 90 %cmp = icmp slt i32 %inc6, %o 91 br i1 %cmp, label %for.body, label %for.cond.cleanup 92 93for.body4: ; preds = %for.body, %for.body4 94 %j.014 = phi i32 [ %mul, %for.body4 ], [ %sub, %for.body ] 95 %cnt.113 = phi i32 [ %inc, %for.body4 ], [ %cnt.016, %for.body ] 96 %inc = add nsw i32 %cnt.113, 1 97 %mul = shl nsw i32 %j.014, 1 98 %cmp2 = icmp slt i32 %mul, %m 99 br i1 %cmp2, label %for.body4, label %for.cond.cleanup3 100} 101 102declare void @foo(ptr) 103 104define void @NonAddRecIV(ptr %a) { 105; CHECK-LABEL: define void @NonAddRecIV 106; CHECK-SAME: (ptr [[A:%.*]]) { 107; CHECK-NEXT: entry: 108; CHECK-NEXT: [[UGLYGEP:%.*]] = getelementptr i8, ptr [[A]], i32 84 109; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[A]], i64 148 110; CHECK-NEXT: br label [[FOR_BODY:%.*]] 111; CHECK: for.body: 112; CHECK-NEXT: [[LSR_IV1:%.*]] = phi ptr [ [[UGLYGEP2:%.*]], [[FOR_BODY]] ], [ [[UGLYGEP]], [[ENTRY:%.*]] ] 113; CHECK-NEXT: store i32 1, ptr [[LSR_IV1]], align 4 114; CHECK-NEXT: [[UGLYGEP2]] = getelementptr i8, ptr [[LSR_IV1]], i64 4 115; CHECK-NEXT: [[LSR_FOLD_TERM_COND_REPLACED_TERM_COND:%.*]] = icmp eq ptr [[UGLYGEP2]], [[SCEVGEP]] 116; CHECK-NEXT: br i1 [[LSR_FOLD_TERM_COND_REPLACED_TERM_COND]], label [[FOR_END:%.*]], label [[FOR_BODY]] 117; CHECK: for.end: 118; CHECK-NEXT: ret void 119; 120entry: 121 %uglygep = getelementptr i8, ptr %a, i32 84 122 br label %for.body 123 124for.body: ; preds = %for.body, %entry 125 %lsr.iv1 = phi ptr [ %uglygep2, %for.body ], [ %uglygep, %entry ] 126 %lsr.iv = phi i32 [ %lsr.iv.next, %for.body ], [ 1, %entry ] 127 store i32 1, ptr %lsr.iv1, align 4 128 %lsr.iv.next = mul nsw i32 %lsr.iv, 2 129 %uglygep2 = getelementptr i8, ptr %lsr.iv1, i64 4 130 %exitcond.not = icmp eq i32 %lsr.iv.next, 65536 131 br i1 %exitcond.not, label %for.end, label %for.body 132 133for.end: ; preds = %for.body 134 ret void 135} 136 137@fp_inc = common global float 0.000000e+00, align 4 138 139define void @NonSCEVableIV(float %init, ptr %A, i32 %N) { 140; CHECK-LABEL: define void @NonSCEVableIV 141; CHECK-SAME: (float [[INIT:%.*]], ptr [[A:%.*]], i32 [[N:%.*]]) { 142; CHECK-NEXT: entry: 143; CHECK-NEXT: [[TMP0:%.*]] = load float, ptr @fp_inc, align 4 144; CHECK-NEXT: br label [[FOR_BODY:%.*]] 145; CHECK: for.body: 146; CHECK-NEXT: [[LSR_IV1:%.*]] = phi ptr [ [[SCEVGEP:%.*]], [[FOR_BODY]] ], [ [[A]], [[ENTRY:%.*]] ] 147; CHECK-NEXT: [[LSR_IV:%.*]] = phi i64 [ [[LSR_IV_NEXT:%.*]], [[FOR_BODY]] ], [ 1, [[ENTRY]] ] 148; CHECK-NEXT: [[X_05:%.*]] = phi float [ [[INIT]], [[ENTRY]] ], [ [[ADD:%.*]], [[FOR_BODY]] ] 149; CHECK-NEXT: store float [[X_05]], ptr [[LSR_IV1]], align 4 150; CHECK-NEXT: [[ADD]] = fsub float [[X_05]], [[TMP0]] 151; CHECK-NEXT: [[LFTR_WIDEIV:%.*]] = trunc i64 [[LSR_IV]] to i32 152; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i32 [[LFTR_WIDEIV]], [[N]] 153; CHECK-NEXT: [[LSR_IV_NEXT]] = add nuw nsw i64 [[LSR_IV]], 1 154; CHECK-NEXT: [[SCEVGEP]] = getelementptr i8, ptr [[LSR_IV1]], i64 4 155; CHECK-NEXT: br i1 [[EXITCOND]], label [[FOR_END:%.*]], label [[FOR_BODY]] 156; CHECK: for.end: 157; CHECK-NEXT: ret void 158; 159entry: 160 %0 = load float, ptr @fp_inc, align 4 161 br label %for.body 162 163for.body: ; preds = %entry 164 %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ] 165 %x.05 = phi float [ %init, %entry ], [ %add, %for.body ] 166 %arrayidx = getelementptr inbounds float, ptr %A, i64 %indvars.iv 167 store float %x.05, ptr %arrayidx, align 4 168 %add = fsub float %x.05, %0 169 %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 170 %lftr.wideiv = trunc i64 %indvars.iv.next to i32 171 %exitcond = icmp eq i32 %lftr.wideiv, %N 172 br i1 %exitcond, label %for.end, label %for.body 173 174for.end: ; preds = %for.end 175 ret void 176} 177 178define void @NonIcmp(ptr %a) { 179; CHECK-LABEL: define void @NonIcmp 180; CHECK-SAME: (ptr [[A:%.*]]) { 181; CHECK-NEXT: entry: 182; CHECK-NEXT: [[UGLYGEP:%.*]] = getelementptr i8, ptr [[A]], i64 84 183; CHECK-NEXT: br label [[FOR_BODY:%.*]] 184; CHECK: for.body: 185; CHECK-NEXT: [[LSR_IV2:%.*]] = phi i64 [ [[LSR_IV_NEXT3:%.*]], [[FOR_BODY]] ], [ 378, [[ENTRY:%.*]] ] 186; CHECK-NEXT: [[LSR_IV1:%.*]] = phi ptr [ [[UGLYGEP2:%.*]], [[FOR_BODY]] ], [ [[UGLYGEP]], [[ENTRY]] ] 187; CHECK-NEXT: store i32 1, ptr [[LSR_IV1]], align 4 188; CHECK-NEXT: [[UGLYGEP2]] = getelementptr i8, ptr [[LSR_IV1]], i64 4 189; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp sle i64 [[LSR_IV2]], 0 190; CHECK-NEXT: [[FIND_COND:%.*]] = and i1 [[EXITCOND_NOT]], true 191; CHECK-NEXT: [[LSR_IV_NEXT3]] = add nsw i64 [[LSR_IV2]], -1 192; CHECK-NEXT: br i1 [[FIND_COND]], label [[FOR_END:%.*]], label [[FOR_BODY]] 193; CHECK: for.end: 194; CHECK-NEXT: ret void 195; 196entry: 197 %uglygep = getelementptr i8, ptr %a, i64 84 198 br label %for.body 199 200for.body: ; preds = %for.body, %entry 201 %lsr.iv1 = phi ptr [ %uglygep2, %for.body ], [ %uglygep, %entry ] 202 %lsr.iv = phi i64 [ %lsr.iv.next, %for.body ], [ 379, %entry ] 203 store i32 1, ptr %lsr.iv1, align 4 204 %lsr.iv.next = add nsw i64 %lsr.iv, -1 205 %uglygep2 = getelementptr i8, ptr %lsr.iv1, i64 4 206 %exitcond.not = icmp sle i64 %lsr.iv.next, 0 207 %find.cond = and i1 %exitcond.not, 1 208 br i1 %find.cond, label %for.end, label %for.body 209 210for.end: ; preds = %for.body 211 ret void 212} 213 214; After LSR, there are three IVs in this loop. As a result, we have two 215; alternate IVs to chose from. At the moment, we chose the last, but this 216; is somewhat arbitrary. 217define void @TermCondMoreThanOneUse(ptr %a) { 218; CHECK-LABEL: define void @TermCondMoreThanOneUse 219; CHECK-SAME: (ptr [[A:%.*]]) { 220; CHECK-NEXT: entry: 221; CHECK-NEXT: [[UGLYGEP:%.*]] = getelementptr i8, ptr [[A]], i64 84 222; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[A]], i64 1600 223; CHECK-NEXT: br label [[FOR_BODY:%.*]] 224; CHECK: for.body: 225; CHECK-NEXT: [[LSR_IV2:%.*]] = phi i64 [ [[LSR_IV_NEXT3:%.*]], [[FOR_BODY]] ], [ -378, [[ENTRY:%.*]] ] 226; CHECK-NEXT: [[LSR_IV1:%.*]] = phi ptr [ [[UGLYGEP2:%.*]], [[FOR_BODY]] ], [ [[UGLYGEP]], [[ENTRY]] ] 227; CHECK-NEXT: store i32 1, ptr [[LSR_IV1]], align 4 228; CHECK-NEXT: [[UGLYGEP2]] = getelementptr i8, ptr [[LSR_IV1]], i64 4 229; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[LSR_IV2]], 0 230; CHECK-NEXT: [[DUMMY:%.*]] = select i1 [[EXITCOND_NOT]], i8 0, i8 1 231; CHECK-NEXT: [[LSR_IV_NEXT3]] = add nsw i64 [[LSR_IV2]], 1 232; CHECK-NEXT: [[LSR_FOLD_TERM_COND_REPLACED_TERM_COND:%.*]] = icmp eq ptr [[UGLYGEP2]], [[SCEVGEP]] 233; CHECK-NEXT: br i1 [[LSR_FOLD_TERM_COND_REPLACED_TERM_COND]], label [[FOR_END:%.*]], label [[FOR_BODY]] 234; CHECK: for.end: 235; CHECK-NEXT: ret void 236; 237entry: 238 %uglygep = getelementptr i8, ptr %a, i64 84 239 br label %for.body 240 241for.body: ; preds = %for.body, %entry 242 %lsr.iv1 = phi ptr [ %uglygep2, %for.body ], [ %uglygep, %entry ] 243 %lsr.iv = phi i64 [ %lsr.iv.next, %for.body ], [ 379, %entry ] 244 store i32 1, ptr %lsr.iv1, align 4 245 %lsr.iv.next = add nsw i64 %lsr.iv, -1 246 %uglygep2 = getelementptr i8, ptr %lsr.iv1, i64 4 247 %exitcond.not = icmp eq i64 %lsr.iv.next, 0 248 %dummy = select i1 %exitcond.not, i8 0, i8 1 249 br i1 %exitcond.not, label %for.end, label %for.body 250 251for.end: ; preds = %for.body 252 ret void 253} 254 255; The test case is reduced from FFmpeg/libavfilter/ebur128.c 256; Testing check if terminating value is safe to expand 257%struct.FFEBUR128State = type { i32, ptr, i64, i64 } 258 259@histogram_energy_boundaries = global [1001 x double] zeroinitializer, align 8 260 261define void @ebur128_calc_gating_block(ptr %st, ptr %optional_output) { 262; CHECK-LABEL: define void @ebur128_calc_gating_block 263; CHECK-SAME: (ptr [[ST:%.*]], ptr [[OPTIONAL_OUTPUT:%.*]]) { 264; CHECK-NEXT: entry: 265; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[ST]], align 8 266; CHECK-NEXT: [[CONV:%.*]] = zext i32 [[TMP0]] to i64 267; CHECK-NEXT: [[CMP28_NOT:%.*]] = icmp eq i32 [[TMP0]], 0 268; CHECK-NEXT: br i1 [[CMP28_NOT]], label [[FOR_END13:%.*]], label [[FOR_COND2_PREHEADER_LR_PH:%.*]] 269; CHECK: for.cond2.preheader.lr.ph: 270; CHECK-NEXT: [[AUDIO_DATA_INDEX:%.*]] = getelementptr inbounds [[STRUCT_FFEBUR128STATE:%.*]], ptr [[ST]], i64 0, i32 3 271; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr [[AUDIO_DATA_INDEX]], align 8 272; CHECK-NEXT: [[DIV:%.*]] = udiv i64 [[TMP1]], [[CONV]] 273; CHECK-NEXT: [[CMP525_NOT:%.*]] = icmp ult i64 [[TMP1]], [[CONV]] 274; CHECK-NEXT: [[AUDIO_DATA:%.*]] = getelementptr inbounds [[STRUCT_FFEBUR128STATE]], ptr [[ST]], i64 0, i32 1 275; CHECK-NEXT: [[UMAX:%.*]] = tail call i64 @llvm.umax.i64(i64 [[DIV]], i64 1) 276; CHECK-NEXT: [[TMP2:%.*]] = shl nuw nsw i64 [[CONV]], 3 277; CHECK-NEXT: br label [[FOR_COND2_PREHEADER:%.*]] 278; CHECK: for.cond2.preheader: 279; CHECK-NEXT: [[LSR_IV1:%.*]] = phi i64 [ [[LSR_IV_NEXT2:%.*]], [[FOR_INC11:%.*]] ], [ 0, [[FOR_COND2_PREHEADER_LR_PH]] ] 280; CHECK-NEXT: [[CHANNEL_SUM_030:%.*]] = phi double [ 0.000000e+00, [[FOR_COND2_PREHEADER_LR_PH]] ], [ [[CHANNEL_SUM_1_LCSSA:%.*]], [[FOR_INC11]] ] 281; CHECK-NEXT: [[C_029:%.*]] = phi i64 [ 0, [[FOR_COND2_PREHEADER_LR_PH]] ], [ [[INC12:%.*]], [[FOR_INC11]] ] 282; CHECK-NEXT: br i1 [[CMP525_NOT]], label [[FOR_INC11]], label [[FOR_BODY7_LR_PH:%.*]] 283; CHECK: for.body7.lr.ph: 284; CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[AUDIO_DATA]], align 8 285; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[TMP3]], i64 [[LSR_IV1]] 286; CHECK-NEXT: br label [[FOR_BODY7:%.*]] 287; CHECK: for.body7: 288; CHECK-NEXT: [[LSR_IV3:%.*]] = phi ptr [ [[SCEVGEP4:%.*]], [[FOR_BODY7]] ], [ [[SCEVGEP]], [[FOR_BODY7_LR_PH]] ] 289; CHECK-NEXT: [[LSR_IV:%.*]] = phi i64 [ [[LSR_IV_NEXT:%.*]], [[FOR_BODY7]] ], [ [[UMAX]], [[FOR_BODY7_LR_PH]] ] 290; CHECK-NEXT: [[CHANNEL_SUM_127:%.*]] = phi double [ [[CHANNEL_SUM_030]], [[FOR_BODY7_LR_PH]] ], [ [[ADD10:%.*]], [[FOR_BODY7]] ] 291; CHECK-NEXT: [[TMP4:%.*]] = load double, ptr [[LSR_IV3]], align 8 292; CHECK-NEXT: [[ADD10]] = fadd double [[CHANNEL_SUM_127]], [[TMP4]] 293; CHECK-NEXT: [[LSR_IV_NEXT]] = add i64 [[LSR_IV]], -1 294; CHECK-NEXT: [[SCEVGEP4]] = getelementptr i8, ptr [[LSR_IV3]], i64 [[TMP2]] 295; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[LSR_IV_NEXT]], 0 296; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label [[FOR_INC11_LOOPEXIT:%.*]], label [[FOR_BODY7]] 297; CHECK: for.inc11.loopexit: 298; CHECK-NEXT: [[ADD10_LCSSA:%.*]] = phi double [ [[ADD10]], [[FOR_BODY7]] ] 299; CHECK-NEXT: br label [[FOR_INC11]] 300; CHECK: for.inc11: 301; CHECK-NEXT: [[CHANNEL_SUM_1_LCSSA]] = phi double [ [[CHANNEL_SUM_030]], [[FOR_COND2_PREHEADER]] ], [ [[ADD10_LCSSA]], [[FOR_INC11_LOOPEXIT]] ] 302; CHECK-NEXT: [[INC12]] = add nuw nsw i64 [[C_029]], 1 303; CHECK-NEXT: [[LSR_IV_NEXT2]] = add nuw nsw i64 [[LSR_IV1]], 8 304; CHECK-NEXT: [[EXITCOND32_NOT:%.*]] = icmp eq i64 [[INC12]], [[CONV]] 305; CHECK-NEXT: br i1 [[EXITCOND32_NOT]], label [[FOR_END13_LOOPEXIT:%.*]], label [[FOR_COND2_PREHEADER]] 306; CHECK: for.end13.loopexit: 307; CHECK-NEXT: [[CHANNEL_SUM_1_LCSSA_LCSSA:%.*]] = phi double [ [[CHANNEL_SUM_1_LCSSA]], [[FOR_INC11]] ] 308; CHECK-NEXT: br label [[FOR_END13]] 309; CHECK: for.end13: 310; CHECK-NEXT: [[CHANNEL_SUM_0_LCSSA:%.*]] = phi double [ 0.000000e+00, [[ENTRY:%.*]] ], [ [[CHANNEL_SUM_1_LCSSA_LCSSA]], [[FOR_END13_LOOPEXIT]] ] 311; CHECK-NEXT: [[ADD14:%.*]] = fadd double [[CHANNEL_SUM_0_LCSSA]], 0.000000e+00 312; CHECK-NEXT: store double [[ADD14]], ptr [[OPTIONAL_OUTPUT]], align 8 313; CHECK-NEXT: ret void 314; 315entry: 316 %0 = load i32, ptr %st, align 8 317 %conv = zext i32 %0 to i64 318 %cmp28.not = icmp eq i32 %0, 0 319 br i1 %cmp28.not, label %for.end13, label %for.cond2.preheader.lr.ph 320 321for.cond2.preheader.lr.ph: ; preds = %entry 322 %audio_data_index = getelementptr inbounds %struct.FFEBUR128State, ptr %st, i64 0, i32 3 323 %1 = load i64, ptr %audio_data_index, align 8 324 %div = udiv i64 %1, %conv 325 %cmp525.not = icmp ult i64 %1, %conv 326 %audio_data = getelementptr inbounds %struct.FFEBUR128State, ptr %st, i64 0, i32 1 327 %umax = tail call i64 @llvm.umax.i64(i64 %div, i64 1) 328 br label %for.cond2.preheader 329 330for.cond2.preheader: ; preds = %for.cond2.preheader.lr.ph, %for.inc11 331 %channel_sum.030 = phi double [ 0.000000e+00, %for.cond2.preheader.lr.ph ], [ %channel_sum.1.lcssa, %for.inc11 ] 332 %c.029 = phi i64 [ 0, %for.cond2.preheader.lr.ph ], [ %inc12, %for.inc11 ] 333 br i1 %cmp525.not, label %for.inc11, label %for.body7.lr.ph 334 335for.body7.lr.ph: ; preds = %for.cond2.preheader 336 %2 = load ptr, ptr %audio_data, align 8 337 br label %for.body7 338 339for.body7: ; preds = %for.body7.lr.ph, %for.body7 340 %channel_sum.127 = phi double [ %channel_sum.030, %for.body7.lr.ph ], [ %add10, %for.body7 ] 341 %i.026 = phi i64 [ 0, %for.body7.lr.ph ], [ %inc, %for.body7 ] 342 %mul = mul i64 %i.026, %conv 343 %add = add i64 %mul, %c.029 344 %arrayidx = getelementptr inbounds double, ptr %2, i64 %add 345 %3 = load double, ptr %arrayidx, align 8 346 %add10 = fadd double %channel_sum.127, %3 347 %inc = add nuw i64 %i.026, 1 348 %exitcond.not = icmp eq i64 %inc, %umax 349 br i1 %exitcond.not, label %for.inc11, label %for.body7 350 351for.inc11: ; preds = %for.body7, %for.cond2.preheader 352 %channel_sum.1.lcssa = phi double [ %channel_sum.030, %for.cond2.preheader ], [ %add10, %for.body7 ] 353 %inc12 = add nuw nsw i64 %c.029, 1 354 %exitcond32.not = icmp eq i64 %inc12, %conv 355 br i1 %exitcond32.not, label %for.end13, label %for.cond2.preheader 356 357for.end13: ; preds = %for.inc11, %entry 358 %channel_sum.0.lcssa = phi double [ 0.000000e+00, %entry ], [ %channel_sum.1.lcssa, %for.inc11 ] 359 %add14 = fadd double %channel_sum.0.lcssa, 0.000000e+00 360 store double %add14, ptr %optional_output, align 8 361 ret void 362} 363 364declare i64 @llvm.umax.i64(i64, i64) 365 366%struct.PAKT_INFO = type { i32, i32, i32, [0 x i32] } 367 368define i64 @alac_seek(ptr %0) { 369; CHECK-LABEL: define i64 @alac_seek 370; CHECK-SAME: (ptr [[TMP0:%.*]]) { 371; CHECK-NEXT: entry: 372; CHECK-NEXT: [[DIV:%.*]] = udiv i64 1, 0 373; CHECK-NEXT: [[TMP1:%.*]] = add nuw nsw i64 [[DIV]], 1 374; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[TMP0]], i64 12 375; CHECK-NEXT: br label [[FOR_BODY_I:%.*]] 376; CHECK: for.body.i: 377; CHECK-NEXT: [[LSR_IV1:%.*]] = phi ptr [ [[SCEVGEP2:%.*]], [[FOR_BODY_I]] ], [ [[SCEVGEP]], [[ENTRY:%.*]] ] 378; CHECK-NEXT: [[LSR_IV:%.*]] = phi i64 [ [[LSR_IV_NEXT:%.*]], [[FOR_BODY_I]] ], [ [[TMP1]], [[ENTRY]] ] 379; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[LSR_IV1]], align 4 380; CHECK-NEXT: [[LSR_IV_NEXT]] = add i64 [[LSR_IV]], -1 381; CHECK-NEXT: [[SCEVGEP2]] = getelementptr i8, ptr [[LSR_IV1]], i64 4 382; CHECK-NEXT: [[EXITCOND_NOT_I:%.*]] = icmp eq i64 [[LSR_IV_NEXT]], 0 383; CHECK-NEXT: br i1 [[EXITCOND_NOT_I]], label [[ALAC_PAKT_BLOCK_OFFSET_EXIT:%.*]], label [[FOR_BODY_I]] 384; CHECK: alac_pakt_block_offset.exit: 385; CHECK-NEXT: ret i64 0 386; 387entry: 388 %div = udiv i64 1, 0 389 br label %for.body.i 390 391for.body.i: ; preds = %for.body.i, %entry 392 %indvars.iv.i = phi i64 [ 0, %entry ], [ %indvars.iv.next.i, %for.body.i ] 393 %arrayidx.i = getelementptr %struct.PAKT_INFO, ptr %0, i64 0, i32 3, i64 %indvars.iv.i 394 %1 = load i32, ptr %arrayidx.i, align 4 395 %indvars.iv.next.i = add i64 %indvars.iv.i, 1 396 %exitcond.not.i = icmp eq i64 %indvars.iv.i, %div 397 br i1 %exitcond.not.i, label %alac_pakt_block_offset.exit, label %for.body.i 398 399alac_pakt_block_offset.exit: ; preds = %for.body.i 400 ret i64 0 401} 402