1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 3 2; RUN: opt < %s -loop-reduce -S | FileCheck %s 3 4; This test tests several things. The load and store should use the 5; same address instead of having it computed twice, and SCEVExpander should 6; be able to reconstruct the full getelementptr, despite it having a few 7; obstacles set in its way. 8; We only check that the inner loop (bb1-bb2) is "reduced" because LSR 9; currently only operates on inner loops. 10 11target datalayout = "e-p:64:64:64-n32:64" 12 13define void @foo(i64 %n, i64 %m, i64 %o, i64 %q, ptr nocapture %p) nounwind { 14; CHECK-LABEL: define void @foo( 15; CHECK-SAME: i64 [[N:%.*]], i64 [[M:%.*]], i64 [[O:%.*]], i64 [[Q:%.*]], ptr captures(none) [[P:%.*]]) #[[ATTR0:[0-9]+]] { 16; CHECK-NEXT: entry: 17; CHECK-NEXT: [[TMP:%.*]] = icmp sgt i64 [[N]], 0 18; CHECK-NEXT: br i1 [[TMP]], label [[BB_NPH3:%.*]], label [[RETURN:%.*]] 19; CHECK: bb.nph: 20; CHECK-NEXT: br label [[BB1:%.*]] 21; CHECK: bb1: 22; CHECK-NEXT: [[LSR_IV2:%.*]] = phi ptr [ [[SCEVGEP3:%.*]], [[BB2:%.*]] ], [ [[LSR_IV:%.*]], [[BB_NPH:%.*]] ] 23; CHECK-NEXT: [[J_01:%.*]] = phi i64 [ [[TMP9:%.*]], [[BB2]] ], [ 0, [[BB_NPH]] ] 24; CHECK-NEXT: [[TMP6:%.*]] = load double, ptr [[LSR_IV2]], align 8 25; CHECK-NEXT: [[TMP7:%.*]] = fdiv double [[TMP6]], 2.100000e+00 26; CHECK-NEXT: store double [[TMP7]], ptr [[LSR_IV2]], align 8 27; CHECK-NEXT: [[TMP9]] = add i64 [[J_01]], 1 28; CHECK-NEXT: br label [[BB2]] 29; CHECK: bb2: 30; CHECK-NEXT: [[SCEVGEP3]] = getelementptr i8, ptr [[LSR_IV2]], i64 8 31; CHECK-NEXT: [[TMP10:%.*]] = icmp slt i64 [[TMP9]], [[M]] 32; CHECK-NEXT: br i1 [[TMP10]], label [[BB1]], label [[BB2_BB3_CRIT_EDGE:%.*]] 33; CHECK: bb2.bb3_crit_edge: 34; CHECK-NEXT: br label [[BB3:%.*]] 35; CHECK: bb3: 36; CHECK-NEXT: [[TMP11:%.*]] = add i64 [[I_02:%.*]], 1 37; CHECK-NEXT: br label [[BB4:%.*]] 38; CHECK: bb4: 39; CHECK-NEXT: [[SCEVGEP1:%.*]] = getelementptr i8, ptr [[LSR_IV]], i64 [[TMP2:%.*]] 40; CHECK-NEXT: [[TMP12:%.*]] = icmp slt i64 [[TMP11]], [[N]] 41; CHECK-NEXT: br i1 [[TMP12]], label [[BB2_PREHEADER:%.*]], label [[BB4_RETURN_CRIT_EDGE:%.*]] 42; CHECK: bb4.return_crit_edge: 43; CHECK-NEXT: br label [[BB4_RETURN_CRIT_EDGE_SPLIT:%.*]] 44; CHECK: bb4.return_crit_edge.split: 45; CHECK-NEXT: br label [[RETURN]] 46; CHECK: bb.nph3: 47; CHECK-NEXT: [[TMP13:%.*]] = icmp sgt i64 [[M]], 0 48; CHECK-NEXT: br i1 [[TMP13]], label [[BB_NPH3_SPLIT:%.*]], label [[BB4_RETURN_CRIT_EDGE_SPLIT]] 49; CHECK: bb.nph3.split: 50; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[P]], i64 41624 51; CHECK-NEXT: [[TMP0:%.*]] = mul i64 [[Q]], [[O]] 52; CHECK-NEXT: [[TMP1:%.*]] = mul i64 [[TMP0]], [[N]] 53; CHECK-NEXT: [[TMP2]] = mul i64 [[TMP1]], 296 54; CHECK-NEXT: br label [[BB2_PREHEADER]] 55; CHECK: bb2.preheader: 56; CHECK-NEXT: [[LSR_IV]] = phi ptr [ [[SCEVGEP]], [[BB_NPH3_SPLIT]] ], [ [[SCEVGEP1]], [[BB4]] ] 57; CHECK-NEXT: [[I_02]] = phi i64 [ [[TMP11]], [[BB4]] ], [ 0, [[BB_NPH3_SPLIT]] ] 58; CHECK-NEXT: br i1 true, label [[BB_NPH]], label [[BB3]] 59; CHECK: return: 60; CHECK-NEXT: ret void 61; 62entry: 63 %tmp = icmp sgt i64 %n, 0 ; <i1> [#uses=1] 64 br i1 %tmp, label %bb.nph3, label %return 65 66bb.nph: ; preds = %bb2.preheader 67 %tmp1 = mul i64 %tmp16, %i.02 ; <i64> [#uses=1] 68 %tmp2 = mul i64 %tmp19, %i.02 ; <i64> [#uses=1] 69 br label %bb1 70 71bb1: ; preds = %bb2, %bb.nph 72 %j.01 = phi i64 [ %tmp9, %bb2 ], [ 0, %bb.nph ] ; <i64> [#uses=3] 73 %tmp3 = add i64 %j.01, %tmp1 ; <i64> [#uses=1] 74 %tmp4 = add i64 %j.01, %tmp2 ; <i64> [#uses=1] 75 %z0 = add i64 %tmp3, 5203 76 %tmp5 = getelementptr double, ptr %p, i64 %z0 ; <ptr> [#uses=1] 77 %tmp6 = load double, ptr %tmp5, align 8 ; <double> [#uses=1] 78 %tmp7 = fdiv double %tmp6, 2.100000e+00 ; <double> [#uses=1] 79 %z1 = add i64 %tmp4, 5203 80 %tmp8 = getelementptr double, ptr %p, i64 %z1 ; <ptr> [#uses=1] 81 store double %tmp7, ptr %tmp8, align 8 82 %tmp9 = add i64 %j.01, 1 ; <i64> [#uses=2] 83 br label %bb2 84 85bb2: ; preds = %bb1 86 %tmp10 = icmp slt i64 %tmp9, %m ; <i1> [#uses=1] 87 br i1 %tmp10, label %bb1, label %bb2.bb3_crit_edge 88 89bb2.bb3_crit_edge: ; preds = %bb2 90 br label %bb3 91 92bb3: ; preds = %bb2.preheader, %bb2.bb3_crit_edge 93 %tmp11 = add i64 %i.02, 1 ; <i64> [#uses=2] 94 br label %bb4 95 96bb4: ; preds = %bb3 97 %tmp12 = icmp slt i64 %tmp11, %n ; <i1> [#uses=1] 98 br i1 %tmp12, label %bb2.preheader, label %bb4.return_crit_edge 99 100bb4.return_crit_edge: ; preds = %bb4 101 br label %bb4.return_crit_edge.split 102 103bb4.return_crit_edge.split: ; preds = %bb.nph3, %bb4.return_crit_edge 104 br label %return 105 106bb.nph3: ; preds = %entry 107 %tmp13 = icmp sgt i64 %m, 0 ; <i1> [#uses=1] 108 %tmp14 = mul i64 %n, 37 ; <i64> [#uses=1] 109 %tmp15 = mul i64 %tmp14, %o ; <i64> [#uses=1] 110 %tmp16 = mul i64 %tmp15, %q ; <i64> [#uses=1] 111 %tmp17 = mul i64 %n, 37 ; <i64> [#uses=1] 112 %tmp18 = mul i64 %tmp17, %o ; <i64> [#uses=1] 113 %tmp19 = mul i64 %tmp18, %q ; <i64> [#uses=1] 114 br i1 %tmp13, label %bb.nph3.split, label %bb4.return_crit_edge.split 115 116bb.nph3.split: ; preds = %bb.nph3 117 br label %bb2.preheader 118 119bb2.preheader: ; preds = %bb.nph3.split, %bb4 120 %i.02 = phi i64 [ %tmp11, %bb4 ], [ 0, %bb.nph3.split ] ; <i64> [#uses=3] 121 br i1 true, label %bb.nph, label %bb3 122 123return: ; preds = %bb4.return_crit_edge.split, %entry 124 ret void 125} 126