1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 2; RUN: opt -loop-reduce -S < %s 2>&1 | FileCheck %s 3 4target datalayout = "e-m:e-i64:64-n32:64" 5target triple = "powerpc64le-unknown-linux-gnu" 6 7; %lsr.iv2 and %lsr.iv10 are in same bb, but they are not equal since start 8; value are different. 9; 10; %scevgep = getelementptr [0 x %0], [0 x %0]* %arg, i64 0, i64 99 11; %scevgep1 = bitcast %0* %scevgep to [0 x %0]* 12; %lsr.iv2 = phi [0 x %0]* [ %1, %bb18 ], [ %scevgep1, %bb ] 13; 14; %lsr.iv10 = phi [0 x %0]* [ %2, %bb18 ], [ %arg, %bb ] 15; 16; Make sure two incomplete phis will not be marked as congruent. 17 18%0 = type <{ float }> 19 20define void @foo(ptr %arg) { 21; CHECK-LABEL: define void @foo( 22; CHECK-SAME: ptr [[ARG:%.*]]) { 23; CHECK-NEXT: bb: 24; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[ARG]], i64 396 25; CHECK-NEXT: br label [[BB3:%.*]] 26; CHECK: bb3: 27; CHECK-NEXT: [[LSR_IV7:%.*]] = phi ptr [ [[SCEVGEP8:%.*]], [[BB18:%.*]] ], [ [[ARG]], [[BB:%.*]] ] 28; CHECK-NEXT: [[LSR_IV5:%.*]] = phi i64 [ [[LSR_IV_NEXT6:%.*]], [[BB18]] ], [ 4, [[BB]] ] 29; CHECK-NEXT: [[LSR_IV1:%.*]] = phi ptr [ [[SCEVGEP2:%.*]], [[BB18]] ], [ [[SCEVGEP]], [[BB]] ] 30; CHECK-NEXT: br i1 true, label [[BB22_PREHEADER:%.*]], label [[BB9_PREHEADER:%.*]] 31; CHECK: bb9.preheader: 32; CHECK-NEXT: br label [[BB9:%.*]] 33; CHECK: bb9: 34; CHECK-NEXT: [[LSR_IV9:%.*]] = phi ptr [ [[LSR_IV7]], [[BB9_PREHEADER]] ], [ [[SCEVGEP10:%.*]], [[BB9]] ] 35; CHECK-NEXT: store <4 x float> undef, ptr [[LSR_IV9]], align 4 36; CHECK-NEXT: [[SCEVGEP10]] = getelementptr i8, ptr [[LSR_IV9]], i64 128 37; CHECK-NEXT: br i1 true, label [[BB17:%.*]], label [[BB9]] 38; CHECK: bb17: 39; CHECK-NEXT: br i1 false, label [[BB18]], label [[BB22_PREHEADER]] 40; CHECK: bb22.preheader: 41; CHECK-NEXT: br label [[BB22:%.*]] 42; CHECK: bb18: 43; CHECK-NEXT: [[LSR_IV_NEXT6]] = add nuw nsw i64 [[LSR_IV5]], 4 44; CHECK-NEXT: [[SCEVGEP2]] = getelementptr i8, ptr [[LSR_IV1]], i64 [[LSR_IV5]] 45; CHECK-NEXT: [[SCEVGEP8]] = getelementptr i8, ptr [[LSR_IV7]], i64 [[LSR_IV5]] 46; CHECK-NEXT: br label [[BB3]] 47; CHECK: bb22: 48; CHECK-NEXT: [[LSR_IV3:%.*]] = phi ptr [ [[LSR_IV1]], [[BB22_PREHEADER]] ], [ [[SCEVGEP4:%.*]], [[BB22]] ] 49; CHECK-NEXT: store float undef, ptr [[LSR_IV3]], align 4 50; CHECK-NEXT: [[SCEVGEP4]] = getelementptr i8, ptr [[LSR_IV3]], i64 4 51; CHECK-NEXT: br label [[BB22]] 52; 53bb: 54 %i = getelementptr inbounds [0 x %0], ptr %arg, i64 0, i64 -1 55 %i2 = getelementptr i8, ptr %i, i64 4 56 br label %bb3 57 58bb3: ; preds = %bb18, %bb 59 %i4 = phi i64 [ %i20, %bb18 ], [ 0, %bb ] 60 %i5 = phi i64 [ %i21, %bb18 ], [ 1, %bb ] 61 br i1 true, label %bb22, label %bb9 62 63bb9: ; preds = %bb9, %bb3 64 %i10 = phi i64 [ 0, %bb3 ], [ %i16, %bb9 ] 65 %i11 = add i64 %i10, %i4 66 %i12 = shl i64 %i11, 2 67 %i13 = getelementptr i8, ptr %i2, i64 %i12 68 store <4 x float> undef, ptr %i13, align 4 69 %i16 = add i64 %i10, 32 70 br i1 true, label %bb17, label %bb9 71 72bb17: ; preds = %bb9 73 br i1 false, label %bb18, label %bb22 74 75bb18: ; preds = %bb17 76 %i19 = add i64 undef, %i4 77 %i20 = add i64 %i19, %i5 78 %i21 = add nuw nsw i64 %i5, 1 79 br label %bb3 80 81bb22: ; preds = %bb22, %bb17, %bb3 82 %i23 = phi i64 [ %i26, %bb22 ], [ undef, %bb17 ], [ 100, %bb3 ] 83 %i24 = add nsw i64 %i23, %i4 84 %i25 = getelementptr %0, ptr %i, i64 %i24, i32 0 85 store float undef, ptr %i25, align 4 86 %i26 = add nuw nsw i64 %i23, 1 87 br label %bb22 88} 89