1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3 2; RUN: llc -O3 -mtriple=thumb-eabi -mcpu=cortex-a9 %s -o - | FileCheck %s -check-prefix=A9 3 4; @simple is the most basic chain of address induction variables. Chaining 5; saves at least one register and avoids complex addressing and setup 6; code. 7; 8; no expensive address computation in the preheader 9; no complex address modes 10define i32 @simple(ptr %a, ptr %b, i32 %x) nounwind { 11; A9-LABEL: simple: 12; A9: @ %bb.0: @ %entry 13; A9-NEXT: .save {r4, r5, r6, lr} 14; A9-NEXT: push {r4, r5, r6, lr} 15; A9-NEXT: mov r3, r0 16; A9-NEXT: lsls r2, r2, #2 17; A9-NEXT: movs r0, #0 18; A9-NEXT: .LBB0_1: @ %loop 19; A9-NEXT: @ =>This Inner Loop Header: Depth=1 20; A9-NEXT: add.w lr, r3, r2 21; A9-NEXT: ldr.w r12, [r3, r2] 22; A9-NEXT: ldr r3, [r3] 23; A9-NEXT: add.w r4, lr, r2 24; A9-NEXT: ldr.w r6, [lr, r2] 25; A9-NEXT: add r0, r3 26; A9-NEXT: adds r3, r4, r2 27; A9-NEXT: add r0, r12 28; A9-NEXT: ldr r5, [r4, r2] 29; A9-NEXT: add r0, r6 30; A9-NEXT: add r3, r2 31; A9-NEXT: add r0, r5 32; A9-NEXT: cmp r3, r1 33; A9-NEXT: bne .LBB0_1 34; A9-NEXT: @ %bb.2: @ %exit 35; A9-NEXT: pop {r4, r5, r6, pc} 36entry: 37 br label %loop 38loop: 39 %iv = phi ptr [ %a, %entry ], [ %iv4, %loop ] 40 %s = phi i32 [ 0, %entry ], [ %s4, %loop ] 41 %v = load i32, ptr %iv 42 %iv1 = getelementptr inbounds i32, ptr %iv, i32 %x 43 %v1 = load i32, ptr %iv1 44 %iv2 = getelementptr inbounds i32, ptr %iv1, i32 %x 45 %v2 = load i32, ptr %iv2 46 %iv3 = getelementptr inbounds i32, ptr %iv2, i32 %x 47 %v3 = load i32, ptr %iv3 48 %s1 = add i32 %s, %v 49 %s2 = add i32 %s1, %v1 50 %s3 = add i32 %s2, %v2 51 %s4 = add i32 %s3, %v3 52 %iv4 = getelementptr inbounds i32, ptr %iv3, i32 %x 53 %cmp = icmp eq ptr %iv4, %b 54 br i1 %cmp, label %exit, label %loop 55exit: 56 ret i32 %s4 57} 58 59; @user is not currently chained because the IV is live across memory ops. 60; 61; stride multiples computed in the preheader 62; complex address modes 63define i32 @user(ptr %a, ptr %b, i32 %x) nounwind { 64; A9-LABEL: user: 65; A9: @ %bb.0: @ %entry 66; A9-NEXT: .save {r4, r5, r6, r7, lr} 67; A9-NEXT: push {r4, r5, r6, r7, lr} 68; A9-NEXT: add.w r3, r2, r2, lsl #1 69; A9-NEXT: lsl.w r12, r2, #4 70; A9-NEXT: lsl.w lr, r3, #2 71; A9-NEXT: movs r3, #0 72; A9-NEXT: .LBB1_1: @ %loop 73; A9-NEXT: @ =>This Inner Loop Header: Depth=1 74; A9-NEXT: ldr r4, [r0] 75; A9-NEXT: ldr.w r5, [r0, r2, lsl #3] 76; A9-NEXT: ldr.w r6, [r0, r2, lsl #2] 77; A9-NEXT: add r3, r4 78; A9-NEXT: ldr.w r7, [r0, lr] 79; A9-NEXT: add r3, r6 80; A9-NEXT: add r3, r5 81; A9-NEXT: add r3, r7 82; A9-NEXT: str r3, [r0] 83; A9-NEXT: add r0, r12 84; A9-NEXT: cmp r0, r1 85; A9-NEXT: bne .LBB1_1 86; A9-NEXT: @ %bb.2: @ %exit 87; A9-NEXT: mov r0, r3 88; A9-NEXT: pop {r4, r5, r6, r7, pc} 89entry: 90 br label %loop 91loop: 92 %iv = phi ptr [ %a, %entry ], [ %iv4, %loop ] 93 %s = phi i32 [ 0, %entry ], [ %s4, %loop ] 94 %v = load i32, ptr %iv 95 %iv1 = getelementptr inbounds i32, ptr %iv, i32 %x 96 %v1 = load i32, ptr %iv1 97 %iv2 = getelementptr inbounds i32, ptr %iv1, i32 %x 98 %v2 = load i32, ptr %iv2 99 %iv3 = getelementptr inbounds i32, ptr %iv2, i32 %x 100 %v3 = load i32, ptr %iv3 101 %s1 = add i32 %s, %v 102 %s2 = add i32 %s1, %v1 103 %s3 = add i32 %s2, %v2 104 %s4 = add i32 %s3, %v3 105 %iv4 = getelementptr inbounds i32, ptr %iv3, i32 %x 106 store i32 %s4, ptr %iv 107 %cmp = icmp eq ptr %iv4, %b 108 br i1 %cmp, label %exit, label %loop 109exit: 110 ret i32 %s4 111} 112 113; @extrastride is a slightly more interesting case of a single 114; complete chain with multiple strides. The test case IR is what LSR 115; used to do, and exactly what we don't want to do. LSR's new IV 116; chaining feature should now undo the damage. 117; 118; no spills 119; only one stride multiple in the preheader 120; no complex address modes or reloads 121define void @extrastride(ptr nocapture %main, i32 %main_stride, ptr nocapture %res, i32 %x, i32 %y, i32 %z) nounwind { 122; A9-LABEL: extrastride: 123; A9: @ %bb.0: @ %entry 124; A9-NEXT: .save {r4, r5, r6, r7, lr} 125; A9-NEXT: push {r4, r5, r6, r7, lr} 126; A9-NEXT: ldr.w r12, [sp, #24] 127; A9-NEXT: cmp.w r12, #0 128; A9-NEXT: beq .LBB2_3 129; A9-NEXT: @ %bb.1: @ %for.body.lr.ph 130; A9-NEXT: ldr r4, [sp, #20] 131; A9-NEXT: add.w lr, r3, r1 132; A9-NEXT: lsls r3, r4, #2 133; A9-NEXT: .LBB2_2: @ %for.body 134; A9-NEXT: @ =>This Inner Loop Header: Depth=1 135; A9-NEXT: adds r5, r0, r1 136; A9-NEXT: ldr r4, [r0, r1] 137; A9-NEXT: ldr r0, [r0] 138; A9-NEXT: subs.w r12, r12, #1 139; A9-NEXT: ldr r6, [r5, r1] 140; A9-NEXT: add r5, r1 141; A9-NEXT: add r0, r4 142; A9-NEXT: ldr r7, [r5, r1] 143; A9-NEXT: add r5, r1 144; A9-NEXT: add r0, r6 145; A9-NEXT: ldr r4, [r5, r1] 146; A9-NEXT: add r0, r7 147; A9-NEXT: add r0, r4 148; A9-NEXT: str r0, [r2] 149; A9-NEXT: add.w r0, r5, r1 150; A9-NEXT: add r2, r3 151; A9-NEXT: add r0, lr 152; A9-NEXT: bne .LBB2_2 153; A9-NEXT: .LBB2_3: @ %for.end 154; A9-NEXT: pop {r4, r5, r6, r7, pc} 155entry: 156 %cmp8 = icmp eq i32 %z, 0 157 br i1 %cmp8, label %for.end, label %for.body.lr.ph 158 159for.body.lr.ph: ; preds = %entry 160 %add.ptr.sum = shl i32 %main_stride, 1 ; s*2 161 %add.ptr1.sum = add i32 %add.ptr.sum, %main_stride ; s*3 162 %add.ptr2.sum = add i32 %x, %main_stride ; s + x 163 %add.ptr4.sum = shl i32 %main_stride, 2 ; s*4 164 %add.ptr3.sum = add i32 %add.ptr2.sum, %add.ptr4.sum ; total IV stride = s*5+x 165 br label %for.body 166 167for.body: ; preds = %for.body.lr.ph, %for.body 168 %main.addr.011 = phi ptr [ %main, %for.body.lr.ph ], [ %add.ptr6, %for.body ] 169 %i.010 = phi i32 [ 0, %for.body.lr.ph ], [ %inc, %for.body ] 170 %res.addr.09 = phi ptr [ %res, %for.body.lr.ph ], [ %add.ptr7, %for.body ] 171 %0 = load i32, ptr %main.addr.011, align 4 172 %add.ptr = getelementptr inbounds i8, ptr %main.addr.011, i32 %main_stride 173 %1 = load i32, ptr %add.ptr, align 4 174 %add.ptr1 = getelementptr inbounds i8, ptr %main.addr.011, i32 %add.ptr.sum 175 %2 = load i32, ptr %add.ptr1, align 4 176 %add.ptr2 = getelementptr inbounds i8, ptr %main.addr.011, i32 %add.ptr1.sum 177 %3 = load i32, ptr %add.ptr2, align 4 178 %add.ptr3 = getelementptr inbounds i8, ptr %main.addr.011, i32 %add.ptr4.sum 179 %4 = load i32, ptr %add.ptr3, align 4 180 %add = add i32 %1, %0 181 %add4 = add i32 %add, %2 182 %add5 = add i32 %add4, %3 183 %add6 = add i32 %add5, %4 184 store i32 %add6, ptr %res.addr.09, align 4 185 %add.ptr6 = getelementptr inbounds i8, ptr %main.addr.011, i32 %add.ptr3.sum 186 %add.ptr7 = getelementptr inbounds i32, ptr %res.addr.09, i32 %y 187 %inc = add i32 %i.010, 1 188 %cmp = icmp eq i32 %inc, %z 189 br i1 %cmp, label %for.end, label %for.body 190 191for.end: ; preds = %for.body, %entry 192 ret void 193} 194 195; @foldedidx is an unrolled variant of this loop: 196; for (unsigned long i = 0; i < len; i += s) { 197; c[i] = a[i] + b[i]; 198; } 199; where 's' can be folded into the addressing mode. 200; Consequently, we should *not* form any chains. 201define void @foldedidx(ptr nocapture %a, ptr nocapture %b, ptr nocapture %c) nounwind ssp { 202; A9-LABEL: foldedidx: 203; A9: @ %bb.0: @ %entry 204; A9-NEXT: .save {r4, r5, r6, lr} 205; A9-NEXT: push {r4, r5, r6, lr} 206; A9-NEXT: mov.w lr, #0 207; A9-NEXT: .LBB3_1: @ %for.body 208; A9-NEXT: @ =>This Inner Loop Header: Depth=1 209; A9-NEXT: ldrb.w r12, [r0, lr] 210; A9-NEXT: add.w r4, r1, lr 211; A9-NEXT: ldrb.w r3, [r1, lr] 212; A9-NEXT: add r3, r12 213; A9-NEXT: strb.w r3, [r2, lr] 214; A9-NEXT: add.w r3, r0, lr 215; A9-NEXT: ldrb.w r12, [r3, #1] 216; A9-NEXT: ldrb r5, [r4, #1] 217; A9-NEXT: add r12, r5 218; A9-NEXT: add.w r5, r2, lr 219; A9-NEXT: strb.w r12, [r5, #1] 220; A9-NEXT: add.w lr, lr, #4 221; A9-NEXT: cmp.w lr, #400 222; A9-NEXT: ldrb.w r12, [r3, #2] 223; A9-NEXT: ldrb r6, [r4, #2] 224; A9-NEXT: add r6, r12 225; A9-NEXT: strb r6, [r5, #2] 226; A9-NEXT: ldrb r3, [r3, #3] 227; A9-NEXT: ldrb r6, [r4, #3] 228; A9-NEXT: add r3, r6 229; A9-NEXT: strb r3, [r5, #3] 230; A9-NEXT: bne .LBB3_1 231; A9-NEXT: @ %bb.2: @ %for.end 232; A9-NEXT: pop {r4, r5, r6, pc} 233entry: 234 br label %for.body 235 236for.body: ; preds = %for.body, %entry 237 %i.07 = phi i32 [ 0, %entry ], [ %inc.3, %for.body ] 238 %arrayidx = getelementptr inbounds i8, ptr %a, i32 %i.07 239 %0 = load i8, ptr %arrayidx, align 1 240 %conv5 = zext i8 %0 to i32 241 %arrayidx1 = getelementptr inbounds i8, ptr %b, i32 %i.07 242 %1 = load i8, ptr %arrayidx1, align 1 243 %conv26 = zext i8 %1 to i32 244 %add = add nsw i32 %conv26, %conv5 245 %conv3 = trunc i32 %add to i8 246 %arrayidx4 = getelementptr inbounds i8, ptr %c, i32 %i.07 247 store i8 %conv3, ptr %arrayidx4, align 1 248 %inc1 = or disjoint i32 %i.07, 1 249 %arrayidx.1 = getelementptr inbounds i8, ptr %a, i32 %inc1 250 %2 = load i8, ptr %arrayidx.1, align 1 251 %conv5.1 = zext i8 %2 to i32 252 %arrayidx1.1 = getelementptr inbounds i8, ptr %b, i32 %inc1 253 %3 = load i8, ptr %arrayidx1.1, align 1 254 %conv26.1 = zext i8 %3 to i32 255 %add.1 = add nsw i32 %conv26.1, %conv5.1 256 %conv3.1 = trunc i32 %add.1 to i8 257 %arrayidx4.1 = getelementptr inbounds i8, ptr %c, i32 %inc1 258 store i8 %conv3.1, ptr %arrayidx4.1, align 1 259 %inc.12 = or disjoint i32 %i.07, 2 260 %arrayidx.2 = getelementptr inbounds i8, ptr %a, i32 %inc.12 261 %4 = load i8, ptr %arrayidx.2, align 1 262 %conv5.2 = zext i8 %4 to i32 263 %arrayidx1.2 = getelementptr inbounds i8, ptr %b, i32 %inc.12 264 %5 = load i8, ptr %arrayidx1.2, align 1 265 %conv26.2 = zext i8 %5 to i32 266 %add.2 = add nsw i32 %conv26.2, %conv5.2 267 %conv3.2 = trunc i32 %add.2 to i8 268 %arrayidx4.2 = getelementptr inbounds i8, ptr %c, i32 %inc.12 269 store i8 %conv3.2, ptr %arrayidx4.2, align 1 270 %inc.23 = or disjoint i32 %i.07, 3 271 %arrayidx.3 = getelementptr inbounds i8, ptr %a, i32 %inc.23 272 %6 = load i8, ptr %arrayidx.3, align 1 273 %conv5.3 = zext i8 %6 to i32 274 %arrayidx1.3 = getelementptr inbounds i8, ptr %b, i32 %inc.23 275 %7 = load i8, ptr %arrayidx1.3, align 1 276 %conv26.3 = zext i8 %7 to i32 277 %add.3 = add nsw i32 %conv26.3, %conv5.3 278 %conv3.3 = trunc i32 %add.3 to i8 279 %arrayidx4.3 = getelementptr inbounds i8, ptr %c, i32 %inc.23 280 store i8 %conv3.3, ptr %arrayidx4.3, align 1 281 %inc.3 = add nsw i32 %i.07, 4 282 %exitcond.3 = icmp eq i32 %inc.3, 400 283 br i1 %exitcond.3, label %for.end, label %for.body 284 285for.end: ; preds = %for.body 286 ret void 287} 288 289; @testNeon is an important example of the nead for ivchains. 290; 291; Loads and stores should use post-increment addressing, no add's or add.w's. 292; Most importantly, there should be no spills or reloads! 293define hidden void @testNeon(ptr %ref_data, i32 %ref_stride, i32 %limit, ptr nocapture %data) nounwind optsize { 294; A9-LABEL: testNeon: 295; A9: @ %bb.0: 296; A9-NEXT: .save {r4, r5, r7, lr} 297; A9-NEXT: push {r4, r5, r7, lr} 298; A9-NEXT: vmov.i32 q8, #0x0 299; A9-NEXT: cmp r2, #1 300; A9-NEXT: blt .LBB4_4 301; A9-NEXT: @ %bb.1: @ %.lr.ph 302; A9-NEXT: movs r5, #0 303; A9-NEXT: movw r4, #64464 304; A9-NEXT: sub.w r12, r5, r2, lsl #6 305; A9-NEXT: sub.w lr, r1, r1, lsl #4 306; A9-NEXT: movt r4, #65535 307; A9-NEXT: mov r5, r3 308; A9-NEXT: .LBB4_2: @ =>This Inner Loop Header: Depth=1 309; A9-NEXT: vld1.64 {d18}, [r0], r1 310; A9-NEXT: subs r2, #1 311; A9-NEXT: vld1.64 {d19}, [r0], r1 312; A9-NEXT: vst1.8 {d18, d19}, [r5]! 313; A9-NEXT: vld1.64 {d20}, [r0], r1 314; A9-NEXT: vld1.64 {d21}, [r0], r1 315; A9-NEXT: vst1.8 {d20, d21}, [r5]! 316; A9-NEXT: vld1.64 {d22}, [r0], r1 317; A9-NEXT: vadd.i8 q9, q9, q10 318; A9-NEXT: vld1.64 {d23}, [r0], r1 319; A9-NEXT: vst1.8 {d22, d23}, [r5]! 320; A9-NEXT: vld1.64 {d20}, [r0], r1 321; A9-NEXT: vadd.i8 q9, q9, q11 322; A9-NEXT: vld1.64 {d21}, [r0], lr 323; A9-NEXT: vadd.i8 q9, q9, q10 324; A9-NEXT: vadd.i8 q8, q8, q9 325; A9-NEXT: vst1.8 {d20, d21}, [r5], r4 326; A9-NEXT: bne .LBB4_2 327; A9-NEXT: @ %bb.3: @ %._crit_edge 328; A9-NEXT: add.w r3, r3, r12, lsl #4 329; A9-NEXT: .LBB4_4: 330; A9-NEXT: vst1.32 {d16, d17}, [r3] 331; A9-NEXT: pop {r4, r5, r7, pc} 332 %1 = icmp sgt i32 %limit, 0 333 br i1 %1, label %.lr.ph, label %45 334 335.lr.ph: ; preds = %0 336 %2 = shl nsw i32 %ref_stride, 1 337 %3 = mul nsw i32 %ref_stride, 3 338 %4 = shl nsw i32 %ref_stride, 2 339 %5 = mul nsw i32 %ref_stride, 5 340 %6 = mul nsw i32 %ref_stride, 6 341 %7 = mul nsw i32 %ref_stride, 7 342 %8 = shl nsw i32 %ref_stride, 3 343 %9 = sub i32 0, %8 344 %10 = mul i32 %limit, -64 345 br label %11 346 347; <label>:11 ; preds = %11, %.lr.ph 348 %.05 = phi ptr [ %ref_data, %.lr.ph ], [ %42, %11 ] 349 %counter.04 = phi i32 [ 0, %.lr.ph ], [ %44, %11 ] 350 %result.03 = phi <16 x i8> [ zeroinitializer, %.lr.ph ], [ %41, %11 ] 351 %.012 = phi ptr [ %data, %.lr.ph ], [ %43, %11 ] 352 %12 = tail call <1 x i64> @llvm.arm.neon.vld1.v1i64.p0(ptr %.05, i32 1) nounwind 353 %13 = getelementptr inbounds i8, ptr %.05, i32 %ref_stride 354 %14 = tail call <1 x i64> @llvm.arm.neon.vld1.v1i64.p0(ptr %13, i32 1) nounwind 355 %15 = shufflevector <1 x i64> %12, <1 x i64> %14, <2 x i32> <i32 0, i32 1> 356 %16 = bitcast <2 x i64> %15 to <16 x i8> 357 %17 = getelementptr inbounds <16 x i8>, ptr %.012, i32 1 358 store <16 x i8> %16, ptr %.012, align 4 359 %18 = getelementptr inbounds i8, ptr %.05, i32 %2 360 %19 = tail call <1 x i64> @llvm.arm.neon.vld1.v1i64.p0(ptr %18, i32 1) nounwind 361 %20 = getelementptr inbounds i8, ptr %.05, i32 %3 362 %21 = tail call <1 x i64> @llvm.arm.neon.vld1.v1i64.p0(ptr %20, i32 1) nounwind 363 %22 = shufflevector <1 x i64> %19, <1 x i64> %21, <2 x i32> <i32 0, i32 1> 364 %23 = bitcast <2 x i64> %22 to <16 x i8> 365 %24 = getelementptr inbounds <16 x i8>, ptr %.012, i32 2 366 store <16 x i8> %23, ptr %17, align 4 367 %25 = getelementptr inbounds i8, ptr %.05, i32 %4 368 %26 = tail call <1 x i64> @llvm.arm.neon.vld1.v1i64.p0(ptr %25, i32 1) nounwind 369 %27 = getelementptr inbounds i8, ptr %.05, i32 %5 370 %28 = tail call <1 x i64> @llvm.arm.neon.vld1.v1i64.p0(ptr %27, i32 1) nounwind 371 %29 = shufflevector <1 x i64> %26, <1 x i64> %28, <2 x i32> <i32 0, i32 1> 372 %30 = bitcast <2 x i64> %29 to <16 x i8> 373 %31 = getelementptr inbounds <16 x i8>, ptr %.012, i32 3 374 store <16 x i8> %30, ptr %24, align 4 375 %32 = getelementptr inbounds i8, ptr %.05, i32 %6 376 %33 = tail call <1 x i64> @llvm.arm.neon.vld1.v1i64.p0(ptr %32, i32 1) nounwind 377 %34 = getelementptr inbounds i8, ptr %.05, i32 %7 378 %35 = tail call <1 x i64> @llvm.arm.neon.vld1.v1i64.p0(ptr %34, i32 1) nounwind 379 %36 = shufflevector <1 x i64> %33, <1 x i64> %35, <2 x i32> <i32 0, i32 1> 380 %37 = bitcast <2 x i64> %36 to <16 x i8> 381 store <16 x i8> %37, ptr %31, align 4 382 %38 = add <16 x i8> %16, %23 383 %39 = add <16 x i8> %38, %30 384 %40 = add <16 x i8> %39, %37 385 %41 = add <16 x i8> %result.03, %40 386 %42 = getelementptr i8, ptr %.05, i32 %9 387 %43 = getelementptr inbounds <16 x i8>, ptr %.012, i32 -64 388 %44 = add nsw i32 %counter.04, 1 389 %exitcond = icmp eq i32 %44, %limit 390 br i1 %exitcond, label %._crit_edge, label %11 391 392._crit_edge: ; preds = %11 393 %scevgep = getelementptr <16 x i8>, ptr %data, i32 %10 394 br label %45 395 396; <label>:45 ; preds = %._crit_edge, %0 397 %result.0.lcssa = phi <16 x i8> [ %41, %._crit_edge ], [ zeroinitializer, %0 ] 398 %.01.lcssa = phi ptr [ %scevgep, %._crit_edge ], [ %data, %0 ] 399 store <16 x i8> %result.0.lcssa, ptr %.01.lcssa, align 4 400 ret void 401} 402 403declare <1 x i64> @llvm.arm.neon.vld1.v1i64.p0(ptr, i32) nounwind readonly 404 405; Handle chains in which the same offset is used for both loads and 406; stores to the same array. 407; rdar://11410078. 408define void @testReuse(ptr %src, i32 %stride) nounwind ssp { 409; A9-LABEL: testReuse: 410; A9: @ %bb.0: @ %entry 411; A9-NEXT: sub.w r12, r0, r1, lsl #2 412; A9-NEXT: sub.w r0, r1, r1, lsl #2 413; A9-NEXT: lsls r2, r0, #1 414; A9-NEXT: movs r3, #0 415; A9-NEXT: .LBB5_1: @ %for.body 416; A9-NEXT: @ =>This Inner Loop Header: Depth=1 417; A9-NEXT: add.w r0, r12, r3 418; A9-NEXT: adds r3, #8 419; A9-NEXT: vld1.8 {d16}, [r0], r1 420; A9-NEXT: cmp r3, #32 421; A9-NEXT: vld1.8 {d17}, [r0], r1 422; A9-NEXT: vhadd.u8 d16, d16, d17 423; A9-NEXT: vld1.8 {d18}, [r0], r1 424; A9-NEXT: vhadd.u8 d17, d17, d18 425; A9-NEXT: vld1.8 {d19}, [r0], r1 426; A9-NEXT: vhadd.u8 d18, d18, d19 427; A9-NEXT: vld1.8 {d20}, [r0], r1 428; A9-NEXT: vhadd.u8 d19, d19, d20 429; A9-NEXT: vld1.8 {d21}, [r0], r1 430; A9-NEXT: vhadd.u8 d20, d20, d21 431; A9-NEXT: vld1.8 {d22}, [r0], r1 432; A9-NEXT: vhadd.u8 d21, d21, d22 433; A9-NEXT: vld1.8 {d23}, [r0], r2 434; A9-NEXT: vst1.8 {d16}, [r0], r1 435; A9-NEXT: vst1.8 {d17}, [r0], r1 436; A9-NEXT: vst1.8 {d18}, [r0], r1 437; A9-NEXT: vst1.8 {d19}, [r0], r1 438; A9-NEXT: vst1.8 {d20}, [r0], r1 439; A9-NEXT: vst1.8 {d21}, [r0] 440; A9-NEXT: bne .LBB5_1 441; A9-NEXT: @ %bb.2: @ %for.end 442; A9-NEXT: bx lr 443entry: 444 %mul = shl nsw i32 %stride, 2 445 %idx.neg = sub i32 0, %mul 446 %mul1 = mul nsw i32 %stride, 3 447 %idx.neg2 = sub i32 0, %mul1 448 %mul5 = shl nsw i32 %stride, 1 449 %idx.neg6 = sub i32 0, %mul5 450 %idx.neg10 = sub i32 0, %stride 451 br label %for.body 452 453for.body: ; preds = %for.body, %entry 454 %i.0110 = phi i32 [ 0, %entry ], [ %inc, %for.body ] 455 %src.addr = phi ptr [ %src, %entry ], [ %add.ptr45, %for.body ] 456 %add.ptr = getelementptr inbounds i8, ptr %src.addr, i32 %idx.neg 457 %vld1 = tail call <8 x i8> @llvm.arm.neon.vld1.v8i8.p0(ptr %add.ptr, i32 1) 458 %add.ptr3 = getelementptr inbounds i8, ptr %src.addr, i32 %idx.neg2 459 %vld2 = tail call <8 x i8> @llvm.arm.neon.vld1.v8i8.p0(ptr %add.ptr3, i32 1) 460 %add.ptr7 = getelementptr inbounds i8, ptr %src.addr, i32 %idx.neg6 461 %vld3 = tail call <8 x i8> @llvm.arm.neon.vld1.v8i8.p0(ptr %add.ptr7, i32 1) 462 %add.ptr11 = getelementptr inbounds i8, ptr %src.addr, i32 %idx.neg10 463 %vld4 = tail call <8 x i8> @llvm.arm.neon.vld1.v8i8.p0(ptr %add.ptr11, i32 1) 464 %vld5 = tail call <8 x i8> @llvm.arm.neon.vld1.v8i8.p0(ptr %src.addr, i32 1) 465 %add.ptr17 = getelementptr inbounds i8, ptr %src.addr, i32 %stride 466 %vld6 = tail call <8 x i8> @llvm.arm.neon.vld1.v8i8.p0(ptr %add.ptr17, i32 1) 467 %add.ptr20 = getelementptr inbounds i8, ptr %src.addr, i32 %mul5 468 %vld7 = tail call <8 x i8> @llvm.arm.neon.vld1.v8i8.p0(ptr %add.ptr20, i32 1) 469 %add.ptr23 = getelementptr inbounds i8, ptr %src.addr, i32 %mul1 470 %vld8 = tail call <8 x i8> @llvm.arm.neon.vld1.v8i8.p0(ptr %add.ptr23, i32 1) 471 %vadd1 = tail call <8 x i8> @llvm.arm.neon.vhaddu.v8i8(<8 x i8> %vld1, <8 x i8> %vld2) nounwind 472 %vadd2 = tail call <8 x i8> @llvm.arm.neon.vhaddu.v8i8(<8 x i8> %vld2, <8 x i8> %vld3) nounwind 473 %vadd3 = tail call <8 x i8> @llvm.arm.neon.vhaddu.v8i8(<8 x i8> %vld3, <8 x i8> %vld4) nounwind 474 %vadd4 = tail call <8 x i8> @llvm.arm.neon.vhaddu.v8i8(<8 x i8> %vld4, <8 x i8> %vld5) nounwind 475 %vadd5 = tail call <8 x i8> @llvm.arm.neon.vhaddu.v8i8(<8 x i8> %vld5, <8 x i8> %vld6) nounwind 476 %vadd6 = tail call <8 x i8> @llvm.arm.neon.vhaddu.v8i8(<8 x i8> %vld6, <8 x i8> %vld7) nounwind 477 tail call void @llvm.arm.neon.vst1.p0.v8i8(ptr %add.ptr3, <8 x i8> %vadd1, i32 1) 478 tail call void @llvm.arm.neon.vst1.p0.v8i8(ptr %add.ptr7, <8 x i8> %vadd2, i32 1) 479 tail call void @llvm.arm.neon.vst1.p0.v8i8(ptr %add.ptr11, <8 x i8> %vadd3, i32 1) 480 tail call void @llvm.arm.neon.vst1.p0.v8i8(ptr %src.addr, <8 x i8> %vadd4, i32 1) 481 tail call void @llvm.arm.neon.vst1.p0.v8i8(ptr %add.ptr17, <8 x i8> %vadd5, i32 1) 482 tail call void @llvm.arm.neon.vst1.p0.v8i8(ptr %add.ptr20, <8 x i8> %vadd6, i32 1) 483 %inc = add nsw i32 %i.0110, 1 484 %add.ptr45 = getelementptr inbounds i8, ptr %src.addr, i32 8 485 %exitcond = icmp eq i32 %inc, 4 486 br i1 %exitcond, label %for.end, label %for.body 487 488for.end: ; preds = %for.body 489 ret void 490} 491 492declare <8 x i8> @llvm.arm.neon.vld1.v8i8.p0(ptr, i32) nounwind readonly 493 494declare void @llvm.arm.neon.vst1.p0.v8i8(ptr, <8 x i8>, i32) nounwind 495 496declare <8 x i8> @llvm.arm.neon.vhaddu.v8i8(<8 x i8>, <8 x i8>) nounwind readnone 497