1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 2; RUN: opt -mtriple=amdgcn -loop-reduce -S < %s | FileCheck %s 3; REQUIRES: asserts 4 5; Test that LSR does not attempt to extend a pointer type to an integer type, 6; which causes a SCEV analysis assertion. 7 8target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8:9" 9 10target triple = "amdgcn-amd-amdhsa" 11 12@gVar = external hidden local_unnamed_addr addrspace(3) global [1024 x double], align 16 13 14define amdgpu_kernel void @scaledregtest() local_unnamed_addr { 15; CHECK-LABEL: @scaledregtest( 16; CHECK-NEXT: entry: 17; CHECK-NEXT: br label [[FOR_BODY:%.*]] 18; CHECK: loopexit: 19; CHECK-NEXT: [[SCEVGEP11_LCSSA:%.*]] = phi ptr addrspace(5) [ [[SCEVGEP11:%.*]], [[FOR_BODY]] ] 20; CHECK-NEXT: [[SCEVGEP13_LCSSA:%.*]] = phi ptr [ [[SCEVGEP13:%.*]], [[FOR_BODY]] ] 21; CHECK-NEXT: br label [[FOR_BODY_1:%.*]] 22; CHECK: for.body.1: 23; CHECK-NEXT: [[LSR_IV5:%.*]] = phi ptr addrspace(5) [ [[SCEVGEP6:%.*]], [[FOR_BODY_1]] ], [ [[SCEVGEP11_LCSSA]], [[LOOPEXIT:%.*]] ] 24; CHECK-NEXT: [[LSR_IV1:%.*]] = phi ptr [ [[SCEVGEP2:%.*]], [[FOR_BODY_1]] ], [ [[SCEVGEP13_LCSSA]], [[LOOPEXIT]] ] 25; CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr addrspace(5) [[LSR_IV5]], align 8 26; CHECK-NEXT: store ptr [[TMP0]], ptr [[LSR_IV1]], align 8 27; CHECK-NEXT: [[SCEVGEP2]] = getelementptr i8, ptr [[LSR_IV1]], i64 8 28; CHECK-NEXT: [[SCEVGEP6]] = getelementptr i8, ptr addrspace(5) [[LSR_IV5]], i32 8 29; CHECK-NEXT: br label [[FOR_BODY_1]] 30; CHECK: for.body: 31; CHECK-NEXT: [[LSR_IV12:%.*]] = phi ptr [ [[SCEVGEP13]], [[FOR_BODY]] ], [ null, [[ENTRY:%.*]] ] 32; CHECK-NEXT: [[LSR_IV10:%.*]] = phi ptr addrspace(5) [ [[SCEVGEP11]], [[FOR_BODY]] ], [ null, [[ENTRY]] ] 33; CHECK-NEXT: [[SCEVGEP11]] = getelementptr i8, ptr addrspace(5) [[LSR_IV10]], i32 64 34; CHECK-NEXT: [[SCEVGEP13]] = getelementptr i8, ptr [[LSR_IV12]], i64 64 35; CHECK-NEXT: br i1 false, label [[LOOPEXIT]], label [[FOR_BODY]] 36; 37entry: 38 br label %for.body 39 40loopexit: 41 %conv = zext i32 %inc to i64 42 br label %for.body.1 43 44for.body.1: 45 %conv.1 = phi i64 [ %conv.2, %for.body.1 ], [ %conv, %loopexit ] 46 %I.1 = phi i32 [ %inc.1, %for.body.1 ], [ %inc, %loopexit ] 47 %idxprom = trunc i64 %conv.1 to i32 48 %arrayidx = getelementptr inbounds ptr, ptr addrspace(5) null, i32 %idxprom 49 %0 = load ptr, ptr addrspace(5) %arrayidx, align 8 50 %arrayidx.1 = getelementptr inbounds ptr, ptr null, i64 %conv.1 51 store ptr %0, ptr %arrayidx.1, align 8 52 %inc.1 = add nuw nsw i32 %I.1, 1 53 %conv.2 = zext i32 %inc.1 to i64 54 br label %for.body.1 55 56for.body: 57 %I = phi i32 [ 0, %entry ], [ %inc, %for.body ] 58 %inc = add nuw nsw i32 %I, 8 59 br i1 false, label %loopexit, label %for.body 60} 61 62define protected amdgpu_kernel void @baseregtest(i32 %n, i32 %lda, i1 %arg) local_unnamed_addr { 63; CHECK-LABEL: @baseregtest( 64; CHECK-NEXT: entry: 65; CHECK-NEXT: br i1 %arg, label [[EXIT:%.*]], label [[IF_END:%.*]] 66; CHECK: if.end: 67; CHECK-NEXT: [[TMP0:%.*]] = tail call i32 @foo() 68; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[TMP0]], 3 69; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr addrspace(3) @gVar, i32 [[TMP1]] 70; CHECK-NEXT: [[TMP2:%.*]] = shl i32 [[N:%.*]], 3 71; CHECK-NEXT: [[TMP3:%.*]] = sext i32 [[TMP0]] to i64 72; CHECK-NEXT: [[TMP4:%.*]] = shl nsw i64 [[TMP3]], 3 73; CHECK-NEXT: [[SCEVGEP2:%.*]] = getelementptr i8, ptr addrspace(1) null, i64 [[TMP4]] 74; CHECK-NEXT: [[TMP5:%.*]] = sext i32 [[LDA:%.*]] to i64 75; CHECK-NEXT: [[TMP6:%.*]] = shl nsw i64 [[TMP5]], 3 76; CHECK-NEXT: br label [[FOR_BODY:%.*]] 77; CHECK: for.body: 78; CHECK-NEXT: [[LSR_IV3:%.*]] = phi ptr addrspace(1) [ [[SCEVGEP4:%.*]], [[FOR_BODY]] ], [ [[SCEVGEP2]], [[IF_END]] ] 79; CHECK-NEXT: [[LSR_IV:%.*]] = phi ptr addrspace(3) [ [[SCEVGEP1:%.*]], [[FOR_BODY]] ], [ [[SCEVGEP]], [[IF_END]] ] 80; CHECK-NEXT: [[TMP7:%.*]] = load double, ptr addrspace(1) [[LSR_IV3]], align 8 81; CHECK-NEXT: store double [[TMP7]], ptr addrspace(3) [[LSR_IV]], align 8 82; CHECK-NEXT: [[SCEVGEP1]] = getelementptr i8, ptr addrspace(3) [[LSR_IV]], i32 [[TMP2]] 83; CHECK-NEXT: [[SCEVGEP4]] = getelementptr i8, ptr addrspace(1) [[LSR_IV3]], i64 [[TMP6]] 84; CHECK-NEXT: br label [[FOR_BODY]] 85; CHECK: exit: 86; CHECK-NEXT: ret void 87; 88entry: 89 br i1 %arg, label %exit, label %if.end 90 91if.end: 92 %0 = tail call i32 @foo() 93 br label %for.body 94 95for.body: 96 %i = phi i32 [ %inc, %for.body ], [ 0, %if.end ] 97 %mul1 = mul nsw i32 %i, %lda 98 %add1 = add nsw i32 %mul1, %0 99 %idxprom = sext i32 %add1 to i64 100 %arrayidx = getelementptr inbounds double, ptr addrspace(1) null, i64 %idxprom 101 %1 = load double, ptr addrspace(1) %arrayidx, align 8 102 %mul2 = mul nsw i32 %i, %n 103 %add2 = add nsw i32 %mul2, %0 104 %arrayidx9110 = getelementptr inbounds [1024 x double], ptr addrspace(3) @gVar, i32 0, i32 %add2 105 store double %1, ptr addrspace(3) %arrayidx9110, align 8 106 %inc = add nuw nsw i32 %i, 1 107 br label %for.body 108 109exit: 110 ret void 111} 112 113declare i32 @foo() 114