xref: /llvm-project/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/missing-alignment.ll (revision f0415f2a456d54daaa231c228d2c9f4ef2ce9b89)
1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2; RUN: opt -mtriple=amdgcn-- -mcpu=tonga -passes=load-store-vectorizer -S -o - %s | FileCheck %s
3
4target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5"
5
6@lds = internal addrspace(3) global [512 x float] undef, align 4
7
8; The original load has an implicit alignment of 4, and should not
9; increase to an align 8 load.
10
11define amdgpu_kernel void @load_keep_base_alignment_missing_align(ptr addrspace(1) %out) {
12; CHECK-LABEL: @load_keep_base_alignment_missing_align(
13; CHECK-NEXT:    [[PTR0:%.*]] = getelementptr inbounds [512 x float], ptr addrspace(3) @lds, i32 0, i32 11
14; CHECK-NEXT:    [[TMP2:%.*]] = load <2 x float>, ptr addrspace(3) [[PTR0]], align 4
15; CHECK-NEXT:    [[VAL01:%.*]] = extractelement <2 x float> [[TMP2]], i32 0
16; CHECK-NEXT:    [[VAL12:%.*]] = extractelement <2 x float> [[TMP2]], i32 1
17; CHECK-NEXT:    [[ADD:%.*]] = fadd float [[VAL01]], [[VAL12]]
18; CHECK-NEXT:    store float [[ADD]], ptr addrspace(1) [[OUT:%.*]], align 4
19; CHECK-NEXT:    ret void
20;
21  %ptr0 = getelementptr inbounds [512 x float], ptr addrspace(3) @lds, i32 0, i32 11
22  %val0 = load float, ptr addrspace(3) %ptr0
23
24  %ptr1 = getelementptr inbounds [512 x float], ptr addrspace(3) @lds, i32 0, i32 12
25  %val1 = load float, ptr addrspace(3) %ptr1
26  %add = fadd float %val0, %val1
27  store float %add, ptr addrspace(1) %out
28  ret void
29}
30
31define amdgpu_kernel void @store_keep_base_alignment_missing_align() {
32; CHECK-LABEL: @store_keep_base_alignment_missing_align(
33; CHECK-NEXT:    [[ARRAYIDX0:%.*]] = getelementptr inbounds [512 x float], ptr addrspace(3) @lds, i32 0, i32 1
34; CHECK-NEXT:    store <2 x float> zeroinitializer, ptr addrspace(3) [[ARRAYIDX0]], align 4
35; CHECK-NEXT:    ret void
36;
37  %arrayidx0 = getelementptr inbounds [512 x float], ptr addrspace(3) @lds, i32 0, i32 1
38  %arrayidx1 = getelementptr inbounds [512 x float], ptr addrspace(3) @lds, i32 0, i32 2
39  store float 0.0, ptr addrspace(3) %arrayidx0
40  store float 0.0, ptr addrspace(3) %arrayidx1
41  ret void
42}
43