xref: /llvm-project/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/merge-vectors.ll (revision 916425b2d1644cad3dc96c52d27a78f523472bb7)
1; RUN: opt -mtriple=amdgcn-amd-amdhsa -passes=load-store-vectorizer -S -o - %s | FileCheck %s
2
3target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-ni:7"
4
5; CHECK-LABEL: @merge_v2i32_v2i32(
6; CHECK: load <4 x i32>
7; CHECK: store <4 x i32> zeroinitializer
8define amdgpu_kernel void @merge_v2i32_v2i32(ptr addrspace(1) nocapture %a, ptr addrspace(1) nocapture readonly %b) #0 {
9entry:
10  %a.1 = getelementptr inbounds <2 x i32>, ptr addrspace(1) %a, i64 1
11  %b.1 = getelementptr inbounds <2 x i32>, ptr addrspace(1) %b, i64 1
12
13  %ld.c = load <2 x i32>, ptr addrspace(1) %b, align 4
14  %ld.c.idx.1 = load <2 x i32>, ptr addrspace(1) %b.1, align 4
15
16  store <2 x i32> zeroinitializer, ptr addrspace(1) %a, align 4
17  store <2 x i32> zeroinitializer, ptr addrspace(1) %a.1, align 4
18
19  ret void
20}
21
22; CHECK-LABEL: @merge_v1i32_v1i32(
23; CHECK: load <2 x i32>
24; CHECK: store <2 x i32> zeroinitializer
25define amdgpu_kernel void @merge_v1i32_v1i32(ptr addrspace(1) nocapture %a, ptr addrspace(1) nocapture readonly %b) #0 {
26entry:
27  %a.1 = getelementptr inbounds <1 x i32>, ptr addrspace(1) %a, i64 1
28  %b.1 = getelementptr inbounds <1 x i32>, ptr addrspace(1) %b, i64 1
29
30  %ld.c = load <1 x i32>, ptr addrspace(1) %b, align 4
31  %ld.c.idx.1 = load <1 x i32>, ptr addrspace(1) %b.1, align 4
32
33  store <1 x i32> zeroinitializer, ptr addrspace(1) %a, align 4
34  store <1 x i32> zeroinitializer, ptr addrspace(1) %a.1, align 4
35
36  ret void
37}
38
39; CHECK-LABEL: @no_merge_v3i32_v3i32(
40; CHECK: load <3 x i32>
41; CHECK: load <3 x i32>
42; CHECK: store <3 x i32> zeroinitializer
43; CHECK: store <3 x i32> zeroinitializer
44define amdgpu_kernel void @no_merge_v3i32_v3i32(ptr addrspace(1) nocapture %a, ptr addrspace(1) nocapture readonly %b) #0 {
45entry:
46  %a.1 = getelementptr inbounds <3 x i32>, ptr addrspace(1) %a, i64 1
47  %b.1 = getelementptr inbounds <3 x i32>, ptr addrspace(1) %b, i64 1
48
49  %ld.c = load <3 x i32>, ptr addrspace(1) %b, align 4
50  %ld.c.idx.1 = load <3 x i32>, ptr addrspace(1) %b.1, align 4
51
52  store <3 x i32> zeroinitializer, ptr addrspace(1) %a, align 4
53  store <3 x i32> zeroinitializer, ptr addrspace(1) %a.1, align 4
54
55  ret void
56}
57
58; CHECK-LABEL: @merge_v2i16_v2i16(
59; CHECK: load <4 x i16>
60; CHECK: store <4 x i16> zeroinitializer
61define amdgpu_kernel void @merge_v2i16_v2i16(ptr addrspace(1) nocapture %a, ptr addrspace(1) nocapture readonly %b) #0 {
62entry:
63  %a.1 = getelementptr inbounds <2 x i16>, ptr addrspace(1) %a, i64 1
64  %b.1 = getelementptr inbounds <2 x i16>, ptr addrspace(1) %b, i64 1
65
66  %ld.c = load <2 x i16>, ptr addrspace(1) %b, align 4
67  %ld.c.idx.1 = load <2 x i16>, ptr addrspace(1) %b.1, align 4
68
69  store <2 x i16> zeroinitializer, ptr addrspace(1) %a, align 4
70  store <2 x i16> zeroinitializer, ptr addrspace(1) %a.1, align 4
71
72  ret void
73}
74
75; CHECK-LABEL: @merge_fat_ptrs(
76; CHECK: load <4 x i16>
77; CHECK: store <4 x i16> zeroinitializer
78define amdgpu_kernel void @merge_fat_ptrs(ptr addrspace(7) nocapture %a, ptr addrspace(7) nocapture readonly %b) #0 {
79entry:
80  %a.1 = getelementptr inbounds <2 x i16>, ptr addrspace(7) %a, i32 1
81  %b.1 = getelementptr inbounds <2 x i16>, ptr addrspace(7) %b, i32 1
82
83  %ld.c = load <2 x i16>, ptr addrspace(7) %b, align 4
84  %ld.c.idx.1 = load <2 x i16>, ptr addrspace(7) %b.1, align 4
85
86  store <2 x i16> zeroinitializer, ptr addrspace(7) %a, align 4
87  store <2 x i16> zeroinitializer, ptr addrspace(7) %a.1, align 4
88
89  ret void
90}
91
92; Ideally this would be merged
93; CHECK-LABEL: @merge_load_i32_v2i16(
94; CHECK: load i32,
95; CHECK: load <2 x i16>
96define amdgpu_kernel void @merge_load_i32_v2i16(ptr addrspace(1) nocapture %a) #0 {
97entry:
98  %a.1 = getelementptr inbounds i32, ptr addrspace(1) %a, i32 1
99
100  %ld.0 = load i32, ptr addrspace(1) %a
101  %ld.1 = load <2 x i16>, ptr addrspace(1) %a.1
102
103  ret void
104}
105
106attributes #0 = { nounwind }
107attributes #1 = { nounwind readnone }
108