1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 2; RUN: opt < %s -passes=instsimplify -S | FileCheck %s 3 4define i47 @shl_by_0(i47 %A) { 5; CHECK-LABEL: @shl_by_0( 6; CHECK-NEXT: ret i47 [[A:%.*]] 7; 8 %B = shl i47 %A, 0 9 ret i47 %B 10} 11 12define i41 @shl_0(i41 %X) { 13; CHECK-LABEL: @shl_0( 14; CHECK-NEXT: ret i41 0 15; 16 %B = shl i41 0, %X 17 ret i41 %B 18} 19 20define <2 x i41> @shl_0_vec_poison_elt(<2 x i41> %X) { 21; CHECK-LABEL: @shl_0_vec_poison_elt( 22; CHECK-NEXT: ret <2 x i41> zeroinitializer 23; 24 %B = shl <2 x i41> <i41 0, i41 poison>, %X 25 ret <2 x i41> %B 26} 27 28define i41 @ashr_by_0(i41 %A) { 29; CHECK-LABEL: @ashr_by_0( 30; CHECK-NEXT: ret i41 [[A:%.*]] 31; 32 %B = ashr i41 %A, 0 33 ret i41 %B 34} 35 36define i39 @ashr_0(i39 %X) { 37; CHECK-LABEL: @ashr_0( 38; CHECK-NEXT: ret i39 0 39; 40 %B = ashr i39 0, %X 41 ret i39 %B 42} 43 44define <2 x i141> @ashr_0_vec_poison_elt(<2 x i141> %X) { 45; CHECK-LABEL: @ashr_0_vec_poison_elt( 46; CHECK-NEXT: ret <2 x i141> zeroinitializer 47; 48 %B = shl <2 x i141> <i141 poison, i141 0>, %X 49 ret <2 x i141> %B 50} 51 52define i55 @lshr_by_bitwidth(i55 %A) { 53; CHECK-LABEL: @lshr_by_bitwidth( 54; CHECK-NEXT: ret i55 poison 55; 56 %B = lshr i55 %A, 55 57 ret i55 %B 58} 59 60define i32 @shl_by_bitwidth(i32 %A) { 61; CHECK-LABEL: @shl_by_bitwidth( 62; CHECK-NEXT: ret i32 poison 63; 64 %B = shl i32 %A, 32 65 ret i32 %B 66} 67 68define <4 x i32> @lshr_by_bitwidth_splat(<4 x i32> %A) { 69; CHECK-LABEL: @lshr_by_bitwidth_splat( 70; CHECK-NEXT: ret <4 x i32> poison 71; 72 %B = lshr <4 x i32> %A, <i32 32, i32 32, i32 32, i32 32> ;; shift all bits out 73 ret <4 x i32> %B 74} 75 76define <4 x i32> @lshr_by_0_splat(<4 x i32> %A) { 77; CHECK-LABEL: @lshr_by_0_splat( 78; CHECK-NEXT: ret <4 x i32> [[A:%.*]] 79; 80 %B = lshr <4 x i32> %A, zeroinitializer 81 ret <4 x i32> %B 82} 83 84define <4 x i32> @shl_by_bitwidth_splat(<4 x i32> %A) { 85; CHECK-LABEL: @shl_by_bitwidth_splat( 86; CHECK-NEXT: ret <4 x i32> poison 87; 88 %B = shl <4 x i32> %A, <i32 32, i32 32, i32 32, i32 32> ;; shift all bits out 89 ret <4 x i32> %B 90} 91 92define i32 @ashr_undef() { 93; CHECK-LABEL: @ashr_undef( 94; CHECK-NEXT: ret i32 0 95; 96 %B = ashr i32 undef, 2 ;; top two bits must be equal, so not undef 97 ret i32 %B 98} 99 100define i32 @ashr_undef_variable_shift_amount(i32 %A) { 101; CHECK-LABEL: @ashr_undef_variable_shift_amount( 102; CHECK-NEXT: ret i32 0 103; 104 %B = ashr i32 undef, %A ;; top %A bits must be equal, so not undef 105 ret i32 %B 106} 107 108define i32 @ashr_all_ones(i32 %A) { 109; CHECK-LABEL: @ashr_all_ones( 110; CHECK-NEXT: ret i32 -1 111; 112 %B = ashr i32 -1, %A 113 ret i32 %B 114} 115 116define <3 x i8> @ashr_all_ones_vec_with_poison_elts(<3 x i8> %x, <3 x i8> %y) { 117; CHECK-LABEL: @ashr_all_ones_vec_with_poison_elts( 118; CHECK-NEXT: ret <3 x i8> splat (i8 -1) 119; 120 %sh = ashr <3 x i8> <i8 poison, i8 -1, i8 poison>, %y 121 ret <3 x i8> %sh 122} 123 124define i8 @lshr_by_sext_bool(i1 %x, i8 %y) { 125; CHECK-LABEL: @lshr_by_sext_bool( 126; CHECK-NEXT: ret i8 [[Y:%.*]] 127; 128 %s = sext i1 %x to i8 129 %r = lshr i8 %y, %s 130 ret i8 %r 131} 132 133define <2 x i8> @lshr_by_sext_bool_vec(<2 x i1> %x, <2 x i8> %y) { 134; CHECK-LABEL: @lshr_by_sext_bool_vec( 135; CHECK-NEXT: ret <2 x i8> [[Y:%.*]] 136; 137 %s = sext <2 x i1> %x to <2 x i8> 138 %r = lshr <2 x i8> %y, %s 139 ret <2 x i8> %r 140} 141 142define i8 @ashr_by_sext_bool(i1 %x, i8 %y) { 143; CHECK-LABEL: @ashr_by_sext_bool( 144; CHECK-NEXT: ret i8 [[Y:%.*]] 145; 146 %s = sext i1 %x to i8 147 %r = ashr i8 %y, %s 148 ret i8 %r 149} 150 151define <2 x i8> @ashr_by_sext_bool_vec(<2 x i1> %x, <2 x i8> %y) { 152; CHECK-LABEL: @ashr_by_sext_bool_vec( 153; CHECK-NEXT: ret <2 x i8> [[Y:%.*]] 154; 155 %s = sext <2 x i1> %x to <2 x i8> 156 %r = ashr <2 x i8> %y, %s 157 ret <2 x i8> %r 158} 159 160define i8 @shl_by_sext_bool(i1 %x, i8 %y) { 161; CHECK-LABEL: @shl_by_sext_bool( 162; CHECK-NEXT: ret i8 [[Y:%.*]] 163; 164 %s = sext i1 %x to i8 165 %r = shl i8 %y, %s 166 ret i8 %r 167} 168 169define <2 x i8> @shl_by_sext_bool_vec(<2 x i1> %x, <2 x i8> %y) { 170; CHECK-LABEL: @shl_by_sext_bool_vec( 171; CHECK-NEXT: ret <2 x i8> [[Y:%.*]] 172; 173 %s = sext <2 x i1> %x to <2 x i8> 174 %r = shl <2 x i8> %y, %s 175 ret <2 x i8> %r 176} 177 178define i64 @shl_or_shr(i32 %a, i32 %b) { 179; CHECK-LABEL: @shl_or_shr( 180; CHECK-NEXT: [[T1:%.*]] = zext i32 [[A:%.*]] to i64 181; CHECK-NEXT: ret i64 [[T1]] 182; 183 %t1 = zext i32 %a to i64 184 %t2 = zext i32 %b to i64 185 %t3 = shl nuw i64 %t1, 32 186 %t4 = or i64 %t2, %t3 187 %t5 = lshr i64 %t4, 32 188 ret i64 %t5 189} 190 191; Since shift count of shl is smaller than the size of %b, OR cannot be eliminated. 192define i64 @shl_or_shr2(i32 %a, i32 %b) { 193; CHECK-LABEL: @shl_or_shr2( 194; CHECK-NEXT: [[T1:%.*]] = zext i32 [[A:%.*]] to i64 195; CHECK-NEXT: [[T2:%.*]] = zext i32 [[B:%.*]] to i64 196; CHECK-NEXT: [[T3:%.*]] = shl nuw i64 [[T1]], 31 197; CHECK-NEXT: [[T4:%.*]] = or i64 [[T2]], [[T3]] 198; CHECK-NEXT: [[T5:%.*]] = lshr i64 [[T4]], 31 199; CHECK-NEXT: ret i64 [[T5]] 200; 201 %t1 = zext i32 %a to i64 202 %t2 = zext i32 %b to i64 203 %t3 = shl nuw i64 %t1, 31 204 %t4 = or i64 %t2, %t3 205 %t5 = lshr i64 %t4, 31 206 ret i64 %t5 207} 208 209; Unit test for vector integer 210define <2 x i64> @shl_or_shr1v(<2 x i32> %a, <2 x i32> %b) { 211; CHECK-LABEL: @shl_or_shr1v( 212; CHECK-NEXT: [[T1:%.*]] = zext <2 x i32> [[A:%.*]] to <2 x i64> 213; CHECK-NEXT: ret <2 x i64> [[T1]] 214; 215 %t1 = zext <2 x i32> %a to <2 x i64> 216 %t2 = zext <2 x i32> %b to <2 x i64> 217 %t3 = shl nuw <2 x i64> %t1, <i64 32, i64 32> 218 %t4 = or <2 x i64> %t3, %t2 219 %t5 = lshr <2 x i64> %t4, <i64 32, i64 32> 220 ret <2 x i64> %t5 221} 222 223; Negative unit test for vector integer 224define <2 x i64> @shl_or_shr2v(<2 x i32> %a, <2 x i32> %b) { 225; CHECK-LABEL: @shl_or_shr2v( 226; CHECK-NEXT: [[T1:%.*]] = zext <2 x i32> [[A:%.*]] to <2 x i64> 227; CHECK-NEXT: [[T2:%.*]] = zext <2 x i32> [[B:%.*]] to <2 x i64> 228; CHECK-NEXT: [[T3:%.*]] = shl nuw <2 x i64> [[T1]], splat (i64 31) 229; CHECK-NEXT: [[T4:%.*]] = or <2 x i64> [[T2]], [[T3]] 230; CHECK-NEXT: [[T5:%.*]] = lshr <2 x i64> [[T4]], splat (i64 31) 231; CHECK-NEXT: ret <2 x i64> [[T5]] 232; 233 %t1 = zext <2 x i32> %a to <2 x i64> 234 %t2 = zext <2 x i32> %b to <2 x i64> 235 %t3 = shl nuw <2 x i64> %t1, <i64 31, i64 31> 236 %t4 = or <2 x i64> %t2, %t3 237 %t5 = lshr <2 x i64> %t4, <i64 31, i64 31> 238 ret <2 x i64> %t5 239} 240 241define i32 @poison(i32 %x) { 242; CHECK-LABEL: @poison( 243; CHECK-NEXT: ret i32 poison 244; 245 %v = lshr i32 %x, poison 246 ret i32 %v 247} 248 249define i32 @poison2(i32 %x) { 250; CHECK-LABEL: @poison2( 251; CHECK-NEXT: ret i32 poison 252; 253 %v = ashr i32 %x, poison 254 ret i32 %v 255} 256 257define i32 @poison3(i32 %x) { 258; CHECK-LABEL: @poison3( 259; CHECK-NEXT: ret i32 poison 260; 261 %v = shl i32 %x, poison 262 ret i32 %v 263} 264 265define i32 @poison4(i32 %x) { 266; CHECK-LABEL: @poison4( 267; CHECK-NEXT: ret i32 poison 268; 269 %v = lshr i32 poison, %x 270 ret i32 %v 271} 272 273define i32 @poison5(i32 %x) { 274; CHECK-LABEL: @poison5( 275; CHECK-NEXT: ret i32 poison 276; 277 %v = ashr i32 poison, %x 278 ret i32 %v 279} 280 281define i32 @poison6(i32 %x) { 282; CHECK-LABEL: @poison6( 283; CHECK-NEXT: ret i32 poison 284; 285 %v = shl i32 poison, %x 286 ret i32 %v 287} 288 289define i32 @all_ones_left_right(i32 %x) { 290; CHECK-LABEL: @all_ones_left_right( 291; CHECK-NEXT: ret i32 -1 292; 293 %left = shl i32 -1, %x 294 %right = ashr i32 %left, %x 295 ret i32 %right 296} 297 298define <2 x i7> @all_ones_left_right_splat(<2 x i7> %x) { 299; CHECK-LABEL: @all_ones_left_right_splat( 300; CHECK-NEXT: ret <2 x i7> splat (i7 -1) 301; 302 %left = shl <2 x i7> <i7 -1, i7 -1>, %x 303 %right = ashr <2 x i7> %left, %x 304 ret <2 x i7> %right 305} 306 307; Poison could propagate, but undef must not. 308 309define <3 x i7> @all_ones_left_right_splat_undef_elt(<3 x i7> %x) { 310; CHECK-LABEL: @all_ones_left_right_splat_undef_elt( 311; CHECK-NEXT: [[LEFT:%.*]] = shl <3 x i7> <i7 undef, i7 -1, i7 undef>, [[X:%.*]] 312; CHECK-NEXT: [[RIGHT:%.*]] = ashr <3 x i7> [[LEFT]], [[X]] 313; CHECK-NEXT: ret <3 x i7> [[RIGHT]] 314; 315 %left = shl <3 x i7> <i7 undef, i7 -1, i7 undef>, %x 316 %right = ashr <3 x i7> %left, %x 317 ret <3 x i7> %right 318} 319 320define <3 x i7> @all_ones_left_right_splat_poison__elt(<3 x i7> %x) { 321; CHECK-LABEL: @all_ones_left_right_splat_poison__elt( 322; CHECK-NEXT: ret <3 x i7> splat (i7 -1) 323; 324 %left = shl <3 x i7> <i7 poison, i7 -1, i7 poison>, %x 325 %right = ashr <3 x i7> %left, %x 326 ret <3 x i7> %right 327} 328 329; negative test - must have -1 330 331define i32 @almost_all_ones_left_right(i32 %x) { 332; CHECK-LABEL: @almost_all_ones_left_right( 333; CHECK-NEXT: [[LEFT:%.*]] = shl i32 -2, [[X:%.*]] 334; CHECK-NEXT: [[RIGHT:%.*]] = ashr i32 [[LEFT]], [[X]] 335; CHECK-NEXT: ret i32 [[RIGHT]] 336; 337 %left = shl i32 -2, %x 338 %right = ashr i32 %left, %x 339 ret i32 %right 340} 341 342; negative test - must have same shift amount 343 344define i32 @all_ones_left_right_not_same_shift(i32 %x, i32 %y) { 345; CHECK-LABEL: @all_ones_left_right_not_same_shift( 346; CHECK-NEXT: [[LEFT:%.*]] = shl i32 -1, [[X:%.*]] 347; CHECK-NEXT: [[RIGHT:%.*]] = ashr i32 [[LEFT]], [[Y:%.*]] 348; CHECK-NEXT: ret i32 [[RIGHT]] 349; 350 %left = shl i32 -1, %x 351 %right = ashr i32 %left, %y 352 ret i32 %right 353} 354 355; shift by splat of bitwidth or more is poison 356 357define <vscale x 4 x i16> @lshr_scalable_overshift(<vscale x 4 x i16> %va) { 358; CHECK-LABEL: @lshr_scalable_overshift( 359; CHECK-NEXT: ret <vscale x 4 x i16> poison 360; 361 %vc = lshr <vscale x 4 x i16> %va, splat (i16 16) 362 ret <vscale x 4 x i16> %vc 363} 364 365; shl nsw+nuw is 0 366define i8 @shl_nsw_nuw_7_eq_0(i8 %x) { 367; CHECK-LABEL: @shl_nsw_nuw_7_eq_0( 368; CHECK-NEXT: ret i8 0 369; 370 %y = shl nsw nuw i8 %x, 7 371 ret i8 %y 372} 373 374; Make sure we match the element width 375define <2 x i8> @shl_vec_nsw_nuw_7_eq_0(<2 x i8> %x) { 376; CHECK-LABEL: @shl_vec_nsw_nuw_7_eq_0( 377; CHECK-NEXT: ret <2 x i8> zeroinitializer 378; 379 %y = shl nsw nuw <2 x i8> %x, <i8 7, i8 7> 380 ret <2 x i8> %y 381} 382 383; negative test (missing nuw) 384define i8 @shl_nsw_7_fail_missing_nuw(i8 %x) { 385; CHECK-LABEL: @shl_nsw_7_fail_missing_nuw( 386; CHECK-NEXT: [[Y:%.*]] = shl nsw i8 [[X:%.*]], 7 387; CHECK-NEXT: ret i8 [[Y]] 388; 389 %y = shl nsw i8 %x, 7 390 ret i8 %y 391} 392 393; negative test (missing nsw) 394define i8 @shl_nuw_7_fail_missing_nsw(i8 %x) { 395; CHECK-LABEL: @shl_nuw_7_fail_missing_nsw( 396; CHECK-NEXT: [[Y:%.*]] = shl nuw i8 [[X:%.*]], 7 397; CHECK-NEXT: ret i8 [[Y]] 398; 399 %y = shl nuw i8 %x, 7 400 ret i8 %y 401} 402 403; negative test (shift value != bitwdth - 1) 404define i8 @shl_nsw_nuw_6_do_nothing(i8 %x) { 405; CHECK-LABEL: @shl_nsw_nuw_6_do_nothing( 406; CHECK-NEXT: [[Y:%.*]] = shl nuw nsw i8 [[X:%.*]], 6 407; CHECK-NEXT: ret i8 [[Y]] 408; 409 %y = shl nsw nuw i8 %x, 6 410 ret i8 %y 411} 412