xref: /llvm-project/llvm/test/Transforms/InstCombine/vector-urem.ll (revision 38fffa630ee80163dc65e759392ad29798905679) 
1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2; RUN: opt < %s -passes=instcombine -S | FileCheck %s
3
4define <4 x i32> @test_v4i32_splatconst_pow2(<4 x i32> %a0) {
5; CHECK-LABEL: @test_v4i32_splatconst_pow2(
6; CHECK-NEXT:    [[TMP1:%.*]] = and <4 x i32> [[A0:%.*]], splat (i32 1)
7; CHECK-NEXT:    ret <4 x i32> [[TMP1]]
8;
9  %1 = urem <4 x i32> %a0, <i32 2, i32 2, i32 2, i32 2>
10  ret <4 x i32> %1
11}
12
13define <4 x i32> @test_v4i32_const_pow2(<4 x i32> %a0) {
14; CHECK-LABEL: @test_v4i32_const_pow2(
15; CHECK-NEXT:    [[TMP1:%.*]] = and <4 x i32> [[A0:%.*]], <i32 0, i32 1, i32 3, i32 7>
16; CHECK-NEXT:    ret <4 x i32> [[TMP1]]
17;
18  %1 = urem <4 x i32> %a0, <i32 1, i32 2, i32 4, i32 8>
19  ret <4 x i32> %1
20}
21
22define <4 x i32> @test_v4i32_const_pow2_poison(<4 x i32> %a0) {
23; CHECK-LABEL: @test_v4i32_const_pow2_poison(
24; CHECK-NEXT:    ret <4 x i32> poison
25;
26  %1 = urem <4 x i32> %a0, <i32 1, i32 2, i32 4, i32 poison>
27  ret <4 x i32> %1
28}
29
30define <4 x i32> @test_v4i32_one(<4 x i32> %a0) {
31; CHECK-LABEL: @test_v4i32_one(
32; CHECK-NEXT:    [[TMP1:%.*]] = icmp ne <4 x i32> [[A0:%.*]], splat (i32 1)
33; CHECK-NEXT:    [[TMP2:%.*]] = zext <4 x i1> [[TMP1]] to <4 x i32>
34; CHECK-NEXT:    ret <4 x i32> [[TMP2]]
35;
36  %1 = urem <4 x i32> <i32 1, i32 1, i32 1, i32 1>, %a0
37  ret <4 x i32> %1
38}
39
40define <4 x i32> @test_v4i32_one_poison(<4 x i32> %a0) {
41; CHECK-LABEL: @test_v4i32_one_poison(
42; CHECK-NEXT:    [[TMP1:%.*]] = icmp ne <4 x i32> [[A0:%.*]], splat (i32 1)
43; CHECK-NEXT:    [[TMP2:%.*]] = zext <4 x i1> [[TMP1]] to <4 x i32>
44; CHECK-NEXT:    ret <4 x i32> [[TMP2]]
45;
46  %1 = urem <4 x i32> <i32 1, i32 1, i32 1, i32 poison>, %a0
47  ret <4 x i32> %1
48}
49
50define <4 x i32> @test_v4i32_negconstsplat(<4 x i32> %a0) {
51; CHECK-LABEL: @test_v4i32_negconstsplat(
52; CHECK-NEXT:    [[A0_FR:%.*]] = freeze <4 x i32> [[A0:%.*]]
53; CHECK-NEXT:    [[TMP1:%.*]] = icmp ult <4 x i32> [[A0_FR]], splat (i32 -3)
54; CHECK-NEXT:    [[TMP2:%.*]] = add <4 x i32> [[A0_FR]], splat (i32 3)
55; CHECK-NEXT:    [[TMP3:%.*]] = select <4 x i1> [[TMP1]], <4 x i32> [[A0_FR]], <4 x i32> [[TMP2]]
56; CHECK-NEXT:    ret <4 x i32> [[TMP3]]
57;
58  %1 = urem <4 x i32> %a0, <i32 -3, i32 -3, i32 -3, i32 -3>
59  ret <4 x i32> %1
60}
61
62define <4 x i32> @test_v4i32_negconst(<4 x i32> %a0) {
63; CHECK-LABEL: @test_v4i32_negconst(
64; CHECK-NEXT:    [[A0_FR:%.*]] = freeze <4 x i32> [[A0:%.*]]
65; CHECK-NEXT:    [[TMP1:%.*]] = icmp ult <4 x i32> [[A0_FR]], <i32 -3, i32 -5, i32 -7, i32 -9>
66; CHECK-NEXT:    [[TMP2:%.*]] = add <4 x i32> [[A0_FR]], <i32 3, i32 5, i32 7, i32 9>
67; CHECK-NEXT:    [[TMP3:%.*]] = select <4 x i1> [[TMP1]], <4 x i32> [[A0_FR]], <4 x i32> [[TMP2]]
68; CHECK-NEXT:    ret <4 x i32> [[TMP3]]
69;
70  %1 = urem <4 x i32> %a0, <i32 -3, i32 -5, i32 -7, i32 -9>
71  ret <4 x i32> %1
72}
73
74define <4 x i32> @test_v4i32_negconst_poison(<4 x i32> %a0) {
75; CHECK-LABEL: @test_v4i32_negconst_poison(
76; CHECK-NEXT:    ret <4 x i32> poison
77;
78  %1 = urem <4 x i32> %a0, <i32 -3, i32 -5, i32 -7, i32 poison>
79  ret <4 x i32> %1
80}
81