xref: /llvm-project/llvm/test/Transforms/InstCombine/vector-trunc.ll (revision 38fffa630ee80163dc65e759392ad29798905679) 
1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2; RUN: opt < %s -passes=instcombine -S | FileCheck %s
3
4define <4 x i16> @trunc_add_nsw(<4 x i32> %0) {
5; CHECK-LABEL: @trunc_add_nsw(
6; CHECK-NEXT:    [[TMP2:%.*]] = ashr <4 x i32> [[TMP0:%.*]], splat (i32 17)
7; CHECK-NEXT:    [[TMP3:%.*]] = trunc nsw <4 x i32> [[TMP2]] to <4 x i16>
8; CHECK-NEXT:    [[TMP4:%.*]] = add nsw <4 x i16> [[TMP3]], splat (i16 1)
9; CHECK-NEXT:    ret <4 x i16> [[TMP4]]
10;
11  %2 = ashr <4 x i32> %0, <i32 17, i32 17, i32 17, i32 17>
12  %3 = trunc <4 x i32> %2 to <4 x i16>
13  %4 = add <4 x i16> %3, <i16 1, i16 1, i16 1, i16 1>
14  ret <4 x i16> %4
15}
16
17define <4 x i16> @trunc_add_no_nsw(<4 x i32> %0) {
18; CHECK-LABEL: @trunc_add_no_nsw(
19; CHECK-NEXT:    [[TMP2:%.*]] = lshr <4 x i32> [[TMP0:%.*]], splat (i32 16)
20; CHECK-NEXT:    [[TMP3:%.*]] = trunc nuw <4 x i32> [[TMP2]] to <4 x i16>
21; CHECK-NEXT:    [[TMP4:%.*]] = add <4 x i16> [[TMP3]], splat (i16 1)
22; CHECK-NEXT:    ret <4 x i16> [[TMP4]]
23;
24  %2 = ashr <4 x i32> %0, <i32 16, i32 16, i32 16, i32 16>
25  %3 = trunc <4 x i32> %2 to <4 x i16>
26  %4 = add <4 x i16> %3, <i16 1, i16 1, i16 1, i16 1>
27  ret <4 x i16> %4
28}
29
30define <4 x i16> @trunc_add_mixed(<4 x i32> %0) {
31; CHECK-LABEL: @trunc_add_mixed(
32; CHECK-NEXT:    [[TMP2:%.*]] = ashr <4 x i32> [[TMP0:%.*]], <i32 17, i32 16, i32 17, i32 16>
33; CHECK-NEXT:    [[TMP3:%.*]] = trunc <4 x i32> [[TMP2]] to <4 x i16>
34; CHECK-NEXT:    [[TMP4:%.*]] = add <4 x i16> [[TMP3]], splat (i16 1)
35; CHECK-NEXT:    ret <4 x i16> [[TMP4]]
36;
37  %2 = ashr <4 x i32> %0, <i32 17, i32 16, i32 17, i32 16>
38  %3 = trunc <4 x i32> %2 to <4 x i16>
39  %4 = add <4 x i16> %3, <i16 1, i16 1, i16 1, i16 1>
40  ret <4 x i16> %4
41}
42